From 577f84d9d232138e3af87c17bb5cd0d1a2ddb185 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 6 Dec 2021 10:15:40 +0100 Subject: [PATCH] fixed wrong signal to inhibit TX --- media_interfaces/sync/med_sync_control_RS.vhd | 20 +++++----- media_interfaces/sync/rx_rsl.vhd | 40 +++++++++---------- .../{rx_rsl_ORIG.vhd => rx_rsl_WRONG.vhd} | 40 +++++++++---------- 3 files changed, 50 insertions(+), 50 deletions(-) rename media_interfaces/sync/{rx_rsl_ORIG.vhd => rx_rsl_WRONG.vhd} (92%) diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index a46bdef..61bf273 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -235,7 +235,7 @@ begin SEND_RST_IN => TX_RST_IN, SEND_RST_WORD_IN => TX_RST_WORD_IN, -- link status signals, internally synced - LINK_TX_READY_IN => '0', -- BUG + LINK_TX_READY_IN => LINK_TX_READY_IN, LINK_RX_READY_IN => link_rx_ready_i, LINK_HALF_DONE_IN => link_half_done_i, LINK_FULL_DONE_IN => link_full_done_i, @@ -289,15 +289,15 @@ begin else x"7"; -- TEST_LINE signals - DEBUG_OUT(3 downto 0) <= rx_fsm_state; - DEBUG_OUT(4) <= RX_LOS_IN; - DEBUG_OUT(5) <= RX_CDR_LOL_IN; - DEBUG_OUT(6) <= TX_PLL_LOL_IN; - DEBUG_OUT(7) <= LINK_TX_READY_IN; - DEBUG_OUT(8) <= link_rx_ready_i; - DEBUG_OUT(9) <= is_wap_zero_i; - DEBUG_OUT(10) <= link_half_done_i; - DEBUG_OUT(11) <= link_full_done_i; + DEBUG_OUT(3 downto 0) <= rx_fsm_state when rising_edge(CLK_REF); + DEBUG_OUT(4) <= RX_LOS_IN when rising_edge(CLK_REF); + DEBUG_OUT(5) <= RX_CDR_LOL_IN when rising_edge(CLK_REF); + DEBUG_OUT(6) <= TX_PLL_LOL_IN when rising_edge(CLK_REF); + DEBUG_OUT(7) <= LINK_TX_READY_IN when rising_edge(CLK_REF); + DEBUG_OUT(8) <= link_rx_ready_i when rising_edge(CLK_REF); + DEBUG_OUT(9) <= is_wap_zero_i when rising_edge(CLK_REF); + DEBUG_OUT(10) <= link_half_done_i when rising_edge(CLK_REF); + DEBUG_OUT(11) <= link_full_done_i when rising_edge(CLK_REF); DEBUG_OUT(12) <= '0'; DEBUG_OUT(13) <= '0'; DEBUG_OUT(14) <= '0'; diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd index 019a903..91cfdca 100644 --- a/media_interfaces/sync/rx_rsl.vhd +++ b/media_interfaces/sync/rx_rsl.vhd @@ -42,8 +42,8 @@ architecture rx_rsl_arc of rx_rsl is signal cnt : unsigned(31 downto 0); type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, - CHECK_WAP, APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, - TEST_RXPCS, NORMAL_OP); + APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, + CHECK_WAP, NORMAL_OP); signal rx_sm : rx_sm_state; @@ -131,27 +131,14 @@ begin else if( cnt = Tcdr ) then cnt <= (others => '0'); - rx_sm <= CHECK_WAP; + rx_sm <= APPLY_RXPCS_RST; else cnt <= cnt + 1; end if; end if; - -- THIS STATE CAN BE ASSIMILATED INTO TEST_CDR - when CHECK_WAP => - STATE_OUT <= x"4"; - RX_SERDES_RST_OUT <= '0'; - RX_PCS_RST_OUT <= '1'; -- really? - LINK_RX_READY_OUT <= '0'; - cnt <= (others => '0'); - if( WAP_ZERO_IN = '1' ) then - rx_sm <= NORMAL_OP; - else - rx_sm <= APPLY_CDR_RST; - end if; - when APPLY_RXPCS_RST => - STATE_OUT <= x"5"; + STATE_OUT <= x"4"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; @@ -163,7 +150,7 @@ begin end if; when WAIT_RXPCS_LOCK => - STATE_OUT <= x"6"; + STATE_OUT <= x"5"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; @@ -175,7 +162,7 @@ begin end if; when TEST_RXPCS => - STATE_OUT <= x"7"; + STATE_OUT <= x"6"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; @@ -185,11 +172,24 @@ begin else if( cnt = Tviol ) then cnt <= (others => '0'); - rx_sm <= NORMAL_OP; + rx_sm <= CHECK_WAP; else cnt <= cnt + 1; end if; end if; + + when CHECK_WAP => + STATE_OUT <= x"7"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + cnt <= (others => '0'); + if( WAP_ZERO_IN = '1' ) then + rx_sm <= NORMAL_OP; + else +-- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK + rx_sm <= APPLY_CDR_RST; + end if; when NORMAL_OP => STATE_OUT <= x"8"; diff --git a/media_interfaces/sync/rx_rsl_ORIG.vhd b/media_interfaces/sync/rx_rsl_WRONG.vhd similarity index 92% rename from media_interfaces/sync/rx_rsl_ORIG.vhd rename to media_interfaces/sync/rx_rsl_WRONG.vhd index 0e3cabf..019a903 100644 --- a/media_interfaces/sync/rx_rsl_ORIG.vhd +++ b/media_interfaces/sync/rx_rsl_WRONG.vhd @@ -42,8 +42,8 @@ architecture rx_rsl_arc of rx_rsl is signal cnt : unsigned(31 downto 0); type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, - APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, - CHECK_WAP, TX_SYNC, NORMAL_OP); + CHECK_WAP, APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, + TEST_RXPCS, NORMAL_OP); signal rx_sm : rx_sm_state; @@ -131,15 +131,28 @@ begin else if( cnt = Tcdr ) then cnt <= (others => '0'); - rx_sm <= APPLY_RXPCS_RST; + rx_sm <= CHECK_WAP; else cnt <= cnt + 1; end if; end if; - when APPLY_RXPCS_RST => + -- THIS STATE CAN BE ASSIMILATED INTO TEST_CDR + when CHECK_WAP => STATE_OUT <= x"4"; RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; -- really? + LINK_RX_READY_OUT <= '0'; + cnt <= (others => '0'); + if( WAP_ZERO_IN = '1' ) then + rx_sm <= NORMAL_OP; + else + rx_sm <= APPLY_CDR_RST; + end if; + + when APPLY_RXPCS_RST => + STATE_OUT <= x"5"; + RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; if( cnt = Tshort ) then @@ -150,7 +163,7 @@ begin end if; when WAIT_RXPCS_LOCK => - STATE_OUT <= x"5"; + STATE_OUT <= x"6"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; @@ -162,7 +175,7 @@ begin end if; when TEST_RXPCS => - STATE_OUT <= x"6"; + STATE_OUT <= x"7"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; @@ -172,24 +185,11 @@ begin else if( cnt = Tviol ) then cnt <= (others => '0'); - rx_sm <= CHECK_WAP; + rx_sm <= NORMAL_OP; else cnt <= cnt + 1; end if; end if; - - when CHECK_WAP => - STATE_OUT <= x"7"; - RX_SERDES_RST_OUT <= '0'; - RX_PCS_RST_OUT <= '0'; - LINK_RX_READY_OUT <= '0'; - cnt <= (others => '0'); - if( WAP_ZERO_IN = '1' ) then - rx_sm <= NORMAL_OP; - else --- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK - rx_sm <= APPLY_CDR_RST; - end if; when NORMAL_OP => STATE_OUT <= x"8"; -- 2.43.0