From 5834bc66a37d83574f8fa879c94e814ae1d5b247 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sun, 20 Mar 2022 10:30:56 +0100 Subject: [PATCH] SCI write bug fixed, some minor changes --- media_interfaces/sync/med_sync_control_RS.vhd | 19 +++++++++++-------- media_interfaces/sync/sci_reader_RS.vhd | 19 ++----------------- trb_net16_hub_func.vhd | 2 +- trb_net16_hub_streaming_port_sctrl_cts.vhd | 4 ++-- 4 files changed, 16 insertions(+), 28 deletions(-) diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 3596517..434f34d 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -102,6 +102,7 @@ architecture med_sync_control_arch of med_sync_control_RS is signal link_status_qsys : std_logic_vector(3 downto 0); signal link_active_i : std_logic; signal link_active_qref : std_logic; + signal link_active_qsys : std_logic; -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; @@ -275,13 +276,13 @@ begin STAT_RESET(3 downto 0) <= rx_fsm_state; STAT_RESET(31 downto 4) <= (others => '0'); - media_med2int_i.stat_op(15) <= '0'; - media_med2int_i.stat_op(14) <= '0'; --reset MUX - media_med2int_i.stat_op(13) <= '0'; --not link_full_done_qsys; --make trbnet reset - media_med2int_i.stat_op(12) <= '0'; - media_med2int_i.stat_op(11) <= led_tx; - media_med2int_i.stat_op(10) <= led_rx or last_led_rx; - media_med2int_i.stat_op(9) <= led_ok; + media_med2int_i.stat_op(15) <= '0'; -- "send reset" + media_med2int_i.stat_op(14) <= not link_active_qsys; --'0'; -- "no signal" - reset IOMUX + media_med2int_i.stat_op(13) <= '0'; -- "reset trbnet" not link_full_done_qsys; --make trbnet reset + media_med2int_i.stat_op(12) <= '0'; -- "link error" + media_med2int_i.stat_op(11) <= led_tx; -- "LED TX" + media_med2int_i.stat_op(10) <= led_rx or last_led_rx; -- "LED RX" + media_med2int_i.stat_op(9) <= led_ok; -- "LED status" media_med2int_i.stat_op(8 downto 6) <= (others => '0'); media_med2int_i.stat_op(5) <= link_full_done_qsys; -- tx_allow media_med2int_i.stat_op(4) <= link_full_done_qsys; -- rx_allow @@ -293,18 +294,20 @@ begin SYNC_MEDIA_SIGS : entity work.signal_sync generic map( - WIDTH => 8, + WIDTH => 9, DEPTH => 3 ) port map( RESET => '0', CLK0 => CLK_SYS, CLK1 => CLK_SYS, + D_IN(8) => link_active_i, D_IN(7) => link_full_done_i, D_IN(6) => link_half_done_i, D_IN(5) => link_tx_ready_i, D_IN(4) => link_rx_ready_i, D_IN(3 downto 0) => link_status, + D_OUT(8) => link_active_qsys, D_OUT(7) => link_full_done_qsys, D_OUT(6) => link_half_done_qsys, D_OUT(5) => link_tx_ready_qsys, diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index d67f99d..08e67ac 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -45,10 +45,6 @@ signal sci_reg_i : std_logic; signal wa_position : std_logic_vector(15 downto 0); signal next_sci_wr : std_logic; ---signal txdata_q : std_logic_vector(7 downto 0); ---signal txack_q : std_logic; ---signal txnack_q : std_logic; - begin ------------------------------------------------ @@ -64,9 +60,7 @@ begin begin wait until rising_edge(CLK); BUS_TX.ack <= '0'; --- txack_q <= '0'; BUS_TX.nack <= '0'; --- txnack_q <= '0'; SCI_WR <= next_sci_wr; @@ -96,9 +90,7 @@ begin when SCTRL => if( sci_reg_i = '1' ) then BUS_TX.data <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))); --- txdata_q <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))); BUS_TX.ack <= '1'; --- txack_q <= '1'; next_sci_wr <= '0'; SCI_RD <= '0'; sci_state <= IDLE; @@ -106,15 +98,14 @@ begin sci_state <= SCTRL_WAIT; end if; when SCTRL_WAIT => + next_sci_wr <= '0'; sci_state <= SCTRL_WAIT2; when SCTRL_WAIT2 => sci_state <= SCTRL_FINISH; when SCTRL_FINISH => BUS_TX.data(7 downto 0) <= SCI_RDDATA; --- txdata_q <= SCI_RDDATA; BUS_TX.ack <= '1'; --- txack_q <= '1'; - next_sci_wr <= '0'; +-- next_sci_wr <= '0'; SCI_RD <= '0'; sci_state <= IDLE; when GET_WA => @@ -144,15 +135,9 @@ begin if( ((BUS_RX.read = '1') or (BUS_RX.write = '1')) and (sci_state /= IDLE) ) then BUS_TX.nack <= '1'; --- txnack_q <= '1'; BUS_TX.ack <= '0'; --- txack_q <= '0'; end if; --- -- should fix timing errors while keeping constraints --- BUS_TX.data(7 downto 0) <= txdata_q; --- BUS_TX.ack <= txack_q; --- BUS_TX.nack <= txnack_q; end process PROC_SCI_CTRL; WA_POS_OUT <= wa_position; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index ac82c27..4e1f3b2 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -521,7 +521,7 @@ component trb_net16_hub_streaming_port_sctrl_cts is INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := x"00000000_00000000_00000000_00000000" & x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00007077_00000000" & + x"00000000_00000000_000050FF_00000000" & x"FFFFFFFF_00000000_FFFFFFFF_FFFFFFFF" ); diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd index cee3c83..55aad6f 100644 --- a/trb_net16_hub_streaming_port_sctrl_cts.vhd +++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd @@ -253,7 +253,7 @@ signal my_address : std_logic_vector(15 downto 0); signal reset_i : std_logic; signal HUB_MED_CTRL_OP : std_logic_vector(mii*16-1 downto 0); -signal reset_i_mux_io : std_logic; +--signal reset_i_mux_io : std_logic; signal hub_make_network_reset : std_logic; -- signal hub_got_network_reset : std_logic; @@ -396,7 +396,7 @@ info_tx_ack_or_info_tx_wack <= info_tx.ack or info_tx.wack; begin if rising_edge(CLK) then reset_i <= RESET; - reset_i_mux_io <= RESET; --MED_STAT_OP(mii*16+14) or +-- reset_i_mux_io <= RESET; --MED_STAT_OP(mii*16+14) or end if; end process; -- 2.43.0