From 5867d24532c6ba9d4b34570f10c6bc19db8172dc Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 28 Jun 2022 10:02:29 +0200 Subject: [PATCH] SFP LEDs added, cleanups started --- gbe_trb/base/gbe_med_interface_single_5G.vhd | 201 +++++++------------ gbe_trb/base/gbe_wrapper_single_5G.vhd | 8 +- 2 files changed, 76 insertions(+), 133 deletions(-) diff --git a/gbe_trb/base/gbe_med_interface_single_5G.vhd b/gbe_trb/base/gbe_med_interface_single_5G.vhd index f205668..b65506b 100644 --- a/gbe_trb/base/gbe_med_interface_single_5G.vhd +++ b/gbe_trb/base/gbe_med_interface_single_5G.vhd @@ -17,25 +17,23 @@ entity gbe_med_interface_single_5G is CLK_125_OUT : out std_logic; CLK_125_IN : in std_logic; CLK_125_RX_OUT : out std_logic; - -- MAC status and config MAC_READY_CONF_OUT : out std_logic; MAC_RECONF_IN : in std_logic; MAC_AN_READY_OUT : out std_logic; - -- MAC data interface MAC_FIFOAVAIL_IN : in std_logic; MAC_FIFOEOF_IN : in std_logic; MAC_FIFOEMPTY_IN : in std_logic; MAC_RX_FIFOFULL_IN : in std_logic; - + -- MAC TX interface MAC_TX_DATA_IN : in std_logic_vector(7 downto 0); MAC_TX_READ_OUT : out std_logic; MAC_TX_DISCRFRM_OUT : out std_logic; MAC_TX_STAT_EN_OUT : out std_logic; MAC_TX_STATS_OUT : out std_logic_vector(30 downto 0); MAC_TX_DONE_OUT : out std_logic; - + -- MAC RX interface MAC_RX_FIFO_ERR_OUT : out std_logic; MAC_RX_STATS_OUT : out std_logic_vector(31 downto 0); MAC_RX_DATA_OUT : out std_logic_vector(7 downto 0); @@ -43,7 +41,6 @@ entity gbe_med_interface_single_5G is MAC_RX_STAT_EN_OUT : out std_logic; MAC_RX_EOF_OUT : out std_logic; MAC_RX_ERROR_OUT : out std_logic; - --SFP Connection SD_RXD_P_IN : in std_logic; SD_RXD_N_IN : in std_logic; @@ -52,7 +49,10 @@ entity gbe_med_interface_single_5G is SD_PRSNT_N_IN : in std_logic; SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic; -- SFP disable - + SD_LED_GREEN_OUT : out std_logic; + SD_LED_YELLOW_OUT : out std_logic; + SD_LED_RED_OUT : out std_logic; + -- Debug DEBUG_OUT : out std_logic_vector(255 downto 0) ); end entity gbe_med_interface_single_5G; @@ -209,13 +209,9 @@ architecture RTL of gbe_med_interface_single_5G is signal xmit : std_logic_vector(0 downto 0); signal sd_tx_correct_disp : std_logic_vector(0 downto 0); signal sd_rx_data : std_logic_vector(7 downto 0); --- signal sd_rx_data_q : std_logic_vector(7 downto 0); signal sd_rx_kcntl : std_logic_vector(0 downto 0); --- signal sd_rx_kcntl_q : std_logic_vector(0 downto 0); signal sd_rx_disp_error : std_logic_vector(0 downto 0); --- signal sd_rx_disp_error_q : std_logic_vector(0 downto 0); signal sd_rx_cv_error : std_logic_vector(0 downto 0); --- signal sd_rx_cv_error_q : std_logic_vector(0 downto 0); signal lsm_status : std_logic; signal rx_clk_en : std_logic; signal tx_clk_en : std_logic; @@ -227,6 +223,7 @@ architecture RTL of gbe_med_interface_single_5G is signal mr_restart_an : std_logic; signal mr_adv_ability : std_logic_vector(15 downto 0); signal mr_an_enable : std_logic; + signal an_link_ok : std_logic; signal pcs_rxd : std_logic_vector(7 downto 0); signal pcs_rx_en : std_logic; signal pcs_rx_er : std_logic; @@ -241,7 +238,7 @@ architecture RTL of gbe_med_interface_single_5G is signal tsm_hdata : std_logic_vector(7 downto 0); signal tsm_haddr : std_logic_vector(7 downto 0); - signal synced_rst, ff : std_logic; + signal synced_rst : std_logic; signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic; @@ -263,112 +260,35 @@ architecture RTL of gbe_med_interface_single_5G is signal pulse : std_logic; signal pulse2 : std_logic; - signal fake : std_logic_vector(0 downto 0); - --- type statetype is (S_KOMMA, S_DATA, S_CH, S_CL); --- signal CSTATE : statetype; -- current state of lsm --- signal NSTATE : statetype; -- next state of lsm --- signal counter : unsigned(15 downto 0); --- --- attribute syn_preserve : boolean; --- attribute syn_keep : boolean; --- --- attribute syn_preserve of sd_rx_data : signal is true; --- attribute syn_keep of sd_rx_data : signal is true; --- attribute syn_preserve of sd_rx_kcntl : signal is true; --- attribute syn_keep of sd_rx_kcntl : signal is true; --- attribute syn_preserve of sd_tx_data : signal is true; --- attribute syn_keep of sd_tx_data : signal is true; --- attribute syn_preserve of sd_tx_kcntl : signal is true; --- attribute syn_keep of sd_tx_kcntl : signal is true; - begin -- We allow only one GbE in ECP5 for now assert not (LINKS_ACTIVE = b"0000") report "Error: no GbE interface selected" severity error; --- -- State machine clocked process --- THE_FSM_PROC: process( CLK_125_IN ) --- begin --- if( rising_edge(CLK_125_IN) ) then --- CSTATE <= NSTATE; --- end if; --- end process THE_FSM_PROC; --- --- THE_FSM_DECODE_PROC: process( CSTATE ) --- begin --- case CSTATE is --- when S_KOMMA => --- NSTATE <= S_DATA; --- sd_tx_data <= x"bc"; --- sd_tx_kcntl(0) <= '1'; --- when S_DATA => --- NSTATE <= S_CH; --- sd_tx_data <= x"b5"; --- sd_tx_kcntl(0) <= '0'; --- when S_CH => --- NSTATE <= S_CL; --- sd_tx_data <= std_logic_vector(counter(15 downto 8)); --- sd_tx_kcntl(0) <= '0'; --- when S_CL => --- NSTATE <= S_KOMMA; --- sd_tx_data <= std_logic_vector(counter(7 downto 0)); --- sd_tx_kcntl(0) <= '0'; --- when others => --- NSTATE <= S_KOMMA; --- sd_tx_data <= x"bc"; --- sd_tx_kcntl(0) <= '1'; --- end case; --- end process THE_FSM_DECODE_PROC; --- --- THE_COUNTER_PROC: process( CLK_125_IN ) --- begin --- if( rising_edge(CLK_125_IN) ) then --- if( CSTATE = S_KOMMA ) then --- counter <= counter + 1; --- end if; --- end if; --- end process THE_COUNTER_PROC; - -------------------------------------------------------------------- -------------------------------------------------------------------- -- debug(255 downto 0) <= (others => '0'); - DEBUG_OUT <= debug; - + DEBUG_OUT <= debug; -- debug(19..0) are on INTCOM -- debug(33..20) are on GPIO -- 33 = CLK2 (white/green) -- 32 = CLK1 (white/blue) -------------------------------------------------------------------- -------------------------------------------------------------------- - - rst_dual <= not GSR_N; --- reset_sync : process(GSR_N, CLK_125_IN) +-- reset_sync: process( CLK_125_IN ) -- begin --- if (GSR_N = '0') then --- ff <= '0'; --- synced_rst <= '0'; --- elsif rising_edge(CLK_125_IN) then --- ff <= '1'; --- synced_rst <= ff; --- end if; --- end process reset_sync; - - reset_sync: process( CLK_125_IN ) - begin - if( rising_edge(CLK_125_IN) ) then +-- if( rising_edge(CLK_125_IN) ) then synced_rst <= GSR_N; - end if; - end process reset_sync; +-- end if; +-- end process reset_sync; + rst_dual <= not GSR_N; SD_TXDIS_OUT <= '0'; CLK_125_OUT <= CLK_125_IN; CLK_125_RX_OUT <= sd_rx_clk; - fake(0) <= '0'; - gbe_serdes: entity serdes_gbe port map( -- external I/Os @@ -432,9 +352,9 @@ begin CV_IN => sd_rx_cv_error(0), LSM_IN => lsm_status, LOS_IN => rx_los_low, - WAP_ZERO_IN => '1', -- not used here + WAP_ZERO_IN => '1', -- not needed here -- outputs - WAP_REQ_OUT => open, -- not used here + WAP_REQ_OUT => open, -- not needed here RX_SERDES_RST_OUT => rx_serdes_rst, -- CLK_REF based RX_PCS_RST_OUT => rx_pcs_rst, -- CLK_REF based LINK_RX_READY_OUT => link_rx_ready, -- CLK_REF based @@ -453,38 +373,35 @@ begin D_OUT(0) => rx_pcs_rst_q, D_OUT(1) => rx_serdes_rst_q ); - - -- register stage to relax timing --- sd_rx_data_q <= sd_rx_data when rising_edge(sd_rx_clk); --- sd_rx_kcntl_q <= sd_rx_kcntl when rising_edge(sd_rx_clk); --- sd_rx_disp_error_q <= sd_rx_disp_error_q when rising_edge(sd_rx_clk); --- sd_rx_cv_error_q <= sd_rx_cv_error_q when rising_edge(sd_rx_clk); - -- "Good" debugging pins - debug(7 downto 0) <= sd_tx_data; - debug(15 downto 8) <= sd_rx_data; - debug(16) <= sd_tx_kcntl(0); - debug(17) <= sd_rx_kcntl(0); - debug(18) <= '0'; - debug(19) <= '0'; - -- "Bad" debugging pins - debug(20) <= pll_lol; - debug(21) <= rx_cdr_lol; - debug(22) <= rx_los_low; - debug(23) <= sd_rx_cv_error(0); - debug(24) <= lsm_status; - debug(25) <= mr_main_reset; - debug(26) <= mr_an_enable; - debug(27) <= mr_restart_an; - debug(28) <= mr_page_rx; - debug(29) <= an_complete; - debug(30) <= '0'; - debug(31) <= '0'; - debug(32) <= link_rx_ready; - debug(33) <= link_tx_ready; --- debug(125) <= sd_rx_data(0) or sd_rx_data(1) or sd_rx_data(2) or sd_rx_data(3) or --- sd_rx_data(4) or sd_rx_data(5) or sd_rx_data(6) or sd_rx_data(7) or --- sd_rx_kcntl(0); + SD_LED_GREEN_OUT <= '1' when (link_tx_ready = '1') and (link_rx_ready = '1') and (an_complete = '1') + else '0'; + SD_LED_YELLOW_OUT <= '1' when (pcs_tx_en = '1') or (pcs_rx_en = '1') + else '0'; + SD_LED_RED_OUT <= '0'; + +-- -- "Good" debugging pins +-- debug(7 downto 0) <= sd_tx_data; +-- debug(15 downto 8) <= sd_rx_data; +-- debug(16) <= sd_tx_kcntl(0); +-- debug(17) <= sd_rx_kcntl(0); +-- debug(18) <= '0'; +-- debug(19) <= '0'; +-- -- "Bad" debugging pins +-- debug(20) <= pll_lol; +-- debug(21) <= rx_cdr_lol; +-- debug(22) <= rx_los_low; +-- debug(23) <= sd_rx_cv_error(0); +-- debug(24) <= lsm_status; +-- debug(25) <= mr_main_reset; +-- debug(26) <= mr_an_enable; +-- debug(27) <= mr_restart_an; +-- debug(28) <= mr_page_rx; +-- debug(29) <= an_complete; +-- debug(30) <= an_link_ok; +-- debug(31) <= '0'; +-- debug(32) <= link_rx_ready; +-- debug(33) <= link_tx_ready; debug(126) <= link_rx_ready; debug(127) <= link_tx_ready; @@ -503,7 +420,7 @@ begin rx_compensation_err => open, ctc_drop_flag => open, ctc_add_flag => open, - an_link_ok => open, + an_link_ok => an_link_ok, --open, -- MAC interface tx_clk_125 => CLK_125_IN, tx_clock_enable_source => tx_clk_en, @@ -542,7 +459,30 @@ begin ); MAC_AN_READY_OUT <= an_complete; - + + -- "Good" debugging pins + debug(7 downto 0) <= pcs_txd; + debug(15 downto 8) <= pcs_rxd; + debug(16) <= pcs_tx_en; + debug(17) <= pcs_tx_er; + debug(18) <= pcs_rx_en; + debug(19) <= pcs_rx_er; + -- "Bad" debugging pins + debug(20) <= pll_lol; + debug(21) <= rx_cdr_lol; + debug(22) <= rx_los_low; + debug(23) <= sd_rx_cv_error(0); + debug(24) <= lsm_status; + debug(25) <= mr_main_reset; + debug(26) <= mr_an_enable; + debug(27) <= mr_restart_an; + debug(28) <= mr_page_rx; + debug(29) <= an_complete; + debug(30) <= an_link_ok; + debug(31) <= '0'; + debug(32) <= link_rx_ready; + debug(33) <= link_tx_ready; + --- SIMPLE --- operational_rate <= b"10"; --- /SIMPLE --- @@ -562,7 +502,6 @@ begin mr_main_reset <= rst_dual; mr_restart_an <= pulse; mr_an_enable <= link_rx_ready; - -- mr_adv_ability <= x"01a0"; mr_adv_ability <= x"0020"; @@ -574,9 +513,7 @@ begin end process SYNC_PROC; pulse <= not delay_q(7) and delay_q(6); - pulse2 <= not delay_q(3) and delay_q(0); - --- /SIMPLE --- -- u0_ri : register_interface_hb port map( diff --git a/gbe_trb/base/gbe_wrapper_single_5G.vhd b/gbe_trb/base/gbe_wrapper_single_5G.vhd index f2fff21..921111c 100644 --- a/gbe_trb/base/gbe_wrapper_single_5G.vhd +++ b/gbe_trb/base/gbe_wrapper_single_5G.vhd @@ -42,7 +42,10 @@ entity gbe_wrapper_single_5G is SD_PRSNT_N_IN : in std_logic; SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic; -- SFP disable - + SD_LED_GREEN_OUT : out std_logic; + SD_LED_YELLOW_OUT : out std_logic; + SD_LED_RED_OUT : out std_logic; + -- TRIGGER_IN : in std_logic; -- for debug purpose only -- CTS interface CTS_NUMBER_IN : in std_logic_vector(15 downto 0); @@ -277,6 +280,9 @@ begin SD_PRSNT_N_IN => SD_PRSNT_N_IN, SD_LOS_IN => SD_LOS_IN, SD_TXDIS_OUT => SD_TXDIS_OUT, + SD_LED_GREEN_OUT => SD_LED_GREEN_OUT, + SD_LED_YELLOW_OUT => SD_LED_YELLOW_OUT, + SD_LED_RED_OUT => SD_LED_RED_OUT, DEBUG_OUT => debug --open ); -- 2.43.0