From 589272c987ed6bd6a8d5f30819b3c3406d2c44c4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 22 Jan 2016 13:37:51 +0100 Subject: [PATCH] Fixing some mistakes in the DiRich lpf --- dirich/config.vhd | 2 +- dirich/dirich.lpf | 2 +- dirich/dirich.vhd | 31 +++++++------- pinout/dirich.lpf | 104 +++++++++++++++++++++++----------------------- 4 files changed, 69 insertions(+), 70 deletions(-) diff --git a/dirich/config.vhd b/dirich/config.vhd index 905c547..a16a010 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -37,7 +37,7 @@ package config is --set to 0 for backplane serdes, set to 3 for front SFP serdes constant INCLUDE_UART : integer := c_NO; - constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_NO; constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf index 303b227..18434dc 100644 --- a/dirich/dirich.lpf +++ b/dirich/dirich.lpf @@ -24,7 +24,7 @@ BLOCK PATH TO PORT "LED*"; BLOCK PATH TO PORT "PROGRAMN"; BLOCK PATH TO PORT "TEMPSENS"; BLOCK PATH FROM PORT "TEMPSENS"; -BLOCK PATH TO PORT "TEST_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 3da0d3a..fa6e94d 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -37,10 +37,10 @@ entity dirich is FLASH_IN : out std_logic; FLASH_OUT : in std_logic; PROGRAMN : out std_logic; - TEMPSENS : inout std_logic; + TEMP_LINE : inout std_logic; --Test Connectors - TEST_LINE : out std_logic_vector(13 downto 0) + TEST_LINE : out std_logic_vector(14 downto 1) ); @@ -210,7 +210,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record BUS_MASTER_OUT => bus_master_out, BUS_MASTER_ACTIVE => bus_master_active, - ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_INOUT => TEMP_LINE, --Timing registers TIMERS_OUT => timer ); @@ -309,9 +309,9 @@ THE_PWM_GEN : entity work.pwm_generator --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- - - TEST_LINE(9 downto 0) <= hdr_io; - + TEST_LINE(10 downto 1) <= hdr_io; + TEST_LINE(14 downto 11) <= time_counter(31 downto 28); + --------------------------------------------------------------------------- -- LCD Data to display --------------------------------------------------------------------------- @@ -334,16 +334,15 @@ THE_PWM_GEN : entity work.pwm_generator --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- --- process begin --- wait until rising_edge(clk_sys); --- time_counter <= time_counter + 1; --- if reset_i = '1' then --- time_counter <= (others => '0'); --- end if; --- end process; - --- TEST_LINE <= med_stat_debug(15 downto 0); - + process begin + wait until rising_edge(clk_sys); + time_counter <= time_counter + 1; + if reset_i = '1' then + time_counter <= (others => '0'); + end if; + end process; + + end architecture; diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf index 55602cc..8f020b1 100644 --- a/pinout/dirich.lpf +++ b/pinout/dirich.lpf @@ -1,35 +1,35 @@ -LOCATE COMP "INPUT[0]" SITE "E5"; -LOCATE COMP "INPUT[1]" SITE "F4"; -LOCATE COMP "INPUT[2]" SITE "E4"; -LOCATE COMP "INPUT[3]" SITE "B5"; -LOCATE COMP "INPUT[4]" SITE "A4"; -LOCATE COMP "INPUT[5]" SITE "C4"; -LOCATE COMP "INPUT[6]" SITE "A3"; -LOCATE COMP "INPUT[7]" SITE "C3"; -LOCATE COMP "INPUT[8]" SITE "A2"; -LOCATE COMP "INPUT[9]" SITE "B2"; -LOCATE COMP "INPUT[10]" SITE "C1"; -LOCATE COMP "INPUT[11]" SITE "D2"; -LOCATE COMP "INPUT[12]" SITE "F2"; -LOCATE COMP "INPUT[13]" SITE "G3"; -LOCATE COMP "INPUT[14]" SITE "H4"; -LOCATE COMP "INPUT[15]" SITE "H5"; -LOCATE COMP "INPUT[16]" SITE "T19"; -LOCATE COMP "INPUT[17]" SITE "T20"; -LOCATE COMP "INPUT[18]" SITE "U19"; -LOCATE COMP "INPUT[19]" SITE "P20"; -LOCATE COMP "INPUT[20]" SITE "R16"; -LOCATE COMP "INPUT[21]" SITE "N19"; -LOCATE COMP "INPUT[22]" SITE "P19"; -LOCATE COMP "INPUT[23]" SITE "L18"; -LOCATE COMP "INPUT[24]" SITE "N18"; -LOCATE COMP "INPUT[25]" SITE "D18"; -LOCATE COMP "INPUT[26]" SITE "E16"; -LOCATE COMP "INPUT[27]" SITE "L16"; -LOCATE COMP "INPUT[28]" SITE "N16"; -LOCATE COMP "INPUT[29]" SITE "N17"; -LOCATE COMP "INPUT[30]" SITE "U16"; -LOCATE COMP "INPUT[31]" SITE "U18"; +LOCATE COMP "INPUT[1]" SITE "E5"; +LOCATE COMP "INPUT[2]" SITE "F4"; +LOCATE COMP "INPUT[3]" SITE "E4"; +LOCATE COMP "INPUT[4]" SITE "B5"; +LOCATE COMP "INPUT[5]" SITE "A4"; +LOCATE COMP "INPUT[6]" SITE "C4"; +LOCATE COMP "INPUT[7]" SITE "A3"; +LOCATE COMP "INPUT[8]" SITE "C3"; +LOCATE COMP "INPUT[9]" SITE "A2"; +LOCATE COMP "INPUT[10]" SITE "B2"; +LOCATE COMP "INPUT[11]" SITE "C1"; +LOCATE COMP "INPUT[12]" SITE "D2"; +LOCATE COMP "INPUT[13]" SITE "F2"; +LOCATE COMP "INPUT[14]" SITE "G3"; +LOCATE COMP "INPUT[15]" SITE "H4"; +LOCATE COMP "INPUT[16]" SITE "H5"; +LOCATE COMP "INPUT[17]" SITE "T19"; +LOCATE COMP "INPUT[18]" SITE "T20"; +LOCATE COMP "INPUT[19]" SITE "U19"; +LOCATE COMP "INPUT[20]" SITE "P20"; +LOCATE COMP "INPUT[21]" SITE "R16"; +LOCATE COMP "INPUT[22]" SITE "N19"; +LOCATE COMP "INPUT[23]" SITE "P19"; +LOCATE COMP "INPUT[24]" SITE "L18"; +LOCATE COMP "INPUT[25]" SITE "N18"; +LOCATE COMP "INPUT[26]" SITE "D18"; +LOCATE COMP "INPUT[27]" SITE "E16"; +LOCATE COMP "INPUT[28]" SITE "L16"; +LOCATE COMP "INPUT[29]" SITE "N16"; +LOCATE COMP "INPUT[30]" SITE "N17"; +LOCATE COMP "INPUT[31]" SITE "U16"; +LOCATE COMP "INPUT[32]" SITE "U18"; DEFINE PORT GROUP "INP_group" "INP*" ; IOBUF GROUP "INP_group" IO_TYPE=LVDS DIFFRESISTOR=OFF BANK_VCCIO=2.5; @@ -96,7 +96,7 @@ IOBUF PORT "ADC_SCLK" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; -LOCATE COMP "PROGRAMN" SITE "W3"; +LOCATE COMP "PROGRAMN" SITE "T1"; IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; LOCATE COMP "SIG[1]" SITE "N4"; @@ -109,33 +109,33 @@ DEFINE PORT GROUP "SIG_group" "SIG*" ; IOBUF GROUP "SIG_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; -LOCATE COMP "FLASH_CLK" SITE "U3"; +# LOCATE COMP "FLASH_CLK" SITE "U3"; LOCATE COMP "FLASH_CS" SITE "R2"; LOCATE COMP "FLASH_IN" SITE "W2"; LOCATE COMP "FLASH_OUT" SITE "V2"; -IOBUF PORT "FLASH_CS" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=3.3; -IOBUF PORT "FLASH_IN" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=3.3; -IOBUF PORT "FLASH_OUT" IO_TYPE=LVCMOS25 BANK_VCCIO=3.3; -IOBUF PORT "FLASH_CS" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_CLK" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_IN" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_OUT" IO_TYPE=LVTTL33 BANK_VCCIO=3.3; +IOBUF PORT "FLASH_CS" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; LOCATE COMP "TEMP_LINE" SITE "R1"; IOBUF PORT "TEMP_LINE" IO_TYPE=LVTTL33 DRIVE=8 BANK_VCCIO=3.3; -LOCATE COMP "TEST[1]" SITE "N3"; -LOCATE COMP "TEST[2]" SITE "M3"; -LOCATE COMP "TEST[3]" SITE "L3"; -LOCATE COMP "TEST[4]" SITE "K3"; -LOCATE COMP "TEST[5]" SITE "N2"; -LOCATE COMP "TEST[6]" SITE "J3"; -LOCATE COMP "TEST[7]" SITE "P1"; -LOCATE COMP "TEST[8]" SITE "L2"; -LOCATE COMP "TEST[9]" SITE "P2"; -LOCATE COMP "TEST[10]" SITE "L1"; -LOCATE COMP "TEST[11]" SITE "P3"; -LOCATE COMP "TEST[12]" SITE "M1"; -LOCATE COMP "TEST[13]" SITE "P4"; -LOCATE COMP "TEST[14]" SITE "N1"; +LOCATE COMP "TEST_LINE[1]" SITE "N3"; +LOCATE COMP "TEST_LINE[2]" SITE "M3"; +LOCATE COMP "TEST_LINE[3]" SITE "L3"; +LOCATE COMP "TEST_LINE[4]" SITE "K3"; +LOCATE COMP "TEST_LINE[5]" SITE "N2"; +LOCATE COMP "TEST_LINE[6]" SITE "J3"; +LOCATE COMP "TEST_LINE[7]" SITE "P1"; +LOCATE COMP "TEST_LINE[8]" SITE "L2"; +LOCATE COMP "TEST_LINE[9]" SITE "P2"; +LOCATE COMP "TEST_LINE[10]" SITE "L1"; +LOCATE COMP "TEST_LINE[11]" SITE "P3"; +LOCATE COMP "TEST_LINE[12]" SITE "M1"; +LOCATE COMP "TEST_LINE[13]" SITE "P4"; +LOCATE COMP "TEST_LINE[14]" SITE "N1"; DEFINE PORT GROUP "TEST_group" "TEST*" ; IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8 BANK_VCCIO=2.5; \ No newline at end of file -- 2.43.0