From 595f7351ee8d42ccb5bf1c36524de26ba0e3c808 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 18 Aug 2016 12:59:35 +0200 Subject: [PATCH] Adding necessary changes to allow reading of ADC on Power board --- combiner/combiner.vhd | 18 +++++-- pinout/power.lpf | 45 ++++++++++++++++ power/compile.pl | 1 + power/config_compile_frankfurt.pl | 26 ++++++++++ power/par.p2t | 21 ++++++++ power/power.prj | 86 +++++++++++++++++++++++++++++++ power/power.vhd | 86 +++++++++++++++++++++++++++++++ 7 files changed, 278 insertions(+), 5 deletions(-) create mode 100644 pinout/power.lpf create mode 120000 power/compile.pl create mode 100644 power/config_compile_frankfurt.pl create mode 100644 power/par.p2t create mode 100644 power/power.prj create mode 100644 power/power.vhd diff --git a/combiner/combiner.vhd b/combiner/combiner.vhd index 6493c44..f5e7773 100644 --- a/combiner/combiner.vhd +++ b/combiner/combiner.vhd @@ -25,7 +25,7 @@ entity combiner is --Additional IO RJ_CLOCK : inout std_logic_vector( 3 downto 0); --1 not available here RJ_TRIG : inout std_logic_vector( 2 downto 1); --0,3 not available here - POWER_BOARD_IO : inout std_logic_vector( 3 downto 0); + POWER_BOARD_IO : inout std_logic_vector( 4 downto 1); RJ45_SIG : in std_logic_vector( 5 downto 1); --Lines to slaves @@ -102,6 +102,7 @@ architecture arch of combiner is signal led_off_i : std_logic; signal enable_ldo_i : std_logic_vector(11 downto 0); + signal spi_cs, spi_miso, spi_mosi, spi_clk : std_logic_vector(15 downto 0); --Media Interface signal med2int : med2int_array_t(0 to INTERFACE_NUM-1); signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); @@ -497,10 +498,10 @@ end generate; PROGRAMN => PROGRAMN, REBOOT_IN => common_ctrl_reg(15), --SPI - SPI_CS_OUT => open, - SPI_MOSI_OUT=> open, - SPI_MISO_IN => open, - SPI_CLK_OUT => open, + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, --Header HEADER_IO => header_io, ADDITIONAL_REG(0) => led_off_i, @@ -590,6 +591,13 @@ end generate; TEST_JTAG(20 downto 7) <= (others => '0'); + POWER_BOARD_IO(1) <= spi_clk(6); + POWER_BOARD_IO(2) <= spi_mosi(6); + POWER_BOARD_IO(3) <= spi_cs(6); + spi_miso(5) <= POWER_BOARD_IO(4); + spi_miso(6) <= POWER_BOARD_IO(4); + + end architecture; diff --git a/pinout/power.lpf b/pinout/power.lpf new file mode 100644 index 0000000..f73d53f --- /dev/null +++ b/pinout/power.lpf @@ -0,0 +1,45 @@ +SYSCONFIG MCCLK_FREQ=133; +BANK 0 VCCIO 3.3 V; +BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 4 VCCIO 2.5 V; +BANK 5 VCCIO 2.5 V; + + +LOCATE COMP "COM_1" SITE "G1"; +LOCATE COMP "COM_2" SITE "J1"; +LOCATE COMP "COM_3" SITE "H1"; +LOCATE COMP "COM_4" SITE "K1"; +DEFINE PORT GROUP "COM_group" "COM*" ; +IOBUF GROUP "COM_group" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "ADC_CLK" SITE "L8"; +LOCATE COMP "ADC_CS_1" SITE "L10"; +LOCATE COMP "ADC_CS_2" SITE "L9"; +LOCATE COMP "ADC_MOSI" SITE "D10"; +LOCATE COMP "ADC_MISO" SITE "D11"; +DEFINE PORT GROUP "ADC_group" "ADC*" ; +IOBUF GROUP "ADC_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_GREEN" SITE "B10"; +LOCATE COMP "LED_ORANGE" SITE "B11"; +LOCATE COMP "LED_RED" SITE "C10"; +LOCATE COMP "LED_YELLOW" SITE "C11"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25; + +LOCATE COMP "TEST_1" SITE "K11"; +LOCATE COMP "TEST_2" SITE "J11"; +LOCATE COMP "TEST_3" SITE "J10"; +LOCATE COMP "TEST_4" SITE "G11"; +LOCATE COMP "TEST_5" SITE "G10"; +LOCATE COMP "TEST_6" SITE "F9"; +LOCATE COMP "TEST_7" SITE "E11"; +LOCATE COMP "TEST_8" SITE "E10"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "ONEWIRE" SITE "B9"; +IOBUF PORT "ONEWIRE" IO_TYPE=LVTTL33 DRIVE=8 PULLMODE=UP; \ No newline at end of file diff --git a/power/compile.pl b/power/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/power/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/power/config_compile_frankfurt.pl b/power/config_compile_frankfurt.pl new file mode 100644 index 0000000..854d219 --- /dev/null +++ b/power/config_compile_frankfurt.pl @@ -0,0 +1,26 @@ +Familyname => 'MachXO3LF', +Devicename => 'LCMXO3LF-4300E', +Package => 'CSFBGA121', +Speedgrade => '5', + +TOPNAME => "power", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.7_x64', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +# synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +make_jed => 1, diff --git a/power/par.p2t b/power/par.p2t new file mode 100644 index 0000000..39a0684 --- /dev/null +++ b/power/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 1 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/power/power.prj b/power/power.prj new file mode 100644 index 0000000..8864a11 --- /dev/null +++ b/power/power.prj @@ -0,0 +1,86 @@ +#-- Synopsys, Inc. +#-- Version J-2015.03L-SP1 +#-- Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt + +#project files + +add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" + +#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +#add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd" +#add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" +#add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd" +#add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +#add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" + +#add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" +#add_file -vhdl -lib work "../../logicbox/cores/efb.vhd" +#add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v" +#add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" + +add_file -vhdl -lib work "power.vhd" + + + +#implementation: "Thresholds" +impl -add workdir -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par + +#device options +set_option -technology MACHXO3LF +set_option -part LCMXO3LF_4300E +set_option -package UWG81CTR +set_option -speed_grade -5 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "power" + +# mapper_options +set_option -frequency 1 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# Lattice XP +set_option -maxfan 1000 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 1 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 +set_option -multi_file_compilation_unit 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/power.edf" + +#set log file +set_option log_file "workdir/power.srf" +impl -active "workdir" diff --git a/power/power.vhd b/power/power.vhd new file mode 100644 index 0000000..999c478 --- /dev/null +++ b/power/power.vhd @@ -0,0 +1,86 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library machxo3lf; +use machxo3lf.all; + +library work; +use work.trb_net_std.all; + +entity power is + port( + + COM : inout std_logic_vector(4 downto 1); + ADC_CLK : out std_logic; + ADC_CS : out std_logic_vector(2 downto 0); + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + + LED_GREEN : out std_logic; + LED_RED : out std_logic; + LED_ORANGE : out std_logic; + LED_YELLOW : out std_logic; + + TEST : out std_logic_vector(8 downto 1); + ONEWIRE : inout std_logic + + ); +end entity; + + +architecture arch of power is + signal clk_osc, clk_i : std_logic; + + + signal sed_error : std_logic; + signal sed_debug : std_logic_vector(31 downto 0); + signal controlsed_i : std_logic_vector(3 downto 0); + + + + component OSCH + generic (NOM_FREQ: string := "33.25"); + port ( + STDBY :IN std_logic; + OSC :OUT std_logic; + SEDSTDBY :OUT std_logic + ); + end component; + + + +begin + + + +--------------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------------- +clk_source: OSCH + generic map ( NOM_FREQ => "33.25" ) + port map ( + STDBY => '0', + OSC => clk_osc, + SEDSTDBY => open + ); + +clk_i <= clk_osc; + + +ADC_CLK <= not COM(1); +ADC_MOSI <= COM(2); +ADC_CS(1) <= COM(3); +ADC_CS(2) <= not COM(3); +COM(4) <= ADC_MISO; + + +LED_GREEN <= COM(3); +LED_YELLOW <= not COM(1); +LED_RED <= COM(2); +LED_ORANGE <= ADC_MISO; + +end architecture; + + + \ No newline at end of file -- 2.43.0