From 5a84ea5af3921a3d9e3cd15b340bf91d190b6ce3 Mon Sep 17 00:00:00 2001 From: local account Date: Thu, 22 Jun 2017 10:30:12 +0200 Subject: [PATCH] latest Version of threshold FPGA - FLASH included --- code/spi_slave.vhd | 4 +- pinout/thresholds.lpf | 2 +- thresholds/compile.pl | 2 +- thresholds/config_compile_gsi.pl | 11 +- thresholds/cores/efb.ipx | 8 + thresholds/cores/efb.lpc | 90 +++++ thresholds/cores/efb.vhd | 202 ++++++++++ thresholds/cores/flash.ipx | 8 + thresholds/cores/flash.lpc | 90 +++++ thresholds/cores/flash.vhd | 202 ++++++++++ thresholds/sim/thresh_tb.vhd | 75 ++++ thresholds/thresholds.prj | 9 +- thresholds/thresholds.vhd | 656 ++++++++++++++++++++----------- 13 files changed, 1115 insertions(+), 244 deletions(-) create mode 100644 thresholds/cores/efb.ipx create mode 100644 thresholds/cores/efb.lpc create mode 100644 thresholds/cores/efb.vhd create mode 100644 thresholds/cores/flash.ipx create mode 100644 thresholds/cores/flash.lpc create mode 100644 thresholds/cores/flash.vhd create mode 100644 thresholds/sim/thresh_tb.vhd diff --git a/code/spi_slave.vhd b/code/spi_slave.vhd index f234756..1223524 100644 --- a/code/spi_slave.vhd +++ b/code/spi_slave.vhd @@ -103,8 +103,8 @@ PROC_GEN_SIGNALS : process begin operation_i <= input(23); if (input(23) = '0') then READ_OUT <= '1'; - else - WRITE_OUT <= '1'; + --else + -- WRITE_OUT <= '1'; end if; ADDR_OUT <= input(31 downto 24); state <= GET_DATA; diff --git a/pinout/thresholds.lpf b/pinout/thresholds.lpf index f6f3b6c..4e91ce1 100644 --- a/pinout/thresholds.lpf +++ b/pinout/thresholds.lpf @@ -1,7 +1,7 @@ COMMERCIAL ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; -SYSCONFIG MCCLK_FREQ=33 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE MUX_CONFIGURATION_PORTS=ENABLE ; +SYSCONFIG MCCLK_FREQ=33.25 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE MUX_CONFIGURATION_PORTS=ENABLE ; LOCATE COMP "MISO_OUT" SITE "E1"; #DAC1_CTRL0 diff --git a/thresholds/compile.pl b/thresholds/compile.pl index 8a19aa6..3dfb1e0 120000 --- a/thresholds/compile.pl +++ b/thresholds/compile.pl @@ -1 +1 @@ -../../trb3sc/scripts/compile.pl \ No newline at end of file +/home/adrian/git/trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/thresholds/config_compile_gsi.pl b/thresholds/config_compile_gsi.pl index a356297..7a3b0a7 100644 --- a/thresholds/config_compile_gsi.pl +++ b/thresholds/config_compile_gsi.pl @@ -1,6 +1,11 @@ + #Familyname => 'MachXO3LF', + #Devicename => 'LCMXO3LF-6900C', + #Package => 'CABGA256', + #Speedgrade => '5', + Familyname => 'MachXO3LF', -Devicename => 'LCMXO3LF-6900C', -Package => 'CABGA256', +Devicename => 'LCMXO3LF-4300E', +Package => 'WLCSP81', Speedgrade => '5', TOPNAME => "thresholds", @@ -15,7 +20,7 @@ nodelist_file => 'nodelist_frankfurt.txt', #Include only necessary lpf files -#pinout_file => '', #name of pin-out file, if not equal TOPNAME +pinout_file => 'thresholds', #name of pin-out file, if not equal TOPNAME include_TDC => 0, include_GBE => 0, diff --git a/thresholds/cores/efb.ipx b/thresholds/cores/efb.ipx new file mode 100644 index 0000000..3d1df68 --- /dev/null +++ b/thresholds/cores/efb.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/thresholds/cores/efb.lpc b/thresholds/cores/efb.lpc new file mode 100644 index 0000000..a395056 --- /dev/null +++ b/thresholds/cores/efb.lpc @@ -0,0 +1,90 @@ +[Device] +Family=machxo3lf +PartType=LCMXO3LF-6900C +PartName=LCMXO3LF-6900C-6BG256C +SpeedGrade=6 +Package=CABGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.2 +ModuleName=efb +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/07/2017 +Time=13:37:08 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1config=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=Positive +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +wb_clk_freq=33.25 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=2014 +ufm_remain= +mem_size=32 +ufm_start= +ufm_init=0 +memfile= +ufm_dt=hex +wb=1 + +[Command] +cmd_line= -w -n efb -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 2014 -mem_size 32 -ufm_0 -wb -dev 6900 diff --git a/thresholds/cores/efb.vhd b/thresholds/cores/efb.vhd new file mode 100644 index 0000000..d3a9a33 --- /dev/null +++ b/thresholds/cores/efb.vhd @@ -0,0 +1,202 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2 +-- Module Version: 1.2 +--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n efb -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 2014 -mem_size 32 -ufm_0 -wb -dev 6900 + +-- Fri Apr 7 13:37:08 2017 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO3L; +use MACHXO3L.components.all; +-- synopsys translate_on + +entity efb is + port ( + wb_clk_i: in std_logic; + wb_rst_i: in std_logic; + wb_cyc_i: in std_logic; + wb_stb_i: in std_logic; + wb_we_i: in std_logic; + wb_adr_i: in std_logic_vector(7 downto 0); + wb_dat_i: in std_logic_vector(7 downto 0); + wb_dat_o: out std_logic_vector(7 downto 0); + wb_ack_o: out std_logic; + wbc_ufm_irq: out std_logic); +end efb; + +architecture Structure of efb is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EFB + generic (EFB_I2C1 : in String; EFB_I2C2 : in String; + EFB_SPI : in String; EFB_TC : in String; + EFB_TC_PORTMODE : in String; EFB_UFM : in String; + EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String; + UFM_INIT_PAGES : in Integer; + UFM_INIT_START_PAGE : in Integer; + UFM_INIT_ALL_ZEROS : in String; + UFM_INIT_FILE_NAME : in String; + UFM_INIT_FILE_FORMAT : in String; + I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String; + I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String; + I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String; + I2C1_CLK_DIVIDER : in Integer; + I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String; + I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String; + I2C2_WAKEUP : in String; SPI_MODE : in String; + SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String; + SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String; + SPI_SLAVE_HANDSHAKE : in String; + SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String; + SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String; + SPI_WAKEUP : in String; TC_MODE : in String; + TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer; + GSR : in String; TC_TOP_SET : in Integer; + TC_OCR_SET : in Integer; TC_OC_MODE : in String; + TC_RESETN : in String; TC_TOP_SEL : in String; + TC_OV_INT : in String; TC_OCR_INT : in String; + TC_ICR_INT : in String; TC_OVERFLOW : in String; + TC_ICAPTURE : in String); + port (WBCLKI: in std_logic; WBRSTI: in std_logic; + WBCYCI: in std_logic; WBSTBI: in std_logic; + WBWEI: in std_logic; WBADRI7: in std_logic; + WBADRI6: in std_logic; WBADRI5: in std_logic; + WBADRI4: in std_logic; WBADRI3: in std_logic; + WBADRI2: in std_logic; WBADRI1: in std_logic; + WBADRI0: in std_logic; WBDATI7: in std_logic; + WBDATI6: in std_logic; WBDATI5: in std_logic; + WBDATI4: in std_logic; WBDATI3: in std_logic; + WBDATI2: in std_logic; WBDATI1: in std_logic; + WBDATI0: in std_logic; PLL0DATI7: in std_logic; + PLL0DATI6: in std_logic; PLL0DATI5: in std_logic; + PLL0DATI4: in std_logic; PLL0DATI3: in std_logic; + PLL0DATI2: in std_logic; PLL0DATI1: in std_logic; + PLL0DATI0: in std_logic; PLL0ACKI: in std_logic; + PLL1DATI7: in std_logic; PLL1DATI6: in std_logic; + PLL1DATI5: in std_logic; PLL1DATI4: in std_logic; + PLL1DATI3: in std_logic; PLL1DATI2: in std_logic; + PLL1DATI1: in std_logic; PLL1DATI0: in std_logic; + PLL1ACKI: in std_logic; I2C1SCLI: in std_logic; + I2C1SDAI: in std_logic; I2C2SCLI: in std_logic; + I2C2SDAI: in std_logic; SPISCKI: in std_logic; + SPIMISOI: in std_logic; SPIMOSII: in std_logic; + SPISCSN: in std_logic; TCCLKI: in std_logic; + TCRSTN: in std_logic; TCIC: in std_logic; + UFMSN: in std_logic; WBDATO7: out std_logic; + WBDATO6: out std_logic; WBDATO5: out std_logic; + WBDATO4: out std_logic; WBDATO3: out std_logic; + WBDATO2: out std_logic; WBDATO1: out std_logic; + WBDATO0: out std_logic; WBACKO: out std_logic; + PLLCLKO: out std_logic; PLLRSTO: out std_logic; + PLL0STBO: out std_logic; PLL1STBO: out std_logic; + PLLWEO: out std_logic; PLLADRO4: out std_logic; + PLLADRO3: out std_logic; PLLADRO2: out std_logic; + PLLADRO1: out std_logic; PLLADRO0: out std_logic; + PLLDATO7: out std_logic; PLLDATO6: out std_logic; + PLLDATO5: out std_logic; PLLDATO4: out std_logic; + PLLDATO3: out std_logic; PLLDATO2: out std_logic; + PLLDATO1: out std_logic; PLLDATO0: out std_logic; + I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic; + I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic; + I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic; + I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic; + I2C1IRQO: out std_logic; I2C2IRQO: out std_logic; + SPISCKO: out std_logic; SPISCKEN: out std_logic; + SPIMISOO: out std_logic; SPIMISOEN: out std_logic; + SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic; + SPIMCSN7: out std_logic; SPIMCSN6: out std_logic; + SPIMCSN5: out std_logic; SPIMCSN4: out std_logic; + SPIMCSN3: out std_logic; SPIMCSN2: out std_logic; + SPIMCSN1: out std_logic; SPIMCSN0: out std_logic; + SPICSNEN: out std_logic; SPIIRQO: out std_logic; + TCINT: out std_logic; TCOC: out std_logic; + WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic; + CFGSTDBY: out std_logic); + end component; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + EFBInst_0: EFB + generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE", + UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 2014, + UFM_INIT_PAGES=> 32, DEV_DENSITY=> "6900L", EFB_UFM=> "ENABLED", + TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF", + TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF", + TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767, + TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM", + TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED", + SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED", + SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED", + SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED", + SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED", + SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER", + EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED", + I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010", + I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED", + I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz", + I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT", + EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.2") + port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i, + WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7), + WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5), + WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3), + WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1), + WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7), + WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5), + WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3), + WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1), + WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo, + PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo, + PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo, + PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo, + PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo, + PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo, + PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo, + PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo, + PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo, + PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo, + I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo, + I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo, + SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo, + TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi, + WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6), + WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4), + WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2), + WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o, + PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open, + PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open, + PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open, + PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open, + PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open, + PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open, + I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open, + I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open, + I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open, + SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open, + SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open, + SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open, + SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open, + SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open, + TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open, + CFGSTDBY=>open); + +end Structure; diff --git a/thresholds/cores/flash.ipx b/thresholds/cores/flash.ipx new file mode 100644 index 0000000..5f07965 --- /dev/null +++ b/thresholds/cores/flash.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/thresholds/cores/flash.lpc b/thresholds/cores/flash.lpc new file mode 100644 index 0000000..f676711 --- /dev/null +++ b/thresholds/cores/flash.lpc @@ -0,0 +1,90 @@ +[Device] +Family=machxo3lf +PartType=LCMXO3LF-4300E +PartName=LCMXO3LF-4300E-5MG256C +SpeedGrade=5 +Package=CSFBGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.2 +ModuleName=flash +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/22/2017 +Time=14:32:07 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1config=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=Positive +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +wb_clk_freq=33.25 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=765 +ufm_remain= +mem_size=2 +ufm_start= +ufm_init=0 +memfile= +ufm_dt=hex +wb=1 + +[Command] +cmd_line= -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 765 -mem_size 2 -ufm_0 -wb -dev 4300 diff --git a/thresholds/cores/flash.vhd b/thresholds/cores/flash.vhd new file mode 100644 index 0000000..2031160 --- /dev/null +++ b/thresholds/cores/flash.vhd @@ -0,0 +1,202 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2 +-- Module Version: 1.2 +--/home/soft/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 765 -mem_size 2 -ufm_0 -wb -dev 4300 + +-- Mon May 22 14:32:07 2017 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO3L; +use MACHXO3L.components.all; +-- synopsys translate_on + +entity flash is + port ( + wb_clk_i: in std_logic; + wb_rst_i: in std_logic; + wb_cyc_i: in std_logic; + wb_stb_i: in std_logic; + wb_we_i: in std_logic; + wb_adr_i: in std_logic_vector(7 downto 0); + wb_dat_i: in std_logic_vector(7 downto 0); + wb_dat_o: out std_logic_vector(7 downto 0); + wb_ack_o: out std_logic; + wbc_ufm_irq: out std_logic); +end flash; + +architecture Structure of flash is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component EFB + generic (EFB_I2C1 : in String; EFB_I2C2 : in String; + EFB_SPI : in String; EFB_TC : in String; + EFB_TC_PORTMODE : in String; EFB_UFM : in String; + EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String; + UFM_INIT_PAGES : in Integer; + UFM_INIT_START_PAGE : in Integer; + UFM_INIT_ALL_ZEROS : in String; + UFM_INIT_FILE_NAME : in String; + UFM_INIT_FILE_FORMAT : in String; + I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String; + I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String; + I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String; + I2C1_CLK_DIVIDER : in Integer; + I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String; + I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String; + I2C2_WAKEUP : in String; SPI_MODE : in String; + SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String; + SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String; + SPI_SLAVE_HANDSHAKE : in String; + SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String; + SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String; + SPI_WAKEUP : in String; TC_MODE : in String; + TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer; + GSR : in String; TC_TOP_SET : in Integer; + TC_OCR_SET : in Integer; TC_OC_MODE : in String; + TC_RESETN : in String; TC_TOP_SEL : in String; + TC_OV_INT : in String; TC_OCR_INT : in String; + TC_ICR_INT : in String; TC_OVERFLOW : in String; + TC_ICAPTURE : in String); + port (WBCLKI: in std_logic; WBRSTI: in std_logic; + WBCYCI: in std_logic; WBSTBI: in std_logic; + WBWEI: in std_logic; WBADRI7: in std_logic; + WBADRI6: in std_logic; WBADRI5: in std_logic; + WBADRI4: in std_logic; WBADRI3: in std_logic; + WBADRI2: in std_logic; WBADRI1: in std_logic; + WBADRI0: in std_logic; WBDATI7: in std_logic; + WBDATI6: in std_logic; WBDATI5: in std_logic; + WBDATI4: in std_logic; WBDATI3: in std_logic; + WBDATI2: in std_logic; WBDATI1: in std_logic; + WBDATI0: in std_logic; PLL0DATI7: in std_logic; + PLL0DATI6: in std_logic; PLL0DATI5: in std_logic; + PLL0DATI4: in std_logic; PLL0DATI3: in std_logic; + PLL0DATI2: in std_logic; PLL0DATI1: in std_logic; + PLL0DATI0: in std_logic; PLL0ACKI: in std_logic; + PLL1DATI7: in std_logic; PLL1DATI6: in std_logic; + PLL1DATI5: in std_logic; PLL1DATI4: in std_logic; + PLL1DATI3: in std_logic; PLL1DATI2: in std_logic; + PLL1DATI1: in std_logic; PLL1DATI0: in std_logic; + PLL1ACKI: in std_logic; I2C1SCLI: in std_logic; + I2C1SDAI: in std_logic; I2C2SCLI: in std_logic; + I2C2SDAI: in std_logic; SPISCKI: in std_logic; + SPIMISOI: in std_logic; SPIMOSII: in std_logic; + SPISCSN: in std_logic; TCCLKI: in std_logic; + TCRSTN: in std_logic; TCIC: in std_logic; + UFMSN: in std_logic; WBDATO7: out std_logic; + WBDATO6: out std_logic; WBDATO5: out std_logic; + WBDATO4: out std_logic; WBDATO3: out std_logic; + WBDATO2: out std_logic; WBDATO1: out std_logic; + WBDATO0: out std_logic; WBACKO: out std_logic; + PLLCLKO: out std_logic; PLLRSTO: out std_logic; + PLL0STBO: out std_logic; PLL1STBO: out std_logic; + PLLWEO: out std_logic; PLLADRO4: out std_logic; + PLLADRO3: out std_logic; PLLADRO2: out std_logic; + PLLADRO1: out std_logic; PLLADRO0: out std_logic; + PLLDATO7: out std_logic; PLLDATO6: out std_logic; + PLLDATO5: out std_logic; PLLDATO4: out std_logic; + PLLDATO3: out std_logic; PLLDATO2: out std_logic; + PLLDATO1: out std_logic; PLLDATO0: out std_logic; + I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic; + I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic; + I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic; + I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic; + I2C1IRQO: out std_logic; I2C2IRQO: out std_logic; + SPISCKO: out std_logic; SPISCKEN: out std_logic; + SPIMISOO: out std_logic; SPIMISOEN: out std_logic; + SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic; + SPIMCSN7: out std_logic; SPIMCSN6: out std_logic; + SPIMCSN5: out std_logic; SPIMCSN4: out std_logic; + SPIMCSN3: out std_logic; SPIMCSN2: out std_logic; + SPIMCSN1: out std_logic; SPIMCSN0: out std_logic; + SPICSNEN: out std_logic; SPIIRQO: out std_logic; + TCINT: out std_logic; TCOC: out std_logic; + WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic; + CFGSTDBY: out std_logic); + end component; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + EFBInst_0: EFB + generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE", + UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 765, + UFM_INIT_PAGES=> 2, DEV_DENSITY=> "4300L", EFB_UFM=> "ENABLED", + TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF", + TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF", + TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767, + TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM", + TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED", + SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED", + SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED", + SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED", + SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED", + SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER", + EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED", + I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010", + I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED", + I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz", + I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT", + EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.2") + port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i, + WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7), + WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5), + WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3), + WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1), + WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7), + WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5), + WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3), + WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1), + WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo, + PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo, + PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo, + PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo, + PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo, + PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo, + PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo, + PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo, + PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo, + PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo, + I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo, + I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo, + SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo, + TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi, + WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6), + WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4), + WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2), + WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o, + PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open, + PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open, + PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open, + PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open, + PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open, + PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open, + I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open, + I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open, + I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open, + SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open, + SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open, + SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open, + SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open, + SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open, + TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open, + CFGSTDBY=>open); + +end Structure; diff --git a/thresholds/sim/thresh_tb.vhd b/thresholds/sim/thresh_tb.vhd new file mode 100644 index 0000000..74d09e8 --- /dev/null +++ b/thresholds/sim/thresh_tb.vhd @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 05.01.2017 14:31:03 +-- Design Name: +-- Module Name: sim_tb - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library work; +use work.trb_net_std.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity sim_tb is +end sim_tb; + +architecture Behavioral of sim_tb is +signal CLK ,Flag_Lim, Flag_LUT: std_logic := '0'; +signal DOUT : std_logic_vector(15 downto 0); +constant CLK_PERIOD : time := 20 ns; + +begin +--Input : entity work.input_env +-- port map( +-- CLK => CLK, +-- DOUT => DIN_i +-- ); + + thresholds : entity work.thresholds + port map( + -- CLK => CLK, + DAC_FLAG => '0', + OUTPUT => DOUT, + MISO_OUT =>open, + MOSI_IN =>'1',--: in std_logic; + SCLK_IN =>'1',--: in std_logic; + CS_IN =>'0'--: in std_logic--; + ); + + + + CLK_PROC : process is + begin + CLK <= '1'; + wait for CLK_PERIOD / 2; + CLK <= '0'; + wait for CLK_PERIOD / 2; + end process; + + + + + +end Behavioral; \ No newline at end of file diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj index b2787ad..7013526 100644 --- a/thresholds/thresholds.prj +++ b/thresholds/thresholds.prj @@ -7,6 +7,7 @@ #add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" +#add file -vhdl -lib work "./test/machxo3lf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd" add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" @@ -18,7 +19,7 @@ add_file -vhdl -lib work "cores/flash.vhd" #add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" #add_file -vhdl -lib work "cores/efb.vhd" -#add_file -verilog -lib work "cores/efb_define_def.v" +add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v" add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" add_file -vhdl -lib work "thresholds.vhd" @@ -39,8 +40,10 @@ set_option -job par_1 -add par #device options set_option -technology MACHXO3LF -set_option -part LCMXO3LF_6900C -set_option -package BG256C +#set_option -part LCMXO3LF_6900C +#set_option -package BG256C +set_option -part LCMXO3LF_4300E +set_option -package UWG81 set_option -speed_grade -5 set_option -part_companion "" diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 2a00fa1..3c4d374 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -10,12 +10,14 @@ use work.trb_net_std.all; entity thresholds is port( - ID : in std_logic; - OUTPUT : out std_logic_vector(15 downto 0); + DAC_FLAG : in std_logic; --ID + OUTPUT : out std_logic_vector(16 downto 1); MISO_OUT : out std_logic; MOSI_IN : in std_logic; SCLK_IN : in std_logic; - CS_IN : in std_logic + CS_IN : in std_logic--; + --LED : out std_logic_vector(7 downto 0); + --DIPSW : in std_logic_vector(3 downto 0) ); end entity; @@ -36,36 +38,48 @@ architecture arch of thresholds is signal sed_debug : std_logic_vector(31 downto 0); signal controlsed_i : std_logic_vector(3 downto 0); - signal pwm_data_i : std_logic_vector(15 downto 0); - signal pwm_write_i : std_logic; - signal pwm_addr_i : std_logic_vector(4 downto 0); - signal pwm_data_ii : std_logic_vector(15 downto 0); - signal pwm_write_ii : std_logic; - signal pwm_addr_ii : std_logic_vector(4 downto 0); + signal pwm_data_i : std_logic_vector(15 downto 0):= x"6000"; + signal pwm_write_i : std_logic; + signal pwm_addr_i : std_logic_vector(4 downto 0); + signal pwm_data_ii : std_logic_vector(15 downto 0); + signal pwm_write_ii : std_logic; + signal pwm_addr_ii : std_logic_vector(4 downto 0); + signal pwm_data_iii : std_logic_vector(15 downto 0); + signal pwm_write_iii : std_logic; + signal pwm_addr_iii : std_logic_vector(4 downto 0); -- signal flashram_reset : std_logic; --signal flashram_write_i: std_logic; signal flashram_data_i : std_logic_vector(7 downto 0); - signal flashram_data_o : std_logic_vector(7 downto 0); - signal ram_data : ram_t := (others =>("0000000000000000"));--: std_logic_vector(15 downto 0); + signal flashram_data_o : std_logic_vector(7 downto 0) := "00000010"; + signal ram_data : ram_t := (others =>("0000000000100001"));--: std_logic_vector(15 downto 0); --signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0); - signal flash_command : std_logic; + signal flash_command : std_logic := '0'; --signal flash_page : std_logic_vector(12 downto 0); - signal flash_go : std_logic; + signal flash_go : std_logic := '1'; signal flash_busy : std_logic; signal flash_err : std_logic; - signal compensate_i : signed(15 downto 0); - signal pwm_i : std_logic_vector(15 downto 0); + signal compensate_i : signed(15 downto 0) := (others =>'0'); + signal pwm_i : std_logic_vector(16 downto 1); signal ufm_bus_ready_in : std_logic; signal ufm_bus_ready_out : std_logic; signal ufm_databyte_counter : unsigned(14 downto 0); - signal ram_data_f_spi_addr : std_logic_vector( 7 downto 0); - signal ram_data_f_spi_data : std_logic_vector(15 downto 0); - signal ram_data_f_spi_write : std_logic; + signal ram_spi_addr : std_logic_vector( 7 downto 0); + signal ram_spi_data : std_logic_vector(15 downto 0):= "0000111100001111"; + signal ram_spi_write : std_logic; + signal show_flash_err : std_logic := '0'; + signal ram_spi_read :std_logic := '0'; + signal flash_temp : std_logic_vector(7 downto 0); + + --type state_type is (Start,IDLE,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15); --type of state machine. + --signal state: state_type := Start; + --signal init : std_logic:='1'; + +-- signal temp : std_logic_vector(3 downto 0):= "0000"; component OSCH generic (NOM_FREQ: string := "33.25"); @@ -112,56 +126,205 @@ THE_SPI : entity work.spi_slave DEBUG => open ); - - -PROC_REGS : process begin - wait until rising_edge(clk_i); - bus_ready <= '0'; - pwm_write_i <= '0'; - flash_go <= '0'; - ram_data_f_spi_write <= '0'; + - if pwm_write_ii = '1' then - pwm_data_i <= pwm_data_ii; - pwm_addr_i <= pwm_addr_ii; - pwm_write_i <= pwm_write_ii; - - elsif bus_read = '1' then - bus_ready <= '1'; - if spi_addr >= x"10" and spi_addr < x"20" then - spi_tx_data <= ram_data(to_integer(unsigned(spi_addr))); +-- count : process (clk_i) +-- begin +-- if rising_edge(clk_i) then +-- if temp="1001" then +-- temp<="0000"; +-- else +-- temp <= std_logic_vector(unsigned(temp) + 1); +-- end if; +-- end if; +-- +-- end process; + +-- state_machine : process (clk_i) +-- begin +-- if rising_edge(clk_i) then +-- pwm_write_i <= '0'; +-- --pwm_data_i <= x"6000"; +-- case state is +-- when Start => --when current state is "s0" +-- if init = '1' then +-- pwm_write_i <= '0'; +-- state <= c0; +-- end if; +-- +-- when c0 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00000"; +-- state <= c1; +-- +-- when c1 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00001"; +-- state <= c2; +-- +-- when c2 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00010"; +-- state <= c3; +-- +-- when c3 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00011"; +-- state <= c4; +-- +-- when c4 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00100"; +-- state <= c5; +-- +-- when c5 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00101"; +-- state <= c6; +-- +-- when c6 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00110"; +-- state <= c7; +-- +-- when c7 => pwm_write_i <= '1'; +-- pwm_addr_i <= "00111"; +-- state <= c8; +-- +-- when c8 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01000"; +-- state <= c9; +-- +-- when c9 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01001"; +-- state <= c10; +-- +-- when c10 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01010"; +-- state <= c11; +-- +-- when c11 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01011"; +-- state <= c12; +-- +-- when c12 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01100"; +-- state <= c13; +-- +-- when c13 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01101"; +-- state <= c14; +-- +-- when c14 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01110"; +-- state <= c15; +-- +-- when c15 => pwm_write_i <= '1'; +-- pwm_addr_i <= "01111"; +-- init <= '0'; +-- state <= IDLE; +-- init <= '0'; +-- +-- when IDLE => pwm_write_i <= pwm_write_ii; +-- pwm_addr_i <= pwm_addr_ii; +-- pwm_data_i <= pwm_data_ii; +-- +-- end case; +-- +-- end if; +-- end process; + + +PWM_select : process begin + wait until rising_edge(clk_i); + + pwm_write_i <= '0'; + if pwm_write_ii = '1' then + pwm_data_i <= pwm_data_ii; + pwm_addr_i <= pwm_addr_ii; + pwm_write_i <= pwm_write_ii; else - case spi_addr is - when x"30" => spi_tx_data <= std_logic_vector(compensate_i); - when x"ee" => spi_tx_data <= sed_debug(15 downto 0); - when x"ef" => spi_tx_data <= sed_debug(31 downto 16); - when others => null; - end case; + pwm_data_i <= pwm_data_iii; + pwm_addr_i <= pwm_addr_iii; + pwm_write_i <= pwm_write_iii; end if; + +end process; + - elsif bus_write = '1' then - if spi_addr < x"10" then -- 0 to 15 0x00 to 0x10 -- write directly to pwm - if flash_busy = '0' or flash_command = '0' then -- avoid conflict with writing from flash - pwm_data_i <= spi_rx_data(15 downto 0); - pwm_addr_i <= spi_addr(4 downto 0); - pwm_write_i <= '1'; - end if; - elsif spi_addr >= x"10" and spi_addr < x"20" then -- write to ram - --ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; - ram_data_f_spi_write <= '1'; - ram_data_f_spi_addr <= spi_addr; - ram_data_f_spi_data <= spi_rx_data; - else - case spi_addr is - -- when x"20" => flash_command <= spi_rx_data(0); --read/write to flash; - -- flash_go <= '1'; - when x"30" => compensate_i <= spi_rx_data(15 downto 0);--signed(uart_rx_data(15 downto 0); - when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); - end case; +PROC_REGS : process begin + wait until rising_edge(clk_i); + bus_ready <= '0'; + pwm_write_iii <= '0'; + flash_go <= '0'; + ram_spi_write <= '0'; + ram_spi_read <= '0'; + + if bus_read = '1' then + bus_ready <= '1'; + + if (spi_addr >= x"10") and (spi_addr < X"20") then + spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(4 downto 0)))); -- Read RAM + else + case spi_addr is + --when x"10" => spi_tx_data <= reg_spi_o(15 downto 0); + --when x"11" => spi_tx_data <= reg_spi_o(31 downto 16); + when x"ee" => spi_tx_data <= sed_debug(15 downto 0); + when x"ef" => spi_tx_data <= sed_debug(31 downto 16); + -- + when others => null; + end case; + end if; + elsif bus_write = '1' then + if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM + pwm_data_iii <= spi_rx_data; + pwm_addr_iii <= spi_addr(4 downto 0); + pwm_write_iii <= '1'; + elsif ( spi_addr >= x"10") and (spi_addr < x"20") then -- write to RAM + ram_spi_data(15 downto 0) <= spi_rx_data; + ram_spi_write <= '1'; + ram_spi_addr <= "0000" & spi_addr(3 downto 0); + pwm_data_iii <= spi_rx_data; + pwm_addr_iii <= spi_addr(4 downto 0); + pwm_write_iii <= '1'; + else + case spi_addr is + when x"20" => flash_command <= '1'; --write to flash; + flash_go <= '1'; + when x"21" => flash_command <= '0'; --read from flash; + flash_go <= '1'; + when x"22" => compensate_i <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0); + when x"ee" => controlsed_i <= spi_rx_data(3 downto 0); + when others => null; + end case; + end if; end if; - end if; end process; +-- ManSel : process begin +-- wait until rising_edge(clk_i); +-- flash_go <= '0'; +-- ram_spi_write <= '0'; +-- --ram_spi_read <= '0'; +-- if pwm_write_ii = '1' then +-- pwm_data_i <= pwm_data_ii; +-- pwm_addr_i <= pwm_addr_ii; +-- pwm_write_i <= pwm_write_ii; +-- elsif DIPSW(0) = '0' then +-- case DIPSW(3 downto 1) is +-- when "000" => ram_spi_data(15 downto 0) <= "1100011100111000"; +-- ram_spi_write <= '1'; +-- ram_spi_addr <= "00000" & DIPSW(3 downto 1); +-- --when "010" => ram_spi_read <= '1'; +-- when "011" => flash_command <= '0'; --read from flash; +-- flash_go <= '1'; +-- when "100" => flash_command <= '1'; --write to flash; +-- flash_go <= '1'; +-- when "101" => ram_spi_data(15 downto 0) <= "0000011000101010"; +-- ram_spi_write <= '1'; +-- ram_spi_addr <= "00000" & DIPSW(3 downto 1); +-- when others => null; +-- end case; +-- else +-- LED <= not ram_data(to_integer(unsigned(DIPSW(3 downto 1))))(7 downto 0); +-- end if; +-- +-- +-- end process; + THE_SED : entity work.sedcheck port map( @@ -190,154 +353,69 @@ THE_PWM_GEN : entity work.pwm_generator ); --TODO connect to output according to ID -OUTPUT <= pwm_i; - +process(pwm_i,DAC_FLAG) + begin + if DAC_FLAG = '1' then + OUTPUT <= pwm_i; + else + OUTPUT(1) <= pwm_i(15); + OUTPUT(2) <= pwm_i(13); + OUTPUT(3) <= pwm_i(8); + OUTPUT(4) <= pwm_i(5); + OUTPUT(5) <= pwm_i(16); + OUTPUT(6) <= pwm_i(4); + OUTPUT(7) <= pwm_i(3); + OUTPUT(8) <= pwm_i(6); + OUTPUT(9) <= pwm_i(2); + OUTPUT(10) <= pwm_i(1); + OUTPUT(11) <= pwm_i(7); + OUTPUT(12) <= pwm_i(9); + OUTPUT(13) <= pwm_i(14); + OUTPUT(14) <= pwm_i(12); + OUTPUT(15) <= pwm_i(10); + OUTPUT(16) <= pwm_i(11); + + end if; + end process; --------------------------------------------------------------------------- -- Flash Controller --------------------------------------------------------------------------- ---THE_UFM : entity work.UFM_control --- generic map( --- NO_DATAPAGES => 2, --- UFM_STARTPAGE => "00"&x"00" --- ) --- port map( --- CLK => clk_i, --- CMD => flash_command, --- GO => flash_go, --- BUSY => flash_busy, --- RESET => '0', --- DATA_IN => flashram_data_i, --- DATA_OUT => flashram_data_o, --- DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte --- BUS_READY_IN => ufm_bus_ready_in, --- BUS_READY_OUT => ufm_bus_ready_out, --- FLASH_ERROR => flash_err --- ); - +THE_UFM : entity work.UFM_control + generic map( + NO_DATAPAGES => 2, + UFM_STARTPAGE => "00"&x"00" + ) + port map( + CLK => clk_i, + CMD => flash_command, + GO => flash_go, + BUSY => flash_busy, + RESET => '0', + DATA_IN => flashram_data_i, + DATA_OUT => flashram_data_o, + DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte + BUS_READY_IN => ufm_bus_ready_in, + BUS_READY_OUT => ufm_bus_ready_out, + FLASH_ERROR => flash_err + ); ---PROC_REGS_FLASH: process begin ---wait until rising_edge( clk_i ); + +-- PROC_REGS_FLASH: process begin +-- wait until rising_edge( clk_i ); -- ufm_bus_ready_in <= '0'; -- pwm_write_ii <= '0'; --- if flash_command = '0' and ufm_bus_ready_out = '1' then --- -- copy data from UFM to registers --- ufm_bus_ready_in <= '1'; --- case to_integer ( ufm_databyte_counter ) is --- when 0 => ram_data( 0)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 1 => ram_data( 0)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00000"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 2 => ram_data( 1)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 3 => ram_data( 1)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00001"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 4 => ram_data( 2)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 5 => ram_data( 2)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00010"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 6 => ram_data( 3)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 7 => ram_data( 3)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00011"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 8 => ram_data( 4)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 9 => ram_data( 4)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00100"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 10 => ram_data( 5)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 11 => ram_data( 5)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00101"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 12 => ram_data( 6)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 13 => ram_data( 6)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00110"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 14 => ram_data( 7)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 15 => ram_data( 7)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "00111"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 16 => ram_data( 8)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 17 => ram_data( 8)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01000"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 18 => ram_data( 9)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 19 => ram_data( 9)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01001"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 20 => ram_data(10)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 21 => ram_data(10)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01010"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 22 => ram_data(11)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 23 => ram_data(11)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01011"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 24 => ram_data(12)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 25 => ram_data(12)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01100"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 26 => ram_data(13)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 27 => ram_data(13)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01101"; --- pwm_data_ii( 15 downto 8) <= flashram_data_o; --- when 28 => ram_data(14)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 29 => ram_data(14)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01110"; --- pwm_data_ii(15 downto 8) <= flashram_data_o; --- when 30 => ram_data(15)( 7 downto 0) <= flashram_data_o; --- pwm_write_ii <= '0'; --- pwm_data_ii( 7 downto 0) <= flashram_data_o; --- when 31 => ram_data(15)(15 downto 8) <= flashram_data_o; --- pwm_write_ii <= '1'; --- pwm_addr_ii <= "01111"; --- pwm_data_ii(15 downto 8) <= flashram_data_o; +-- +-- if flash_command = '0' and ufm_bus_ready_out = '1' then +-- -- copy data from UFM to registers +-- ufm_bus_ready_in <= '1'; +-- case to_integer ( ufm_databyte_counter ) is +-- when 0 => ram_temp <= flashram_data_o; +-- when 1 => ram_data(0)(15 downto 0) <= flashram_data_o & ram_temp; +-- when 2 => ram_temp <= flashram_data_o; +-- when 3 => ram_data(1)(15 downto 0) <= flashram_data_o & ram_temp; -- when others => null; -- end case ; -- @@ -345,45 +423,155 @@ OUTPUT <= pwm_i; -- -- save data from registers to UFM -- ufm_bus_ready_in <= '1'; -- case to_integer ( ufm_databyte_counter ) is --- when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0); --- when 1 => flashram_data_i <= ram_data( 0)(15 downto 8); --- when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0); --- when 3 => flashram_data_i <= ram_data( 1)(15 downto 8); --- when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0); --- when 5 => flashram_data_i <= ram_data( 2)(15 downto 8); --- when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0); --- when 7 => flashram_data_i <= ram_data( 3)(15 downto 8); --- when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0); --- when 9 => flashram_data_i <= ram_data( 4)(15 downto 8); --- when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0); --- when 11 => flashram_data_i <= ram_data( 5)(15 downto 8); --- when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0); --- when 13 => flashram_data_i <= ram_data( 6)(15 downto 8); --- when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0); --- when 15 => flashram_data_i <= ram_data( 7)(15 downto 8); --- when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0); --- when 17 => flashram_data_i <= ram_data( 8)(15 downto 8); --- when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0); --- when 19 => flashram_data_i <= ram_data( 9)(15 downto 8); --- when 20 => flashram_data_i <= ram_data(10)( 7 downto 0); --- when 21 => flashram_data_i <= ram_data(10)(15 downto 8); --- when 22 => flashram_data_i <= ram_data(11)( 7 downto 0); --- when 23 => flashram_data_i <= ram_data(11)(15 downto 8); --- when 24 => flashram_data_i <= ram_data(12)( 7 downto 0); --- when 25 => flashram_data_i <= ram_data(12)(15 downto 8); --- when 26 => flashram_data_i <= ram_data(13)( 7 downto 0); --- when 27 => flashram_data_i <= ram_data(13)(15 downto 8); --- when 28 => flashram_data_i <= ram_data(14)( 7 downto 0); --- when 29 => flashram_data_i <= ram_data(14)(15 downto 8); --- when 30 => flashram_data_i <= ram_data(15)( 7 downto 0); --- when 31 => flashram_data_i <= ram_data(15)(15 downto 8); +-- when 0 => flashram_data_i <= ram_data(1)( 7 downto 0); +-- when 1 => flashram_data_i <= ram_data(1)(15 downto 8); +-- --when 2 => flashram_data_i <= ram_data(1)( 7 downto 0); +-- --when 3 => flashram_data_i <= ram_data(1)(15 downto 8); -- when others => null ; -- end case ; -- -- elsif ram_data_f_spi_write = '1' then --- ram_data(to_integer(unsigned(ram_data_f_spi_addr))) <= ram_data_f_spi_data; +-- ram_data(1) <= reg_spi; +-- elsif ram_data_f_spi_read = '1' then +-- reg_spi_o <= ram_data(1); -- end if ; --- end process ; + + + +PROC_REGS_FLASH: process begin +wait until rising_edge( clk_i ); + ufm_bus_ready_in <= '0'; + pwm_write_ii <= '0'; + if flash_command = '0' and ufm_bus_ready_out = '1' then + -- copy data from UFM to registers + ufm_bus_ready_in <= '1'; + case to_integer ( ufm_databyte_counter ) is + when 0 => flash_temp <= flashram_data_o; + when 1 => ram_data( 0) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00000"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 2 => flash_temp <= flashram_data_o; + when 3 => ram_data( 1) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00001"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 4 => flash_temp <= flashram_data_o; + when 5 => ram_data( 2) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00010"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 6 => flash_temp <= flashram_data_o; + when 7 => ram_data( 3) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00011"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 8 => flash_temp <= flashram_data_o; + when 9 => ram_data( 4) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00100"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 10 => flash_temp <= flashram_data_o; + when 11 => ram_data( 5) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00101"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 12 => flash_temp <= flashram_data_o; + when 13 => ram_data( 6) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00110"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 14 => flash_temp <= flashram_data_o; + when 15 => ram_data( 7) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "00111"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 16 => flash_temp <= flashram_data_o; + when 17 => ram_data( 8) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01000"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 18 => flash_temp <= flashram_data_o; + when 19 => ram_data( 9) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01001"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 20 => flash_temp <= flashram_data_o; + when 21 => ram_data(10) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01010"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 22 => flash_temp <= flashram_data_o; + when 23 => ram_data(11) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01011"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 24 => flash_temp <= flashram_data_o; + when 25 => ram_data(12) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01100"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 26 => flash_temp <= flashram_data_o; + when 27 => ram_data(13) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01101"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 28 => flash_temp <= flashram_data_o; + when 29 => ram_data(14) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01110"; + pwm_data_ii <= flashram_data_o & flash_temp; + when 30 => flash_temp <= flashram_data_o; + when 31 => ram_data(15) <= flashram_data_o & flash_temp; + pwm_write_ii <= '1'; + pwm_addr_ii <= "01111"; + pwm_data_ii <= flashram_data_o & flash_temp; + when others => null; + end case ; + + elsif flash_command = '1' and ufm_bus_ready_out = '1' then + -- save data from registers to UFM + ufm_bus_ready_in <= '1'; + case to_integer ( ufm_databyte_counter ) is + when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0); + when 1 => flashram_data_i <= ram_data( 0)(15 downto 8); + when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0); + when 3 => flashram_data_i <= ram_data( 1)(15 downto 8); + when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0); + when 5 => flashram_data_i <= ram_data( 2)(15 downto 8); + when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0); + when 7 => flashram_data_i <= ram_data( 3)(15 downto 8); + when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0); + when 9 => flashram_data_i <= ram_data( 4)(15 downto 8); + when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0); + when 11 => flashram_data_i <= ram_data( 5)(15 downto 8); + when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0); + when 13 => flashram_data_i <= ram_data( 6)(15 downto 8); + when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0); + when 15 => flashram_data_i <= ram_data( 7)(15 downto 8); + when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0); + when 17 => flashram_data_i <= ram_data( 8)(15 downto 8); + when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0); + when 19 => flashram_data_i <= ram_data( 9)(15 downto 8); + when 20 => flashram_data_i <= ram_data(10)( 7 downto 0); + when 21 => flashram_data_i <= ram_data(10)(15 downto 8); + when 22 => flashram_data_i <= ram_data(11)( 7 downto 0); + when 23 => flashram_data_i <= ram_data(11)(15 downto 8); + when 24 => flashram_data_i <= ram_data(12)( 7 downto 0); + when 25 => flashram_data_i <= ram_data(12)(15 downto 8); + when 26 => flashram_data_i <= ram_data(13)( 7 downto 0); + when 27 => flashram_data_i <= ram_data(13)(15 downto 8); + when 28 => flashram_data_i <= ram_data(14)( 7 downto 0); + when 29 => flashram_data_i <= ram_data(14)(15 downto 8); + when 30 => flashram_data_i <= ram_data(15)( 7 downto 0); + when 31 => flashram_data_i <= ram_data(15)(15 downto 8); + when others => null ; + end case ; + + elsif ram_spi_write = '1' then + ram_data(to_integer(unsigned(ram_spi_addr))) <= ram_spi_data; + end if ; +end process ; -- 2.43.0