From 5aaa3058781cf7c14d9c540bea788f0e89368930 Mon Sep 17 00:00:00 2001 From: palka Date: Thu, 21 Aug 2008 10:06:33 +0000 Subject: [PATCH] no trb, veto only for timing and is connectedto CTU as a trigger source --- oldfiles/vulom3/bus_data_com5.vhd | 1267 ++++++++--------- oldfiles/vulom3/eco_delay.vhd | 4 +- oldfiles/vulom3/new_downscale_ck.vhd | 157 ++- oldfiles/vulom3/set_width_special.vhd | 98 +- oldfiles/vulom3/trig_box1.vhd | 1795 +++++++++++++------------ oldfiles/vulom3/ulogic.vhd | 19 +- oldfiles/vulom3/vlogic_1.vhd | 15 +- 7 files changed, 1765 insertions(+), 1590 deletions(-) diff --git a/oldfiles/vulom3/bus_data_com5.vhd b/oldfiles/vulom3/bus_data_com5.vhd index 861f5a1..e1f18a5 100644 --- a/oldfiles/vulom3/bus_data_com5.vhd +++ b/oldfiles/vulom3/bus_data_com5.vhd @@ -54,7 +54,11 @@ entity bus_data_com5 is dtu_bus_t : out std_logic; dtu_bus_ts : out std_logic; dtu_bus_td : out std_logic_vector (3 downto 0); - out_inhibit : in std_logic + DTU_CODE_SELECT : in std_logic_vector(4 downto 0); + out_inhibit : in std_logic; + cal_inhibit : in std_logic; + DEBUG_REG_01 : out std_logic_vector(15 downto 0); + TRB_BUSY_ENABLE : in std_logic ); end bus_data_com5; @@ -90,610 +94,673 @@ signal ack_accu, retx_accu : std_logic_vector(3 downto 0); signal gts_from_trb, cal_trigger_from_trb : std_logic:='0'; signal trb_go_norm, trb_go_norm_s, trb_go_calib, trb_go_calib_s, trb_finished : std_logic; signal dtu_start : std_logic; - +signal dtu_code : std_logic_vector(3 downto 0); +signal prepared_code : std_logic_vector(3 downto 0); begin - - delay : process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - scaler_pti1_s <= scaler_pti1; - scaler_pti2_s <= scaler_pti2; - scaler_pti3_s <= scaler_pti3; - scaler_pti4_s <= scaler_pti4; - scaler_pti5_s <= scaler_pti5; - scaler_ts_s <= scaler_ts; - scaler_vs_s <= scaler_vs; - scaler_dead_s <= scaler_dead; - latch_s <= latch; - latch_dsc_s <= latch_dsc; - bus_busy_s <= bus_busy; - bus_ack_s <= bus_ack; - bus_retx_s <= bus_retx; - end if; - end process; - - - input_gts : process(clk_300MHz) - begin - if rising_edge(clk_300MHz) then - if gts_dtu_r = '1' then --gts latch for trb bus - gts_dtu_q <= '0'; - elsif gts_pulse = '1' then - gts_dtu_q <= '1'; - end if; - - dtu_inhibit <= (not com_run) or dtu_start; - end if; - end process; - - - input_cal : process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - cal_trigger_s <= cal_trigger; - cal_trigger_d1 <= cal_trigger_s; - cal_trigger_pulse <= cal_trigger_s and not cal_trigger_d1 and not out_inhibit; - end if; - end process; - + delay : process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + scaler_pti1_s <= scaler_pti1; + scaler_pti2_s <= scaler_pti2; + scaler_pti3_s <= scaler_pti3; + scaler_pti4_s <= scaler_pti4; + scaler_pti5_s <= scaler_pti5; + scaler_ts_s <= scaler_ts; + scaler_vs_s <= scaler_vs; + scaler_dead_s <= scaler_dead; + latch_s <= latch; + latch_dsc_s <= latch_dsc; + bus_busy_s <= bus_busy; + bus_ack_s <= bus_ack; + bus_retx_s <= bus_retx; + end if; + end process; + input_gts : process(clk_300MHz) + begin + if rising_edge(clk_300MHz) then + if gts_dtu_r = '1' then --gts latch for trb bus + gts_dtu_q <= '0'; + elsif gts_pulse = '1' then + gts_dtu_q <= '1'; + end if; + dtu_inhibit <= (not com_run) or dtu_start; +-- dtu_inhibit <= dtu_start; + end if; + end process; + input_cal : process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + cal_trigger_s <= cal_trigger; + cal_trigger_d1 <= cal_trigger_s; + cal_trigger_pulse <= cal_trigger_s and not cal_trigger_d1 and not out_inhibit; + end if; + end process; ---------------------------------------------------------------------- TRB comm - - fsm : process(clk_100MHz) --TX lenght: 3.1-3.2 µs - begin - if rising_edge(clk_100MHz) then - case state_a is - - when ready => - ecl_bus_data <= "00"; - ecl_bus_clk <= '0'; - bus_inhibit <= '0'; - trb_finished <= '1'; - trb_go_norm_s <= trb_go_norm; - trb_go_calib_s <= trb_go_calib; - if (trb_go_norm or trb_go_calib) = '1' then - state_a <= start_sequence_0; - else state_a <= ready; - end if; + fsm : process(clk_100MHz) --TX lenght: 3.1-3.2 µs + begin + if rising_edge(clk_100MHz) then + if com_run = '0' then + state_a <= ready; + else + case state_a is + when ready => + DEBUG_REG_01(4 downto 0) <= "00001"; + ecl_bus_data <= "00"; + ecl_bus_clk <= '0'; + bus_inhibit <= '0'; + trb_finished <= '1'; + trb_go_norm_s <= trb_go_norm; + trb_go_calib_s <= trb_go_calib; + if (trb_go_norm or trb_go_calib) = '1' then + state_a <= start_sequence_0; + else state_a <= ready; + end if; ---------------------------- - when start_sequence_0 => - trb_finished <= '0'; - bus_inhibit <= '1'; - ecl_bus_data <= "01"; - ecl_bus_clk <= '0'; - ack_accu <= "0000"; - retx_accu <= "0000"; - state_a <= start_sequence_1; - - when start_sequence_1 => - gts_trb_r <= '1'; - ecl_bus_clk <= '1'; - state_a <= start_sequence_2; - - when start_sequence_2 => - ecl_bus_data <= "10"; - ecl_bus_clk <= '0'; - state_a <= start_sequence_3; - - when start_sequence_3 => - ecl_bus_clk <= '1'; - state_a <= start_sequence_4; - - when start_sequence_4 => - ecl_bus_data <= "01"; - ecl_bus_clk <= '0'; - state_a <= start_sequence_5; - - when start_sequence_5 => - ecl_bus_clk <= '1'; - state_a <= start_sequence_6; - - when start_sequence_6 => - ecl_bus_data <= "10"; - ecl_bus_clk <= '0'; - state_a <= start_sequence_7; - - when start_sequence_7 => - ecl_bus_clk <= '1'; - if trb_go_norm_s = '1' then - state_a <= normal_code_0; - elsif trb_go_calib_s = '1' then - state_a <= calib_code_0; - else state_a <= ready; - end if; + when start_sequence_0 => + DEBUG_REG_01(4 downto 0) <= "00010"; + trb_finished <= '0'; + bus_inhibit <= '1'; + ecl_bus_data <= "01"; + ecl_bus_clk <= '0'; + ack_accu <= "0000"; + retx_accu <= "0000"; + state_a <= start_sequence_1; + when start_sequence_1 => + DEBUG_REG_01(4 downto 0) <= "00011"; + gts_trb_r <= '1'; + ecl_bus_clk <= '1'; + state_a <= start_sequence_2; + when start_sequence_2 => + DEBUG_REG_01(4 downto 0) <= "00100"; + ecl_bus_data <= "10"; + ecl_bus_clk <= '0'; + state_a <= start_sequence_3; + when start_sequence_3 => + DEBUG_REG_01(4 downto 0) <= "00101"; + ecl_bus_clk <= '1'; + state_a <= start_sequence_4; + when start_sequence_4 => + DEBUG_REG_01(4 downto 0) <= "00110"; + ecl_bus_data <= "01"; + ecl_bus_clk <= '0'; + state_a <= start_sequence_5; + when start_sequence_5 => + DEBUG_REG_01(4 downto 0) <= "00111"; + ecl_bus_clk <= '1'; + state_a <= start_sequence_6; + when start_sequence_6 => + DEBUG_REG_01(4 downto 0) <= "01000"; + ecl_bus_data <= "10"; + ecl_bus_clk <= '0'; + state_a <= start_sequence_7; + when start_sequence_7 => + DEBUG_REG_01(4 downto 0) <= "01001"; + ecl_bus_clk <= '1'; + if trb_go_norm_s = '1' then + state_a <= normal_code_0; + elsif trb_go_calib_s = '1' then + state_a <= calib_code_0; + else state_a <= ready; + end if; ---------------------------------------------- - when normal_code_0 => - ecl_bus_data <= "01"; - ecl_bus_clk <= '0'; - state_a <= normal_code_1; - - when normal_code_1 => - checksum <= x"00000001"; - ecl_bus_clk <= '1'; - state_a <= xfer_0; - - when calib_code_0 => - ecl_bus_data <= "11"; - ecl_bus_clk <= '0'; - state_a <= calib_code_1; - - when calib_code_1 => - checksum <= x"00000003"; - ecl_bus_clk <= '1'; - state_a <= xfer_0; + when normal_code_0 => + DEBUG_REG_01(4 downto 0) <= "01010"; + ecl_bus_data <= "01"; + ecl_bus_clk <= '0'; + state_a <= normal_code_1; + when normal_code_1 => + DEBUG_REG_01(4 downto 0) <= "01011"; + checksum <= x"00000001"; + ecl_bus_clk <= '1'; + state_a <= xfer_0; + when calib_code_0 => + DEBUG_REG_01(4 downto 0) <= "01100"; + ecl_bus_data <= "11"; + ecl_bus_clk <= '0'; + state_a <= calib_code_1; + when calib_code_1 => + DEBUG_REG_01(4 downto 0) <= "01101"; + checksum <= x"00000003"; + ecl_bus_clk <= '1'; + state_a <= xfer_0; --------------------------------------------------- - when xfer_0 => - checksum <= checksum + xfer_buffer; - ecl_bus_data <= xfer_buffer(1 downto 0); - ecl_bus_clk <= '0'; - state_a <= xfer_1; - - when xfer_0alter => - ecl_bus_data <= xfer_buffer(1 downto 0); - ecl_bus_clk <= '0'; - state_a <= xfer_1; - - when xfer_1 => - ecl_bus_clk <= '1'; - state_a <= xfer_2; - - when xfer_2 => - ecl_bus_data <= xfer_buffer(3 downto 2); - ecl_bus_clk <= '0'; - state_a <= xfer_3; - - when xfer_3 => - ecl_bus_clk <= '1'; - state_a <= xfer_4; - - when xfer_4 => - ecl_bus_data <= xfer_buffer(5 downto 4); - ecl_bus_clk <= '0'; - state_a <= xfer_5; - - when xfer_5 => - ecl_bus_clk <= '1'; - state_a <= xfer_6; - - when xfer_6 => - ecl_bus_data <= xfer_buffer(7 downto 6); - ecl_bus_clk <= '0'; - state_a <= xfer_7; - - when xfer_7 => - ecl_bus_clk <= '1'; - state_a <= xfer_8; - - when xfer_8 => - ecl_bus_data <= xfer_buffer(9 downto 8); - ecl_bus_clk <= '0'; - state_a <= xfer_9; - - when xfer_9 => - ecl_bus_clk <= '1'; - state_a <= xfer_10; - - when xfer_10 => - ecl_bus_data <= xfer_buffer(11 downto 10); - ecl_bus_clk <= '0'; - state_a <= xfer_11; - - when xfer_11 => - ecl_bus_clk <= '1'; - state_a <= xfer_12; - - when xfer_12 => - ecl_bus_data <= xfer_buffer(13 downto 12); - ecl_bus_clk <= '0'; - state_a <= xfer_13; - - when xfer_13 => - ecl_bus_clk <= '1'; - state_a <= xfer_14; - - when xfer_14 => - ecl_bus_data <= xfer_buffer(15 downto 14); - ecl_bus_clk <= '0'; - state_a <= xfer_15; - - when xfer_15 => - ecl_bus_clk <= '1'; - state_a <= xfer_6; - if state_b = checksum_0 then - state_a <= xfer_0alter; - elsif state_b = checksum_1 then - state_a <= xfer_0alter; - elsif state_b = finished then - state_a <= wait_for_busy; - else state_a <= xfer_0; - end if; ------------------------------------------------------ - when wait_for_busy => - ecl_bus_clk <= '0'; - ecl_bus_data <= "00"; - state_a <= hold_busy; - - when hold_busy => - if bus_ack_s = '0' and ack_accu /= "0000" then --ack accumulator - ack_accu <= ack_accu - 1; - elsif bus_ack_s = '1' and ack_accu /= "1111" then - ack_accu <= ack_accu + 1; - end if; - - if bus_retx_s = '0' and retx_accu /= "0000" then --retransmit accumulator - retx_accu <= retx_accu - 1; - elsif bus_retx_s = '1' and retx_accu /= "1111" then - retx_accu <= retx_accu + 1; - end if; - - if retx_accu = 10 then - state_a <= start_sequence_0; - elsif (ack_accu = 10 or com_run = '0') then - state_a <= ready; - else state_a <= hold_busy; - end if; ---------------------------------------------------------------------- - when others => - state_a <= ready; - - end case; - end if; - end process; - - - fsm2 : process(clk_100MHz) - begin - if rising_edge(clk_100MHz) then - case state_b is - - when tag => - xfer_buffer <= tag_counter_dtu - 1; - if state_a = xfer_13 then - state_b <= latches; - else state_b <= tag; - end if; - - when latches => - xfer_buffer <= '0' & latch_dsc_s & '0' & latch_s; - if state_a = xfer_13 then - state_b <= scalers_0; - else state_b <= latches; - end if; - - when scalers_0 => - xfer_buffer <= scaler_pti1_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_1; - else state_b <= scalers_0; - end if; - - when scalers_1 => - xfer_buffer <= scaler_pti1_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_2; - else state_b <= scalers_1; - end if; - - when scalers_2 => - xfer_buffer <= scaler_pti2_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_3; - else state_b <= scalers_2; - end if; - - when scalers_3 => - xfer_buffer <= scaler_pti2_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_4; - else state_b <= scalers_3; - end if; - - when scalers_4 => - xfer_buffer <= scaler_pti3_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_5; - else state_b <= scalers_4; - end if; - - when scalers_5 => - xfer_buffer <= scaler_pti3_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_6; - else state_b <= scalers_5; - end if; - - when scalers_6 => - xfer_buffer <= scaler_pti4_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_7; - else state_b <= scalers_6; - end if; - - when scalers_7 => - xfer_buffer <= scaler_pti4_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_8; - else state_b <= scalers_7; - end if; - - when scalers_8 => - xfer_buffer <= scaler_pti5_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_9; - else state_b <= scalers_8; - end if; - - when scalers_9 => - xfer_buffer <= scaler_pti5_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_10; - else state_b <= scalers_9; - end if; - - when scalers_10 => - xfer_buffer <= scaler_ts_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_11; - else state_b <= scalers_10; - end if; - - when scalers_11 => - xfer_buffer <= scaler_ts_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_12; - else state_b <= scalers_11; - end if; - - when scalers_12 => - xfer_buffer <= scaler_vs_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_13; - else state_b <= scalers_12; - end if; - - when scalers_13 => - xfer_buffer <= scaler_vs_s(31 downto 16); - if state_a = xfer_13 then - state_b <= scalers_14; - else state_b <= scalers_13; - end if; - - when scalers_14 => - xfer_buffer <= scaler_dead_s(15 downto 0); - if state_a = xfer_13 then - state_b <= scalers_15; - else state_b <= scalers_14; - end if; - - when scalers_15 => - xfer_buffer <= scaler_dead_s(31 downto 16); - if state_a = xfer_13 then - state_b <= checksum_0; - else state_b <= scalers_15; - end if; - - when checksum_0 => - xfer_buffer <= checksum(15 downto 0); - if state_a = xfer_13 then - state_b <= checksum_1; - else state_b <= checksum_0; - end if; - - when checksum_1 => - xfer_buffer <= checksum(31 downto 16); - if state_a = xfer_13 then - state_b <= finished; - else state_b <= checksum_1; - end if; - - when finished => - xfer_buffer <= x"0000"; - if state_a = wait_for_busy then - state_b <= tag; - else state_b <= finished; - end if; - - when others => - state_b <= tag; - - end case; - end if; - end process; ----------------------------------------------------------------------- DTU comm - fsm3 : process(clk_100MHz) --TX lenght: 470 ns + wait time (currently 2.5 µs total) - begin - if rising_edge(clk_100MHz) then - case state_c is - - when idle => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"d"; - count <= 0; - trb_go_norm <= '0'; - trb_go_calib <= '0'; - gts_dtu_r <= '0'; - dtu_start <= '0'; - com_run_s <= com_run; - if com_run = '1' and com_run_s = '0' then - state_c <= begin_run_0; - elsif com_run = '0' and com_run_s = '1' then - state_c <= end_run_0; - elsif gts_dtu_q = '1' and com_run = '1' then - state_c <= norm_event_0; - elsif cal_trigger_pulse = '1' and com_run = '1' then - state_c <= calib_event_0; - else state_c <= idle; - end if; ------------------------------------- - when begin_run_0 => - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"d"; - tag_counter_dtu <= x"0000"; - dtu_start <= '1'; - count <= count + 1; - if count = 4 then - state_c <= begin_run_1; - else state_c <= begin_run_0; - end if; - - when begin_run_1 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 9 then - state_c <= tag_low_0; - else state_c <= begin_run_1; - end if; -------------------------------------- - when end_run_0 => - trb_run_s <= '0'; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"e"; - count <= count + 1; - if count = 4 then - state_c <= end_run_1; - else state_c <= end_run_0; - end if; - - when end_run_1 => - trb_run <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 9 then - state_c <= tag_low_0; - else state_c <= end_run_1; - end if; --------------------------------------- - when norm_event_0 => - trb_go_norm <= '1'; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"1"; - count <= count + 1; - if count = 4 then - state_c <= norm_event_1; - else state_c <= norm_event_0; - end if; - - when norm_event_1 => - trb_go_norm <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 9 then - state_c <= tag_low_0; - else state_c <= norm_event_1; - end if; + when xfer_0 => + DEBUG_REG_01(4 downto 0) <= "01110"; + checksum <= checksum + xfer_buffer; + ecl_bus_data <= xfer_buffer(1 downto 0); + ecl_bus_clk <= '0'; + state_a <= xfer_1; + when xfer_0alter => + DEBUG_REG_01(4 downto 0) <= "01111"; + ecl_bus_data <= xfer_buffer(1 downto 0); + ecl_bus_clk <= '0'; + state_a <= xfer_1; + when xfer_1 => + DEBUG_REG_01(4 downto 0) <= "10000"; + ecl_bus_clk <= '1'; + state_a <= xfer_2; + when xfer_2 => + DEBUG_REG_01(4 downto 0) <= "10001"; + ecl_bus_data <= xfer_buffer(3 downto 2); + ecl_bus_clk <= '0'; + state_a <= xfer_3; + when xfer_3 => + DEBUG_REG_01(4 downto 0) <= "10010"; + ecl_bus_clk <= '1'; + state_a <= xfer_4; + when xfer_4 => + DEBUG_REG_01(4 downto 0) <= "10011"; + ecl_bus_data <= xfer_buffer(5 downto 4); + ecl_bus_clk <= '0'; + state_a <= xfer_5; + when xfer_5 => + DEBUG_REG_01(4 downto 0) <= "10100"; + ecl_bus_clk <= '1'; + state_a <= xfer_6; + when xfer_6 => + DEBUG_REG_01(4 downto 0) <= "10101"; + ecl_bus_data <= xfer_buffer(7 downto 6); + ecl_bus_clk <= '0'; + state_a <= xfer_7; + when xfer_7 => + DEBUG_REG_01(4 downto 0) <= "10110"; + ecl_bus_clk <= '1'; + state_a <= xfer_8; + when xfer_8 => + DEBUG_REG_01(4 downto 0) <= "10111"; + ecl_bus_data <= xfer_buffer(9 downto 8); + ecl_bus_clk <= '0'; + state_a <= xfer_9; + when xfer_9 => + DEBUG_REG_01(4 downto 0) <= "11000"; + ecl_bus_clk <= '1'; + state_a <= xfer_10; + when xfer_10 => + DEBUG_REG_01(4 downto 0) <= "11001"; + ecl_bus_data <= xfer_buffer(11 downto 10); + ecl_bus_clk <= '0'; + state_a <= xfer_11; + + when xfer_11 => + DEBUG_REG_01(4 downto 0) <= "11010"; + ecl_bus_clk <= '1'; + state_a <= xfer_12; + when xfer_12 => + DEBUG_REG_01(4 downto 0) <= "11011"; + ecl_bus_data <= xfer_buffer(13 downto 12); + ecl_bus_clk <= '0'; + state_a <= xfer_13; + when xfer_13 => + DEBUG_REG_01(4 downto 0) <= "11100"; + ecl_bus_clk <= '1'; + state_a <= xfer_14; + when xfer_14 => + DEBUG_REG_01(4 downto 0) <= "11101"; + ecl_bus_data <= xfer_buffer(15 downto 14); + ecl_bus_clk <= '0'; + state_a <= xfer_15; + when xfer_15 => + DEBUG_REG_01(4 downto 0) <= "11110"; + ecl_bus_clk <= '1'; + state_a <= xfer_6; + if state_b = checksum_0 then + state_a <= xfer_0alter; + elsif state_b = checksum_1 then + state_a <= xfer_0alter; + elsif state_b = finished then + state_a <= wait_for_busy; + else state_a <= xfer_0; + end if; +----------------------------------------------------- + when wait_for_busy => + DEBUG_REG_01(4 downto 0) <= "11110"; + ecl_bus_clk <= '0'; + ecl_bus_data <= "00"; + state_a <= hold_busy; + when hold_busy => + DEBUG_REG_01(4 downto 0) <= "11111"; + if bus_ack_s = '0' and ack_accu /= "0000" then --ack accumulator + ack_accu <= ack_accu - 1; + elsif bus_ack_s = '1' and ack_accu /= "1111" then + ack_accu <= ack_accu + 1; + end if; + if bus_retx_s = '0' and retx_accu /= "0000" then --retransmit accumulator + retx_accu <= retx_accu - 1; + elsif bus_retx_s = '1' and retx_accu /= "1111" then + retx_accu <= retx_accu + 1; + end if; + if retx_accu = 10 then + state_a <= start_sequence_0; + elsif (ack_accu = 10 or com_run = '0') or TRB_BUSY_ENABLE = '0' then + state_a <= ready; + else state_a <= hold_busy; + end if; +--------------------------------------------------------------------- + when others => + DEBUG_REG_01(4 downto 0) <= "00000"; + state_a <= ready; + end case; + end if; + end if; + end process; + fsm2 : process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + if com_run = '0' then + state_b <= tag; + else + case state_b is + when tag => + DEBUG_REG_01(9 downto 5) <= "00001"; + xfer_buffer <= tag_counter_dtu - 1; + if state_a = xfer_13 then + state_b <= latches; + else state_b <= tag; + end if; + when latches => + DEBUG_REG_01(9 downto 5) <= "00010"; + xfer_buffer <= '0' & latch_dsc_s & '0' & latch_s; + if state_a = xfer_13 then + state_b <= scalers_0; + else state_b <= latches; + end if; + when scalers_0 => + DEBUG_REG_01(9 downto 5) <= "00011"; + xfer_buffer <= scaler_pti1_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_1; + else state_b <= scalers_0; + end if; + when scalers_1 => + DEBUG_REG_01(9 downto 5) <= "00100"; + xfer_buffer <= scaler_pti1_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_2; + else state_b <= scalers_1; + end if; + when scalers_2 => + DEBUG_REG_01(9 downto 5) <= "00101"; + xfer_buffer <= scaler_pti2_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_3; + else state_b <= scalers_2; + end if; + when scalers_3 => + DEBUG_REG_01(9 downto 5) <= "00110"; + xfer_buffer <= scaler_pti2_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_4; + else state_b <= scalers_3; + end if; + when scalers_4 => + DEBUG_REG_01(9 downto 5) <= "00111"; + xfer_buffer <= scaler_pti3_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_5; + else state_b <= scalers_4; + end if; + when scalers_5 => + DEBUG_REG_01(9 downto 5) <= "01000"; + xfer_buffer <= scaler_pti3_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_6; + else state_b <= scalers_5; + end if; + when scalers_6 => + DEBUG_REG_01(9 downto 5) <= "01001"; + xfer_buffer <= scaler_pti4_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_7; + else state_b <= scalers_6; + end if; + when scalers_7 => + DEBUG_REG_01(9 downto 5) <= "01010"; + xfer_buffer <= scaler_pti4_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_8; + else state_b <= scalers_7; + end if; + when scalers_8 => + DEBUG_REG_01(9 downto 5) <= "01011"; + xfer_buffer <= scaler_pti5_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_9; + else state_b <= scalers_8; + end if; + when scalers_9 => + DEBUG_REG_01(9 downto 5) <= "01100"; + xfer_buffer <= scaler_pti5_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_10; + else state_b <= scalers_9; + end if; + when scalers_10 => + DEBUG_REG_01(9 downto 5) <= "01110"; + xfer_buffer <= scaler_ts_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_11; + else state_b <= scalers_10; + end if; + when scalers_11 => + DEBUG_REG_01(9 downto 5) <= "01111"; + xfer_buffer <= scaler_ts_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_12; + else state_b <= scalers_11; + end if; + when scalers_12 => + DEBUG_REG_01(9 downto 5) <= "10000"; + xfer_buffer <= scaler_vs_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_13; + else state_b <= scalers_12; + end if; + when scalers_13 => + DEBUG_REG_01(9 downto 5) <= "10001"; + xfer_buffer <= scaler_vs_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_14; + else state_b <= scalers_13; + end if; + when scalers_14 => + DEBUG_REG_01(9 downto 5) <= "10010"; + xfer_buffer <= scaler_dead_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_15; + else state_b <= scalers_14; + end if; + when scalers_15 => + DEBUG_REG_01(9 downto 5) <= "10011"; + xfer_buffer <= scaler_dead_s(31 downto 16); + if state_a = xfer_13 then + state_b <= checksum_0; + else state_b <= scalers_15; + end if; + when checksum_0 => + DEBUG_REG_01(9 downto 5) <= "10101"; + xfer_buffer <= checksum(15 downto 0); + if state_a = xfer_13 then + state_b <= checksum_1; + else state_b <= checksum_0; + end if; + when checksum_1 => + DEBUG_REG_01(9 downto 5) <= "10110"; + xfer_buffer <= checksum(31 downto 16); + if state_a = xfer_13 then + state_b <= finished; + else state_b <= checksum_1; + end if; + when finished => + DEBUG_REG_01(9 downto 5) <= "10111"; + xfer_buffer <= x"0000"; + if state_a = wait_for_busy then + state_b <= tag; + else state_b <= finished; + end if; + when others => + DEBUG_REG_01(9 downto 5) <= "00000"; + state_b <= tag; + end case; + end if; + end if; + end process; +---------------------------------------------------------------------- DTU comm + PREPARE_CODE_FOR_DTU: process (clk_100MHz) + begin -- process PREPARE_CODE_FOR_DTU + if rising_edge(clk_100MHz) then + if com_run_s = '0' then + prepared_code <= x"d"; + elsif com_run_s = '1' and cal_inhibit = '0' then + prepared_code <= dtu_code; + elsif com_run_s = '1' and cal_inhibit = '1' then + prepared_code <= x"9"; + else + prepared_code <= dtu_code; + end if; + end if; + end process PREPARE_CODE_FOR_DTU; + DTU_CODE_CHANGE : process (clk_100MHz) + begin -- process DTU_CODE_CHANGE + if rising_edge (clk_100MHz) then + if DTU_CODE_SELECT(4) = '0' then + dtu_code <= x"1"; + else + dtu_code <= DTU_CODE_SELECT(3 downto 0); + end if; + end if; + end process DTU_CODE_CHANGE; + fsm3 : process(clk_100MHz) --TX lenght: 470 ns + wait time (currently 2.5 µs total) + begin + if rising_edge(clk_100MHz) then + if com_run = '0' then + state_c <= idle; + com_run_s <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"d"; + count <= 0; + trb_go_norm <= '0'; + trb_go_calib <= '0'; + gts_dtu_r <= '0'; + dtu_start <= '0'; + else + -- implemented default value + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; +-- dtu_bus_td <= x"d"; + dtu_bus_td <= prepared_code; + case state_c is + when idle => + DEBUG_REG_01(14 downto 10)<= "00001"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; +-- dtu_bus_td <= x"d"; + count <= 0; + trb_go_norm <= '0'; + trb_go_calib <= '0'; + gts_dtu_r <= '0'; + dtu_start <= '0'; +-- com_run_s <= com_run; +-- if com_run = '1' and com_run_s = '0' then + if com_run = '1' and com_run_s = '0' then + state_c <= begin_run_0; +-- elsif com_run = '0' and com_run_s = '1' then +-- state_c <= end_run_0; + elsif gts_dtu_q = '1' and com_run = '1' then + state_c <= norm_event_0; + elsif cal_trigger_pulse = '1' and com_run = '1' then + state_c <= calib_event_0; + else state_c <= idle; + end if; +------------------------------------ + when begin_run_0 => + DEBUG_REG_01(14 downto 10)<= "00010"; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"d"; + -- trb_go_norm <= '1'; + tag_counter_dtu <= x"0000"; + com_run_s <= '1'; + dtu_start <= '1'; + count <= count + 1; + if count = 4+5 then + state_c <= begin_run_1; + else state_c <= begin_run_0; + end if; + when begin_run_1 => + DEBUG_REG_01(14 downto 10)<= "00011"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"d"; + count <= count + 1; + if count = 9+10 then + state_c <= tag_low_0; + else state_c <= begin_run_1; + end if; +------------------------------------- + when end_run_0 => + DEBUG_REG_01(14 downto 10)<= "00100"; + trb_run_s <= '0'; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"e"; + count <= count + 1; + if count = 4+5 then + state_c <= end_run_1; + else state_c <= end_run_0; + end if; + when end_run_1 => + DEBUG_REG_01(14 downto 10)<= "00101"; + trb_run <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 9+10 then + state_c <= tag_low_0; + else state_c <= end_run_1; + end if; +-------------------------------------- + when norm_event_0 => + DEBUG_REG_01(14 downto 10)<= "00110"; + trb_go_norm <= '1'; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= dtu_code;-- "1"; + count <= count + 1; + if count = 4+5 then + state_c <= norm_event_1; + else state_c <= norm_event_0; + end if; + when norm_event_1 => + DEBUG_REG_01(14 downto 10)<= "00111"; + trb_go_norm <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= dtu_code; + count <= count + 1; + if count = 9+10 then + state_c <= tag_low_0; + else state_c <= norm_event_1; + end if; --------------------------------------- - when calib_event_0 => - trb_go_calib <= '1'; - dtu_bus_t <= '1'; - dtu_bus_ts <= '0'; - dtu_bus_td <= x"9"; - count <= count + 1; - if count = 4 then - state_c <= calib_event_1; - else state_c <= calib_event_0; - end if; - - when calib_event_1 => - trb_go_calib <= '0'; - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 9 then - state_c <= tag_low_0; - else state_c <= calib_event_1; - end if; + when calib_event_0 => + DEBUG_REG_01(14 downto 10)<= "01000"; + trb_go_calib <= '1'; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"9"; + count <= count + 1; + if count = 4+5 then + state_c <= calib_event_1; + else state_c <= calib_event_0; + end if; + when calib_event_1 => + DEBUG_REG_01(14 downto 10)<= "01001"; + trb_go_calib <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"9"; + count <= count + 1; + if count = 9+10 then + state_c <= tag_low_0; + else state_c <= calib_event_1; + end if; --------------------------------------------------------- - when tag_low_0 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '1'; - dtu_bus_td <= tag_counter_dtu(3 downto 0); - count <= count + 1; - if count = 14 then - state_c <= tag_low_1; - else state_c <= tag_low_0; - end if; - - when tag_low_1 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 19 then - state_c <= tag_high_0; - else state_c <= tag_low_1; - end if; - - when tag_high_0 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '1'; - dtu_bus_td <= tag_counter_dtu(7 downto 4); - count <= count + 1; - if count = 24 then - state_c <= tag_high_1; - else state_c <= tag_high_0; - end if; - - when tag_high_1 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 29 then - state_c <= tag_prio_0; - else state_c <= tag_high_1; - end if; - - when tag_prio_0 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '1'; - dtu_bus_td <= "0000"; - count <= count + 1; - if count = 34 then - state_c <= tag_prio_1; - else state_c <= tag_prio_0; - end if; - - when tag_prio_1 => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - count <= count + 1; - if count = 39 then - state_c <= wait_last; - else state_c <= tag_prio_1; - end if; - - when wait_last => - dtu_bus_t <= '0'; - dtu_bus_ts <= '0'; - dtu_bus_td <= "0000"; - count <= count + 1; - if count = 244 then --change this to increase wait time (44 default) - state_c <= wait_for_trb; - else state_c <= wait_last; - end if; - - when wait_for_trb => - if trb_finished = '1' then - state_c <= count_incr; - else state_c <= wait_for_trb; - end if; - - when count_incr => - gts_dtu_r <= '1'; - tag_counter_dtu <= tag_counter_dtu + 1; - state_c <= idle; - - - when others => - state_c <= idle; - - end case; - end if; - end process; - - + when tag_low_0 => + DEBUG_REG_01(14 downto 10)<= "01010"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '1'; + dtu_bus_td <= tag_counter_dtu(3 downto 0); + count <= count + 1; + if count = 14+15 then + state_c <= tag_low_1; + else state_c <= tag_low_0; + end if; + when tag_low_1 => + DEBUG_REG_01(14 downto 10)<= "01011"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= tag_counter_dtu(3 downto 0); + count <= count + 1; + if count = 19+20 then + state_c <= tag_high_0; + else state_c <= tag_low_1; + end if; + when tag_high_0 => + DEBUG_REG_01(14 downto 10)<= "01100"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '1'; + dtu_bus_td <= tag_counter_dtu(7 downto 4); + count <= count + 1; + if count = 24+25 then + state_c <= tag_high_1; + else state_c <= tag_high_0; + end if; + when tag_high_1 => + DEBUG_REG_01(14 downto 10)<= "01101"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= tag_counter_dtu(7 downto 4); + count <= count + 1; + if count = 29+30 then + state_c <= tag_prio_0; + else state_c <= tag_high_1; + end if; + when tag_prio_0 => + DEBUG_REG_01(14 downto 10)<= "01110"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '1'; + dtu_bus_td <= tag_counter_dtu(7 downto 4); + count <= count + 1; + if count = 34+35 then + state_c <= tag_prio_1; + else state_c <= tag_prio_0; + end if; + when tag_prio_1 => + DEBUG_REG_01(14 downto 10)<= "01111"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + dtu_bus_td <= tag_counter_dtu(7 downto 4); + if count = 39+40 then + state_c <= wait_last; + else state_c <= tag_prio_1; + end if; + when wait_last => + DEBUG_REG_01(14 downto 10)<= "10000"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; +-- dtu_bus_td <= "0000"; + count <= count + 1; + if count = 244 then --change this to increase wait time (44 default) + state_c <= wait_for_trb; + else state_c <= wait_last; + end if; + when wait_for_trb => + DEBUG_REG_01(14 downto 10)<= "10001"; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; +-- dtu_bus_td <= "0000"; + if trb_finished = '1' or dtu_start = '1' then + state_c <= count_incr; + else state_c <= wait_for_trb; + end if; + when count_incr => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; +-- dtu_bus_td <= "0000"; + DEBUG_REG_01(14 downto 10)<= "10010"; + gts_dtu_r <= '1'; + tag_counter_dtu <= tag_counter_dtu + 1; + state_c <= idle; + when others => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; +-- dtu_bus_td <= "0000"; + DEBUG_REG_01(14 downto 10)<= "00000"; + state_c <= idle; + end case; + end if; + end if; + end process; end Behavioral; diff --git a/oldfiles/vulom3/eco_delay.vhd b/oldfiles/vulom3/eco_delay.vhd index 94186ff..5cae31e 100644 --- a/oldfiles/vulom3/eco_delay.vhd +++ b/oldfiles/vulom3/eco_delay.vhd @@ -39,9 +39,9 @@ begin internal <= signal_in; chain <= (chain (30 downto 0) & (not internal and signal_in)); - if (chain(22) = '1' and chain(31) ='0') then + if (chain(15) = '1') then signal_out_s <= '1'; - elsif (chain(22) = '0' and chain(31) ='1') then + elsif (chain(15) = '0' and chain(27) ='1') then signal_out_s <= '0'; end if; end if; diff --git a/oldfiles/vulom3/new_downscale_ck.vhd b/oldfiles/vulom3/new_downscale_ck.vhd index 4c518d4..1165d24 100644 --- a/oldfiles/vulom3/new_downscale_ck.vhd +++ b/oldfiles/vulom3/new_downscale_ck.vhd @@ -23,6 +23,7 @@ entity new_downscale_ck is port ( clk : in std_logic; downscaled : out std_logic; output_disable : in std_logic; + global_inhibit : in std_logic; scaler_reset : out std_logic; cal_inhibit : out std_logic; cal_trigger : out std_logic); @@ -31,6 +32,7 @@ end new_downscale_ck; architecture Behavioral of new_downscale_ck is signal accu_1 : std_logic_vector(21 downto 0); signal accu_3 : std_logic_vector(15 downto 0); +signal accu_4 : std_logic_vector(15 downto 0); signal count, count_d, clk_10kHz : std_logic; signal accu_2 : std_logic_vector(15 downto 0); signal delay_1, delay_2 : std_logic; @@ -38,76 +40,89 @@ signal delay_1, delay_2 : std_logic; begin - process(clk) --pulser - begin - if rising_edge(clk) then - accu_1 <= accu_1 + 1; - - case downscale_value is - when "0000" => count <= accu_1(6); - when "0001" => count <= accu_1(7); - when "0010" => count <= accu_1(8); - when "0011" => count <= accu_1(9); - when "0100" => count <= accu_1(10); - when "0101" => count <= accu_1(11); - when "0110" => count <= accu_1(12); - when "0111" => count <= accu_1(13); - when "1000" => count <= accu_1(14); - when "1001" => count <= accu_1(15); - when "1010" => count <= accu_1(16); - when "1011" => count <= accu_1(17); - when "1100" => count <= accu_1(18); - when "1101" => count <= accu_1(19); - when "1110" => count <= accu_1(20); - when "1111" => count <= accu_1(21); - when others => count <= 'X'; - end case; - - count_d <= count; - downscaled <= (not count_d) and count; - end if; - end process; - - - process(clk) --10 kHz clock generator - begin - if rising_edge(clk) then - if accu_2 = x"3a97" then - accu_2 <= x"0000"; - clk_10kHz <= not clk_10kHz; - else - accu_2 <= accu_2 + 1; - end if; - end if; - end process; - - - process(clk_10kHz) --calibration pulse - begin - if rising_edge(clk_10kHz) then - if accu_3 = x"0000" then - cal_inhibit <= not output_disable; - cal_trigger <= '0'; - scaler_reset <= '1'; - accu_3 <= accu_3 + 1; - elsif accu_3 = x"0001" then - cal_inhibit <= not output_disable; - cal_trigger <= not output_disable; - scaler_reset <= '0'; - accu_3 <= accu_3 + 1; - elsif accu_3 = x"0002" then - cal_inhibit <= '0'; - cal_trigger <= '0'; - scaler_reset <= '0'; - accu_3 <= accu_3 + 1; - elsif accu_3 = x"270f" then --10e3 - cal_inhibit <= '0'; - cal_trigger <= '0'; - scaler_reset <= '0'; - accu_3 <= x"0000"; - else accu_3 <= accu_3 + 1; - end if; - end if; - end process; + process(clk) --pulser + begin + if rising_edge(clk) then + accu_1 <= accu_1 + 1; + case downscale_value is + when "0000" => count <= accu_1(6); + when "0001" => count <= accu_1(7); + when "0010" => count <= accu_1(8); + when "0011" => count <= accu_1(9); + when "0100" => count <= accu_1(10); + when "0101" => count <= accu_1(11); + when "0110" => count <= accu_1(12); + when "0111" => count <= accu_1(13); + when "1000" => count <= accu_1(14); + when "1001" => count <= accu_1(15); + when "1010" => count <= accu_1(16); + when "1011" => count <= accu_1(17); + when "1100" => count <= accu_1(18); + when "1101" => count <= accu_1(19); + when "1110" => count <= accu_1(20); + when "1111" => count <= accu_1(21); + when others => count <= 'X'; + end case; + count_d <= count; + downscaled <= (not count_d) and count; + end if; + end process; + process(clk) --10 kHz clock generator + begin + if rising_edge(clk) then + if accu_2 = x"3a97" then + accu_2 <= x"0000"; + clk_10kHz <= not clk_10kHz; + else + accu_2 <= accu_2 + 1; + end if; + end if; + end process; + process(clk_10kHz) --calibration pulse + begin + if rising_edge(clk_10kHz) then + if accu_3 = x"0000" then + scaler_reset <= '1'; + accu_3 <= accu_3 + 1; + elsif accu_3 = x"0001" then + scaler_reset <= '0'; + accu_3 <= accu_3 + 1; + elsif accu_3 = x"0002" then + scaler_reset <= '0'; + accu_3 <= accu_3 + 1; + elsif accu_3 = x"270f" then --10e3 + scaler_reset <= '0'; + accu_3 <= x"0000"; + else accu_3 <= accu_3 + 1; + end if; + end if; + end process; + process(clk_10kHz) --calibration pulse + begin + if rising_edge(clk_10kHz) then + if accu_4 = x"0000" and global_inhibit = '0' then + cal_inhibit <= not output_disable; + cal_trigger <= '0'; + accu_4 <= accu_4 + 1; + elsif accu_4 = x"0000" and global_inhibit = '1' then + cal_inhibit <= not output_disable; + cal_trigger <= '0'; + accu_4 <= accu_4; + elsif accu_4 = x"0001" then + cal_inhibit <= not output_disable; + cal_trigger <= not output_disable; + accu_4 <= accu_4 + 1; + elsif accu_4 = x"0002" then + cal_inhibit <= '0'; + cal_trigger <= '0'; + accu_4 <= accu_4 + 1; + elsif accu_4 = x"270f" then --10e3 + cal_inhibit <= '0'; + cal_trigger <= '0'; + accu_4 <= x"0000"; + else accu_4 <= accu_4 + 1; + end if; + end if; + end process; end Behavioral; diff --git a/oldfiles/vulom3/set_width_special.vhd b/oldfiles/vulom3/set_width_special.vhd index 08ef7fa..adebea9 100644 --- a/oldfiles/vulom3/set_width_special.vhd +++ b/oldfiles/vulom3/set_width_special.vhd @@ -19,61 +19,65 @@ library UNISIM; use UNISIM.vcomponents.all; entity set_width_special is port ( - clk : in std_logic; + clk : in std_logic; to_be_set : in std_logic; width_value : in std_logic_vector(3 downto 0); width_adjusted_pulse : out std_logic); end set_width_special; architecture Behavioral of set_width_special is -signal reset, to_be_set_delayed, q : std_logic; -signal shift : std_logic_vector(15 downto 0); +signal reset_timing_signal, clocked_timing_signal : std_logic; +signal timing_signal_counter : std_logic_vector(5 downto 0); +signal start_pulse, end_pulse : std_logic; +signal during_pulse, to_be_set_synch, to_be_set_synch_delayed : std_logic; begin + + SYNCH_TO_BE_SET: process (CLK) + begin + if rising_edge(CLK) then + to_be_set_synch <= to_be_set; + to_be_set_synch_delayed <= to_be_set_synch; + end if; + end process SYNCH_TO_BE_SET; + MAKE_START: process (CLK) + begin + if rising_edge(CLK) then + if to_be_set_synch_delayed = '0' and to_be_set_synch = '1' then + start_pulse <= '1'; + end_pulse <= '0'; + elsif to_be_set_synch_delayed = '1' and to_be_set_synch = '0' then + start_pulse <= '0'; + end_pulse <= '1'; + else + start_pulse <= '0'; + end_pulse <= '0'; + end if; + end if; + end process MAKE_START; + DURING_PULSE_PROC: process (CLK) + begin + if rising_edge(CLK) then + if start_pulse = '1' then + during_pulse <= '1'; + elsif timing_signal_counter(5) = '1' then + during_pulse <= '0'; + end if; + end if; + end process DURING_PULSE_PROC; - process (clk) - begin - if rising_edge(clk) then - if reset = '1' then - q <= '0'; - elsif to_be_set = '1' then - q <= '1'; - end if; - - if q = '0' then - shift <= shift (14 downto 0) & to_be_set; - to_be_set_delayed <= to_be_set; - else - shift <= shift (14 downto 0) & '0'; - to_be_set_delayed <= '0'; - end if; - - case width_value is - when "0000" => reset <= shift(0); - when "0001" => reset <= shift(1); - when "0010" => reset <= shift(2); - when "0011" => reset <= shift(3); - when "0100" => reset <= shift(4); - when "0101" => reset <= shift(5); - when "0110" => reset <= shift(6); - when "0111" => reset <= shift(7); - when "1000" => reset <= shift(8); - when "1001" => reset <= shift(9); - when "1010" => reset <= shift(10); - when "1011" => reset <= shift(11); - when "1100" => reset <= shift(12); - when "1101" => reset <= shift(13); - when "1110" => reset <= shift(14); - when "1111" => reset <= shift(15); - when others => reset <= 'X'; - end case; - - if (to_be_set_delayed = '0' and reset ='1') then - width_adjusted_pulse <= '0'; - elsif (to_be_set_delayed = '1' and reset ='0') then - width_adjusted_pulse <= '1'; - end if; - end if; - end process; + PULSER_LENGHT_COUNTER: process (CLK) + begin + if rising_edge(CLK) then + if during_pulse = '1' then + timing_signal_counter <= timing_signal_counter + 1; + elsif start_pulse = '1' then + timing_signal_counter <= (others => '0'); + else + timing_signal_counter <= timing_signal_counter; + end if; + end if; + end process PULSER_LENGHT_COUNTER; + width_adjusted_pulse <= during_pulse;--to_be_set or during_pulse; end Behavioral; diff --git a/oldfiles/vulom3/trig_box1.vhd b/oldfiles/vulom3/trig_box1.vhd index 0df2182..194ef61 100644 --- a/oldfiles/vulom3/trig_box1.vhd +++ b/oldfiles/vulom3/trig_box1.vhd @@ -19,877 +19,942 @@ library UNISIM; use UNISIM.Vcomponents.ALL; entity trig_box1 is - port (clk_50MHz : in std_logic; - clk_300MHz : in std_logic; - clk_100MHz : in std_logic; - ECL : in std_logic_vector(16 downto 1); - ECO : out std_logic_vector(16 downto 1); - IOO : in std_logic_vector(16 downto 1); - TIN : out std_logic_vector(16 downto 1); - LEMIN : in std_logic_vector(2 downto 1); - LEMOU : out std_logic_vector(2 downto 1); - INPUT_ENABLE : in std_logic_vector(7 downto 1); - DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_1 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_2 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_3 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_4 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0); - DELAY_REGISTER_5 : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0); - DELAY_REGISTER_TS : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0); - DELAY_REGISTER_VS : in std_logic_vector(3 downto 0); - WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0); - DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0); - BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); --(4) enables branch, (3 downto 0) is the width value - WIDTH_OUTPUT : in std_logic_vector(3 downto 0); - MUX_SELECTOR_1 : in std_logic_vector(3 downto 0); - MUX_SELECTOR_2 : in std_logic_vector(3 downto 0); - OR_ON_OFF : in std_logic_vector(7 downto 0); - SCALER_PTI1 : out std_logic_vector(31 downto 0); - SCALER_PTI2 : out std_logic_vector(31 downto 0); - SCALER_PTI3 : out std_logic_vector(31 downto 0); - SCALER_PTI4 : out std_logic_vector(31 downto 0); - SCALER_PTI5 : out std_logic_vector(31 downto 0); - SCALER_TS : out std_logic_vector(31 downto 0); - SCALER_VS : out std_logic_vector(31 downto 0); - SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); -- x"yz" y= mdc channel select, z= tof channel select - SCALER_MDC : out std_logic_vector(31 downto 0); - SCALER_TOF : out std_logic_vector(31 downto 0); - SCALER_RESET : in std_logic_vector(7 downto 0); - PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0); - DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0); - WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0); - WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0); - SCALER_DEAD : out std_logic_vector(31 downto 0); - TS_GATING_DISABLE : in std_logic_vector(7 downto 1); - SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); - SCALER_MUX1 : out std_logic_vector(31 downto 0); - SCALER_MUX2 : out std_logic_vector(31 downto 0); - CAL_TRIGGER_DISABLE : in std_logic; - COM_RUN : in std_logic; - DTU_ERROR : inout std_logic; - hpv : inout std_logic_vector(15 downto 0); - hpw : inout std_logic_vector(15 downto 0) - ); + port (clk_50MHz : in std_logic; + clk_300MHz : in std_logic; + clk_100MHz : in std_logic; + ECL : in std_logic_vector(16 downto 1); + ECO : out std_logic_vector(16 downto 1); + IOO : in std_logic_vector(16 downto 1); + TIN : out std_logic_vector(16 downto 1); + LEMIN : in std_logic_vector(2 downto 1); + LEMOU : out std_logic_vector(2 downto 1); + INPUT_ENABLE : in std_logic_vector(7 downto 1); + DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_1 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_2 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_3 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_4 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_5 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0); + DELAY_REGISTER_TS : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0); + DELAY_REGISTER_VS : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0); + BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); --(4) enables branch, (3 downto 0) is the width value + WIDTH_OUTPUT : in std_logic_vector(3 downto 0); + MUX_SELECTOR_1 : in std_logic_vector(3 downto 0); + MUX_SELECTOR_2 : in std_logic_vector(3 downto 0); + OR_ON_OFF : in std_logic_vector(7 downto 0); + SCALER_PTI1 : out std_logic_vector(31 downto 0); + SCALER_PTI2 : out std_logic_vector(31 downto 0); + SCALER_PTI3 : out std_logic_vector(31 downto 0); + SCALER_PTI4 : out std_logic_vector(31 downto 0); + SCALER_PTI5 : out std_logic_vector(31 downto 0); + SCALER_TS : out std_logic_vector(31 downto 0); + SCALER_VS : out std_logic_vector(31 downto 0); + SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); -- x"yz" y= mdc channel select, z= tof channel select + SCALER_MDC : out std_logic_vector(31 downto 0); + SCALER_TOF : out std_logic_vector(31 downto 0); + SCALER_RESET : in std_logic_vector(7 downto 0); + PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0); + DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0); + WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0); + WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0); + SCALER_DEAD : out std_logic_vector(31 downto 0); + TS_GATING_DISABLE : in std_logic_vector(7 downto 1); + SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_MUX1 : out std_logic_vector(31 downto 0); + SCALER_MUX2 : out std_logic_vector(31 downto 0); + DTU_CODE_SELECT : in std_logic_vector(4 downto 0); + CAL_TRIGGER_DISABLE : in std_logic; + COM_RUN : in std_logic; + DTU_ERROR : inout std_logic; + hpv : inout std_logic_vector(15 downto 0); + hpw : inout std_logic_vector(15 downto 0); + DEBUG_REG_00 : out std_logic_vector(31 downto 0); + TRB_BUSY_ENABLE : in std_logic + ); end trig_box1; + + architecture RTL of trig_box1 is - component one_clock_long port ( - clk : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; - component delay port ( - clk : in std_logic; - to_be_delayed : in std_logic; - delay_value : in std_logic_vector(3 downto 0); - delayed_pulse : out std_logic); - end component; - component downscale port ( - clk : in std_logic; - disable : in std_logic; - to_be_downscaled : in std_logic; - downscale_value : in std_logic_vector(3 downto 0); - downscaled : out std_logic); - end component; - component set_width port ( - clk : in std_logic; - to_be_set : in std_logic; - width_value : in std_logic_vector(3 downto 0); - width_adjusted_pulse : out std_logic); - end component; - component set_width_special port ( - clk : in std_logic; - to_be_set : in std_logic; - width_value : in std_logic_vector(3 downto 0); - width_adjusted_pulse : out std_logic); - end component; - component scaler port ( - clk : in std_logic; - input_pulse : in std_logic; - scaler_reset : in std_logic; - scaler_value : out std_logic_vector(19 downto 0)); - end component; - component scaler_s port ( - clk_300mhz : in std_logic; - clk_100mhz : in std_logic; - input_pulse : in std_logic; - scaler_reset : in std_logic; - scaler_value : out std_logic_vector(31 downto 0)); - end component; - component eco_delay port ( - clk : in std_logic; - signal_in : in std_logic; - signal_out : out std_logic); - end component; - component new_downscale_ck - port( - downscale_value : in std_logic_vector(3 downto 0); - clk : in std_logic; - downscaled : out std_logic; - output_disable : in std_logic; - scaler_reset : out std_logic; - cal_inhibit : out std_logic; - cal_trigger : out std_logic - ); - end component; - component beam_ramp - port( - clk_300mhz : in std_logic; - clk_50mhz : in std_logic; - input : in std_logic; - delay_value : in std_logic_vector(7 downto 0); - width_value_inhibit : in std_logic_vector(7 downto 0); - width_value_external : in std_logic_vector(7 downto 0); - output_inhibit : out std_logic; - output_external : out std_logic - ); - end component; - component bus_data_com5 - port( - clk_300mhz : in std_logic; - clk_100mhz : in std_logic; - gts_pulse : in std_logic; - cal_trigger : in std_logic; - bus_busy : in std_logic; --not used - bus_ack : in std_logic; - bus_retx : in std_logic; - latch : in std_logic_vector(6 downto 0); - latch_dsc : in std_logic_vector(6 downto 0); - scaler_pti1 : in std_logic_vector(31 downto 0); - scaler_pti2 : in std_logic_vector(31 downto 0); - scaler_pti3 : in std_logic_vector(31 downto 0); - scaler_pti4 : in std_logic_vector(31 downto 0); - scaler_pti5 : in std_logic_vector(31 downto 0); - scaler_ts : in std_logic_vector(31 downto 0); - scaler_vs : in std_logic_vector(31 downto 0); - scaler_dead : in std_logic_vector(31 downto 0); - bus_inhibit : out std_logic; - dtu_inhibit : out std_logic; - ecl_bus_data : out std_logic_vector(1 downto 0); - ecl_bus_clk : out std_logic; - com_run : in std_logic; - dtu_bus_t : out std_logic; - dtu_bus_ts : out std_logic; - dtu_bus_td : out std_logic_vector (3 downto 0); - out_inhibit : in std_logic - ); - end component; - signal pti1_one_clock, pti1_delayed, pti1_ready, pti1_downscaled, pti1_self_coin : std_logic; - signal pti2_one_clock, pti2_delayed, pti2_ready, pti2_downscaled, pti2_self_coin : std_logic; - signal pti3_one_clock, pti3_delayed, pti3_ready, pti3_downscaled, pti3_self_coin : std_logic; - signal pti4_one_clock, pti4_delayed, pti4_ready, pti4_downscaled, pti4_self_coin : std_logic; - signal pti5_one_clock, pti5_delayed, pti5_ready, pti5_downscaled, pti5_self_coin : std_logic; - signal ts_one_clock, ts_delayed, ts_ready, dead, ts_self_coin : std_logic; - signal vs_one_clocks, vs_delayed, vs_ready, vs_width_set, vs_self_coin : std_logic; - signal clock_downscaled, clock_ready : std_logic; - signal cal_inhibit, cal_trigger, out_inhibit, beam_inhibit, bus_inhibit : std_logic; - signal global_timing_signal_out, or_out : std_logic; - signal pti1_and_gts, pti2_and_gts, pti3_and_gts, pti4_and_gts, pti5_and_gts : std_logic; - signal lemin_s, lemin_s1, mux_out : std_logic_vector(1 downto 0); - signal mdc_tof_or, mdc_tof_or_width_set, tof_or, tof_or_delayed, tof_mult_2, tof_mult_2_one, mdc_tof_trigger, mdc_tof_trigger_width_set : std_logic; - signal eco_s, eco_out : std_logic_vector(16 downto 1); - signal tof_one_clock, tof_del, tof_s, tof_s1, mdc_s, mdc_s1 : std_logic_vector(5 downto 0); - signal tof_mux, mdc_mux, pti5_mux, ts_mux, mdc_one_clock : std_logic; - signal scaler_pti1_count, scaler_pti2_count, scaler_pti3_count, scaler_pti4_count, scaler_pti5_count, scaler_ts_count, scaler_vs_count, scaler_dead_count : std_logic_vector(31 downto 0); + +component ONE_CLOCK_LONG port ( + clk : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); +end component; + +component DELAY port ( + clk : in std_logic; + to_be_delayed : in std_logic; + delay_value : in std_logic_vector(3 downto 0); + delayed_pulse : out std_logic); +end component; + +component DOWNSCALE port ( + clk : in std_logic; + disable : in std_logic; + to_be_downscaled : in std_logic; + downscale_value : in std_logic_vector(3 downto 0); + downscaled : out std_logic); +end component; + +component SET_WIDTH port ( + clk : in std_logic; + to_be_set : in std_logic; + width_value : in std_logic_vector(3 downto 0); + width_adjusted_pulse : out std_logic); +end component; + +component SET_WIDTH_special port ( + clk : in std_logic; + to_be_set : in std_logic; + width_value : in std_logic_vector(3 downto 0); + width_adjusted_pulse : out std_logic); +end component; + +component SCALER port ( + clk : in std_logic; + input_pulse : in std_logic; + scaler_reset : in std_logic; + scaler_value : out std_logic_vector(19 downto 0)); +end component; + +component SCALER_S port ( + clk_300MHz : in std_logic; + clk_100MHz : in std_logic; + input_pulse : in std_logic; + scaler_reset : in std_logic; + scaler_value : out std_logic_vector(31 downto 0)); +end component; + +component ECO_DELAY port ( + clk : in std_logic; + signal_in : in std_logic; + signal_out : out std_logic); +end component; + +COMPONENT new_downscale_ck +PORT( + downscale_value : IN std_logic_vector(3 downto 0); + clk : IN std_logic; + downscaled : OUT std_logic; + output_disable : IN std_logic; + global_inhibit : in std_logic; + scaler_reset : OUT std_logic; + cal_inhibit : OUT std_logic; + cal_trigger : OUT std_logic + ); +END COMPONENT; + +COMPONENT beam_ramp +PORT( + clk_300MHz : IN std_logic; + clk_50MHz : IN std_logic; + input : IN std_logic; + delay_value : IN std_logic_vector(7 downto 0); + width_value_inhibit : IN std_logic_vector(7 downto 0); + width_value_external : IN std_logic_vector(7 downto 0); + output_inhibit : OUT std_logic; + output_external : OUT std_logic + ); +END COMPONENT; + +COMPONENT bus_data_com5 +PORT( + clk_300MHz : IN std_logic; + clk_100MHz : IN std_logic; + gts_pulse : IN std_logic; + cal_trigger : IN std_logic; + bus_busy : IN std_logic; --not used + bus_ack : in std_logic; + bus_retx : in std_logic; + latch : IN std_logic_vector(6 downto 0); + latch_dsc : IN std_logic_vector(6 downto 0); + scaler_pti1 : IN std_logic_vector(31 downto 0); + scaler_pti2 : IN std_logic_vector(31 downto 0); + scaler_pti3 : IN std_logic_vector(31 downto 0); + scaler_pti4 : IN std_logic_vector(31 downto 0); + scaler_pti5 : IN std_logic_vector(31 downto 0); + scaler_ts : IN std_logic_vector(31 downto 0); + scaler_vs : IN std_logic_vector(31 downto 0); + scaler_dead : IN std_logic_vector(31 downto 0); + bus_inhibit : OUT std_logic; + dtu_inhibit : out std_logic; + ecl_bus_data : OUT std_logic_vector(1 downto 0); + ecl_bus_clk : OUT std_logic; + com_run : IN std_logic; + dtu_bus_t : out std_logic; + dtu_bus_ts : out std_logic; + dtu_bus_td : out std_logic_vector (3 downto 0); + DTU_CODE_SELECT : in std_logic_vector(4 downto 0); + DEBUG_REG_01 : out std_logic_vector(15 downto 0); + cal_inhibit : in std_logic; + out_inhibit : in std_logic; + TRB_BUSY_ENABLE : in std_logic + ); +END COMPONENT; + + +signal PTI1_ONE_CLOCK, PTI1_DELAYED, PTI1_READY, PTI1_DOWNSCALED, PTI1_SELF_COIN : std_logic; +signal PTI2_ONE_CLOCK, PTI2_DELAYED, PTI2_READY, PTI2_DOWNSCALED, PTI2_SELF_COIN : std_logic; +signal PTI3_ONE_CLOCK, PTI3_DELAYED, PTI3_READY, PTI3_DOWNSCALED, PTI3_SELF_COIN : std_logic; +signal PTI4_ONE_CLOCK, PTI4_DELAYED, PTI4_READY, PTI4_DOWNSCALED, PTI4_SELF_COIN : std_logic; +signal PTI5_ONE_CLOCK, PTI5_DELAYED, PTI5_READY, PTI5_DOWNSCALED, PTI5_SELF_COIN : std_logic; +signal TS_ONE_CLOCK, TS_DELAYED, TS_READY, dead, TS_SELF_COIN : std_logic; +signal VS_ONE_CLOCKS, VS_DELAYED, VS_READY, VS_WIDTH_SET, VS_SELF_COIN : std_logic; +signal CLOCK_DOWNSCALED, CLOCK_READY : std_logic; +signal cal_inhibit, cal_trigger, out_inhibit, beam_inhibit, bus_inhibit : std_logic; +signal GLOBAL_TIMING_SIGNAL_OUT, OR_out : std_logic; +signal PTI1_and_GTS, PTI2_and_GTS, PTI3_and_GTS, PTI4_and_GTS, PTI5_and_GTS : std_logic; +signal lemin_s, lemin_s1, mux_out : std_logic_vector(1 downto 0); +signal mdc_tof_or, mdc_tof_or_width_set, tof_or, tof_or_delayed, tof_mult_2, tof_mult_2_one, mdc_tof_trigger, mdc_tof_trigger_width_set : std_logic; +signal eco_s, eco_out : std_logic_vector(16 downto 1); +signal tof_one_clock, tof_del, tof_s, tof_s1, mdc_s, mdc_s1 : std_logic_vector(5 downto 0); +signal tof_mux, mdc_mux, pti5_mux, ts_mux, mdc_one_clock : std_logic; +signal scaler_pti1_count, scaler_pti2_count, scaler_pti3_count, scaler_pti4_count, scaler_pti5_count, + scaler_ts_count, scaler_vs_count, scaler_dead_count : std_logic_vector(31 downto 0); signal self_coin_delay_1, self_coin_delay_2, self_coin_delay_3, self_coin_delay_4, self_coin_delay_5 : std_logic_vector(3 downto 0); - signal scaler_reset_internal : std_logic; - signal dtu_bus_t, dtu_bus_ts, dtu_bus_tb_s, dtu_inhibit : std_logic; - signal dtu_bus_td : std_logic_vector(3 downto 0); - signal gts_to_databus, cal_to_databus : std_logic; +signal scaler_reset_internal : std_logic; +signal dtu_bus_t, dtu_bus_ts, dtu_bus_tb_s, dtu_inhibit : std_logic; +signal dtu_bus_td : std_logic_vector(3 downto 0); +signal GTS_to_databus, CAL_to_databus : std_logic; + begin --------------------------------------------------------------one clock long - one1 : one_clock_long port map ( - clk => clk_300mhz, - en_clk => input_enable(1), - signal_in => ioo(1), - pulse => pti1_one_clock); - one2 : one_clock_long port map ( - clk => clk_300mhz, - en_clk => input_enable(2), - signal_in => ioo(2), - pulse => pti2_one_clock); - one3 : one_clock_long port map ( - clk => clk_300mhz, - en_clk => input_enable(3), - signal_in => ioo(3), - pulse => pti3_one_clock); - one4 : one_clock_long port map ( --directly connected to the or of tof, so ecl input n°4 is unused - clk => clk_300mhz, - en_clk => input_enable(4), - signal_in => tof_or, - pulse => pti4_one_clock); - one5 : one_clock_long port map ( - clk => clk_300mhz, - en_clk => input_enable(5), - signal_in => ioo(5), - pulse => pti5_one_clock); - one6 : one_clock_long port map ( - clk => clk_300mhz, - en_clk => input_enable(6), - signal_in => ioo(6), - pulse => ts_one_clock); - one7 : one_clock_long port map ( - clk => clk_300mhz, - en_clk => input_enable(7), - signal_in => ioo(7), - pulse => vs_one_clocks); - one_mdc : one_clock_long port map ( --used only for scaler - clk => clk_300mhz, - en_clk => '1', - signal_in => mdc_mux, - pulse => mdc_one_clock); - tof_generate_oneclock : for i in 9 to 14 generate - one_tof : one_clock_long port map ( - clk => clk_300mhz, - en_clk => '1', --tof always enabled - signal_in => ecl(i), - pulse => tof_one_clock(i-9)); - end generate; +-------------------------------------------------------------ONE CLOCK LONG +one1: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => INPUT_ENABLE(1), + signal_in => IOO(1), + pulse => PTI1_ONE_CLOCK); + +one2: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => INPUT_ENABLE(2), + signal_in => IOO(2), + pulse => PTI2_ONE_CLOCK); + +one3: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => INPUT_ENABLE(3), + signal_in => IOO(3), + pulse => PTI3_ONE_CLOCK); + +one4: ONE_CLOCK_LONG port map ( --Directly connected to the OR of TOF, so ECL input n°4 is unused + clk => clk_300MHz, + en_clk => INPUT_ENABLE(4), + signal_in => tof_or, + pulse => PTI4_ONE_CLOCK); + +one5: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => INPUT_ENABLE(5), + signal_in => IOO(5), + pulse => PTI5_ONE_CLOCK); + +one6: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => INPUT_ENABLE(6), + signal_in => IOO(6), + pulse => TS_ONE_CLOCK); + +one7: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => INPUT_ENABLE(7), + signal_in => IOO(7), + pulse => VS_ONE_CLOCKS); + +one_mdc: ONE_CLOCK_LONG port map ( --used only for scaler + clk => clk_300MHz, + en_clk => '1', + signal_in => mdc_mux, + pulse => mdc_one_clock); + +tof_generate_oneclock : for i in 9 to 14 generate + one_tof: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => '1', --tof always enabled + signal_in => ECL(i), + pulse => tof_one_clock(i-9)); +end generate; --------------------------------------------- - multiplicity : one_clock_long port map ( - clk => clk_300mhz, - en_clk => '1', - signal_in => tof_mult_2, - pulse => tof_mult_2_one); +multiplicity: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => '1', + signal_in => tof_mult_2, + pulse => tof_mult_2_one); --------------------------------------------- - one_ck : one_clock_long port map ( - clk => clk_300mhz, - en_clk => '1', - signal_in => clock_downscaled, - pulse => clock_ready); - --------------------------------------------------------------------------delay - del1 : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti1_one_clock, - delay_value => delay_register_1(3 downto 0), - delayed_pulse => pti1_delayed); - - del2 : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti2_one_clock, - delay_value => delay_register_2(3 downto 0), - delayed_pulse => pti2_delayed); - - del3 : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti3_one_clock, - delay_value => delay_register_3(3 downto 0), - delayed_pulse => pti3_delayed); - - del4 : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti4_one_clock, - delay_value => delay_register_4(3 downto 0), - delayed_pulse => pti4_delayed); - - del5 : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti5_mux, - delay_value => delay_register_5(3 downto 0), - delayed_pulse => pti5_delayed); - - del6 : delay port map ( - clk => clk_300mhz, - to_be_delayed => ts_mux, - delay_value => delay_register_ts(3 downto 0), - delayed_pulse => ts_delayed); - - del7 : delay port map ( - clk => clk_300mhz, - to_be_delayed => vs_one_clocks, - delay_value => delay_register_vs(3 downto 0), - delayed_pulse => vs_delayed); - - self_coin_delay_1 <= '0' & width_register_1(3 downto 1); --automatic delay = width / 2 - self_coin_delay_2 <= '0' & width_register_2(3 downto 1); - self_coin_delay_3 <= '0' & width_register_3(3 downto 1); - self_coin_delay_4 <= '0' & width_register_4(3 downto 1); - self_coin_delay_5 <= '0' & width_register_5(3 downto 1); - - del1_self : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti1_downscaled, - delay_value => self_coin_delay_1, - delayed_pulse => pti1_self_coin); - - del2_self : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti2_downscaled, - delay_value => self_coin_delay_2, - delayed_pulse => pti2_self_coin); - - del3_self : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti3_downscaled, - delay_value => self_coin_delay_3, - delayed_pulse => pti3_self_coin); - - del4_self : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti4_downscaled, - delay_value => self_coin_delay_4, - delayed_pulse => pti4_self_coin); - - del5_self : delay port map ( - clk => clk_300mhz, - to_be_delayed => pti5_downscaled, - delay_value => self_coin_delay_5, - delayed_pulse => pti5_self_coin); - - tof_generate_delay : for t in 0 to 5 generate - del_tof : delay port map ( - clk => clk_300mhz, - to_be_delayed => tof_one_clock(t), - delay_value => delay_register_4(3 downto 0), - delayed_pulse => tof_del(t)); - end generate; - --------------------------------------------------------------------------scaler - scal1 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, --pti1÷5 before inhibit - input_pulse => pti1_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti1_count); - - scal2 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => pti2_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti2_count); - - scal3 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => pti3_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti3_count); - - scal4 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => pti4_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti4_count); - - scal5 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => pti5_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti5_count); - - scal1a : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, --pti1÷5 after inhibit - input_pulse => eco_s(9), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti1_accepted); - - scal2a : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => eco_s(10), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti2_accepted); - - scal3a : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => eco_s(11), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti3_accepted); - - scal4a : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => eco_s(12), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti4_accepted); - - scal5a : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => eco_s(13), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_pti5_accepted); - - scalts : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, --ts, vs and dead - input_pulse => ts_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_ts_count); - - scalvs : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => vs_delayed, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_vs_count); - - scaldead : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => dead, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_dead_count); - - scalmdc : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, --mdc and tof - input_pulse => mdc_one_clock, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_mdc); - - scaltof : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => tof_mux, - scaler_reset => scaler_reset_internal, - scaler_value => scaler_tof); - - scalmux1 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => mux_out(0), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_mux1); - - scalmux2 : scaler_s port map ( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - input_pulse => mux_out(1), - scaler_reset => scaler_reset_internal, - scaler_value => scaler_mux2); - ----------------------------------------------------------------------------downscale - dwsc1 : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => pti1_delayed, - downscale_value => downscale_register_1(3 downto 0), - downscaled => pti1_downscaled); - - dwsc2 : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => pti2_delayed, - downscale_value => downscale_register_2(3 downto 0), - downscaled => pti2_downscaled); - - dwsc3 : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => pti3_delayed, - downscale_value => downscale_register_3(3 downto 0), - downscaled => pti3_downscaled); - - dwsc4 : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => pti4_delayed, - downscale_value => downscale_register_4(3 downto 0), - downscaled => pti4_downscaled); - - dwsc5 : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => pti5_delayed, - downscale_value => downscale_register_5(3 downto 0), - downscaled => pti5_downscaled); - - dwscts : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => ts_delayed, - downscale_value => downscale_register_ts(3 downto 0), - downscaled => ts_ready); - - dwscvs : downscale port map ( - clk => clk_300mhz, - disable => out_inhibit, - to_be_downscaled => vs_delayed, - downscale_value => downscale_register_vs(3 downto 0), - downscaled => vs_ready); - --------------------------------------------------------------------------------width - setw1 : set_width port map ( - clk => clk_300mhz, - to_be_set => pti1_downscaled, - width_value => width_register_1(3 downto 0), - width_adjusted_pulse => pti1_ready); - - setw2 : set_width port map ( - clk => clk_300mhz, - to_be_set => pti2_downscaled, - width_value => width_register_2(3 downto 0), - width_adjusted_pulse => pti2_ready); - - setw3 : set_width port map ( - clk => clk_300mhz, - to_be_set => pti3_downscaled, - width_value => width_register_3(3 downto 0), - width_adjusted_pulse => pti3_ready); - - setw4 : set_width port map ( - clk => clk_300mhz, - to_be_set => pti4_downscaled, - width_value => width_register_4(3 downto 0), - width_adjusted_pulse => pti4_ready); - - setw5 : set_width port map ( - clk => clk_300mhz, - to_be_set => pti5_downscaled, - width_value => width_register_5(3 downto 0), - width_adjusted_pulse => pti5_ready); - - setw7 : set_width port map ( - clk => clk_300mhz, - to_be_set => vs_delayed, - width_value => width_register_vs(3 downto 0), - width_adjusted_pulse => vs_width_set); - ---*/*/*///*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --read note 1) - mdc_tof_trigger_width_set <= '1'; --(a) +one_ck: ONE_CLOCK_LONG port map ( + clk => clk_300MHz, + en_clk => '1', + signal_in => CLOCK_DOWNSCALED, + pulse => CLOCK_READY); + +-------------------------------------------------------------------------DELAY +del1: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI1_ONE_CLOCK, + delay_value => DELAY_REGISTER_1(3 downto 0), + delayed_pulse => PTI1_DELAYED); + +del2: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI2_ONE_CLOCK, + delay_value => DELAY_REGISTER_2(3 downto 0), + delayed_pulse => PTI2_DELAYED); + +del3: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI3_ONE_CLOCK, + delay_value => DELAY_REGISTER_3(3 downto 0), + delayed_pulse => PTI3_DELAYED); + +del4: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI4_ONE_CLOCK, + delay_value => DELAY_REGISTER_4(3 downto 0), + delayed_pulse => PTI4_DELAYED); + +del5: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => pti5_mux, + delay_value => DELAY_REGISTER_5(3 downto 0), + delayed_pulse => PTI5_DELAYED); + +del6: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => ts_mux, + delay_value => DELAY_REGISTER_TS(3 downto 0), + delayed_pulse => TS_DELAYED); + +del7: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => VS_ONE_CLOCKS, + delay_value => DELAY_REGISTER_VS(3 downto 0), + delayed_pulse => VS_DELAYED); + +self_coin_delay_1 <= '0' & WIDTH_REGISTER_1(3 downto 1); --automatic delay = width / 2 +self_coin_delay_2 <= '0' & WIDTH_REGISTER_2(3 downto 1); +self_coin_delay_3 <= '0' & WIDTH_REGISTER_3(3 downto 1); +self_coin_delay_4 <= '0' & WIDTH_REGISTER_4(3 downto 1); +self_coin_delay_5 <= '0' & WIDTH_REGISTER_5(3 downto 1); + +del1_self: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI1_DOWNSCALED, + delay_value => self_coin_delay_1, + delayed_pulse => PTI1_SELF_COIN); + +del2_self: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI2_DOWNSCALED, + delay_value => self_coin_delay_2, + delayed_pulse => PTI2_SELF_COIN); + +del3_self: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI3_DOWNSCALED, + delay_value => self_coin_delay_3, + delayed_pulse => PTI3_SELF_COIN); + +del4_self: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI4_DOWNSCALED, + delay_value => self_coin_delay_4, + delayed_pulse => PTI4_SELF_COIN); + +del5_self: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => PTI5_DOWNSCALED, + delay_value => self_coin_delay_5, + delayed_pulse => PTI5_SELF_COIN); + +tof_generate_delay : for t in 0 to 5 generate + del_tof: DELAY port map ( + clk => clk_300MHz, + to_be_delayed => tof_one_clock(t), + delay_value => DELAY_REGISTER_4(3 downto 0), + delayed_pulse => tof_del(t)); +end generate; + +-------------------------------------------------------------------------SCALER +scal1: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, --PTI1÷5 before inhibit + input_pulse => PTI1_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI1_count); + +scal2: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => PTI2_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI2_count); + +scal3: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => PTI3_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI3_count); + +scal4: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => PTI4_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI4_count); + +scal5: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => PTI5_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI5_count); + +scal1a: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, --PTI1÷5 after inhibit + input_pulse => eco_s(9), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI1_ACCEPTED); + +scal2a: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => eco_s(10), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI2_ACCEPTED); + +scal3a: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => eco_s(11), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI3_ACCEPTED); + +scal4a: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => eco_s(12), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI4_ACCEPTED); + +scal5a: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => eco_s(13), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_PTI5_ACCEPTED); + +scalts: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, --TS, VS and dead + input_pulse => TS_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_TS_count); + +scalvs: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => VS_DELAYED, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_VS_count); + +scaldead: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => dead, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_DEAD_count); + +scalmdc: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, --MDC and TOF + input_pulse => mdc_one_clock, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_MDC); + +scaltof: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => tof_mux, + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_TOF); + +scalmux1: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => mux_out(0), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_MUX1); + +scalmux2: SCALER_S port map ( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + input_pulse => mux_out(1), + scaler_reset => scaler_reset_internal, + scaler_value => SCALER_MUX2); + +---------------------------------------------------------------------------DOWNSCALE +dwsc1: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => PTI1_DELAYED, + downscale_value => DOWNSCALE_REGISTER_1(3 downto 0), + downscaled => PTI1_DOWNSCALED); + +dwsc2: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => PTI2_DELAYED, + downscale_value => DOWNSCALE_REGISTER_2(3 downto 0), + downscaled => PTI2_DOWNSCALED); + +dwsc3: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => PTI3_DELAYED, + downscale_value => DOWNSCALE_REGISTER_3(3 downto 0), + downscaled => PTI3_DOWNSCALED); + +dwsc4: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => PTI4_DELAYED, + downscale_value => DOWNSCALE_REGISTER_4(3 downto 0), + downscaled => PTI4_DOWNSCALED); + +dwsc5: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => PTI5_DELAYED, + downscale_value => DOWNSCALE_REGISTER_5(3 downto 0), + downscaled => PTI5_DOWNSCALED); + +dwscts: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => TS_DELAYED, + downscale_value => DOWNSCALE_REGISTER_TS(3 downto 0), + downscaled => TS_READY); + +dwscvs: DOWNSCALE port map ( + clk => clk_300MHz, + disable => out_inhibit, + to_be_downscaled => VS_DELAYED, + downscale_value => DOWNSCALE_REGISTER_VS(3 downto 0), + downscaled => VS_READY); + +-------------------------------------------------------------------------------WIDTH +setw1: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => PTI1_DOWNSCALED, + width_value => WIDTH_REGISTER_1(3 downto 0), + width_adjusted_pulse => PTI1_READY); + +setw2: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => PTI2_DOWNSCALED, + width_value => WIDTH_REGISTER_2(3 downto 0), + width_adjusted_pulse => PTI2_READY); + +setw3: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => PTI3_DOWNSCALED, + width_value => WIDTH_REGISTER_3(3 downto 0), + width_adjusted_pulse => PTI3_READY); + +setw4: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => PTI4_DOWNSCALED, + width_value => WIDTH_REGISTER_4(3 downto 0), + width_adjusted_pulse => PTI4_READY); + +setw5: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => PTI5_DOWNSCALED, + width_value => WIDTH_REGISTER_5(3 downto 0), + width_adjusted_pulse => PTI5_READY); + +setw7: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => VS_DELAYED, + width_value => WIDTH_REGISTER_VS(3 downto 0), + width_adjusted_pulse => VS_WIDTH_SET); + +--*/*/*///*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --READ NOTE 1) +mdc_tof_trigger_width_set <= '1'; --(a) --*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/* - - setw_mdc_tof_trigger : set_width port map ( - clk => clk_300mhz, - to_be_set => mdc_tof_or, - width_value => branch_en_with_mdc_tof_width(3 downto 0), --- width_adjusted_pulse => mdc_tof_trigger_width_set); --(c) - width_adjusted_pulse => open); --(b) - - setwout : set_width_special port map ( - clk => clk_300mhz, - to_be_set => global_timing_signal_out, - width_value => x"6", -- fixed to 20 ns - width_adjusted_pulse => lemou(1)); - -------------------------------------------------------------------------------------------output - delaygen1 : for i in 1 to 7 generate - delay_out : eco_delay port map ( - clk => clk_300mhz, - signal_in => eco_s(i), - signal_out => eco_out(i)); - end generate; - - eco(7 downto 1) <= eco_out(7 downto 1); - - setmux1 : set_width port map ( - clk => clk_300mhz, - to_be_set => mux_out(0), - width_value => "0010", - width_adjusted_pulse => eco(8)); - - delaygen2 : for i in 9 to 15 generate - delay_out : eco_delay port map ( - clk => clk_300mhz, - signal_in => eco_s(i), - signal_out => eco_out(i)); - end generate; - - eco(15 downto 9) <= eco_out(15 downto 9); - - setmux2 : set_width port map ( - clk => clk_300mhz, - to_be_set => mux_out(1), - width_value => "0010", - width_adjusted_pulse => eco(16)); - - inst_new_downscale_ck : new_downscale_ck port map( - downscale_value => downscale_register_clock(3 downto 0), - clk => clk_300mhz, - output_disable => cal_trigger_disable, - scaler_reset => scaler_reset_internal, - downscaled => clock_downscaled, - cal_inhibit => cal_inhibit, - cal_trigger => cal_trigger); - - - lemou(2) <= '0'; --now calib pulse is coming out from lemo n°1, this output is unused - - inst_beam_ramp : beam_ramp port map( - clk_300mhz => clk_300mhz, - clk_50mhz => clk_50mhz, - input => lemin_s(1), - output_inhibit => beam_inhibit, - output_external => tin(12), - delay_value => delay_register_beam, - width_value_inhibit => width_inhibit_register_beam, - width_value_external => width_external_register_beam); + +setw_mdc_tof_trigger: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => mdc_tof_or, + width_value => BRANCH_EN_with_MDC_TOF_WIDTH(3 downto 0), +-- width_adjusted_pulse => mdc_tof_trigger_width_set); --(c) + width_adjusted_pulse => open); --(b) + +setwout: SET_WIDTH_special port map ( + clk => clk_300MHz, + to_be_set => GLOBAL_TIMING_SIGNAL_OUT, + width_value => x"6", -- fixed to 20 ns + width_adjusted_pulse => LEMOU(1)); + +------------------------------------------------------------------------------------------OUTPUT +delaygen1 : for i in 1 to 7 generate + delay_out : ECO_DELAY port map ( + clk => clk_300MHz, + signal_in => eco_s(i), + signal_out => eco_out(i)); +end generate; + +ECO(7 downto 1) <= eco_out(7 downto 1); + +setmux1: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => mux_out(0), + width_value => "0010", + width_adjusted_pulse => ECO(8)); + +delaygen2 : for i in 9 to 15 generate + delay_out : ECO_DELAY port map ( + clk => clk_300MHz, + signal_in => eco_s(i), + signal_out => eco_out(i)); +end generate; + +ECO(15 downto 9) <= eco_out(15 downto 9); + +setmux2: SET_WIDTH port map ( + clk => clk_300MHz, + to_be_set => mux_out(1), + width_value => "0010", + width_adjusted_pulse => ECO(16)); + +Inst_new_downscale_ck: new_downscale_ck PORT MAP( + downscale_value => DOWNSCALE_REGISTER_CLOCK(3 downto 0), + clk => clk_300MHz, + output_disable => CAL_TRIGGER_DISABLE, + scaler_reset => scaler_reset_internal, + downscaled => CLOCK_DOWNSCALED, + global_inhibit => out_inhibit, + cal_inhibit => cal_inhibit, + cal_trigger => cal_trigger); + + +LEMOU(2) <= out_inhibit;--OR_out;-- GLOBAL_TIMING_SIGNAL_OUT; --Now calib pulse is coming out from lemo n°1, this output is unused + +Inst_beam_ramp: beam_ramp PORT MAP( + clk_300MHz => clk_300MHz, + clk_50MHz => clk_50MHz, + input => lemin_s(1), + output_inhibit => beam_inhibit, + output_external => TIN(12), + delay_value => DELAY_REGISTER_BEAM, + width_value_inhibit => WIDTH_INHIBIT_REGISTER_BEAM, + width_value_external => WIDTH_EXTERNAL_REGISTER_BEAM); + +--------------BUS COMMUNICATION + +Inst_bus_data_com5: bus_data_com5 PORT MAP( + clk_300MHz => clk_300MHz, + clk_100MHz => clk_100MHz, + gts_pulse => GTS_to_databus, + cal_trigger => cal_trigger, + bus_busy => IOO(16), --not used + bus_ack => IOO(15), + bus_retx => IOO(14), + latch => eco_out(7 downto 1), + latch_dsc => eco_out(15 downto 9), + scaler_pti1 => scaler_pti1_count, + scaler_pti2 => scaler_pti2_count, + scaler_pti3 => scaler_pti3_count, + scaler_pti4 => scaler_pti4_count, + scaler_pti5 => scaler_pti5_count, + scaler_ts => scaler_ts_count, + scaler_vs => scaler_vs_count, + scaler_dead => scaler_dead_count, + bus_inhibit => bus_inhibit, + dtu_inhibit => dtu_inhibit, + ecl_bus_data => TIN(11 downto 10), + ecl_bus_clk => open,--TIN(9), + com_run => com_run, + dtu_bus_t => dtu_bus_t, + dtu_bus_ts => dtu_bus_ts, + dtu_bus_td => dtu_bus_td, + DTU_CODE_SELECT => DTU_CODE_SELECT, + DEBUG_REG_01 => DEBUG_REG_00(15 downto 0), + cal_inhibit => cal_inhibit, + out_inhibit => out_inhibit, + TRB_BUSY_ENABLE => TRB_BUSY_ENABLE + ); + + --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ + hpv(14) <= not dtu_bus_t; --This is a "firmware patch": the VME connector + hpw(14) <= not dtu_bus_ts; --for DTU is reversed (mistake in pcb layout) so + hpw(10) <= not dtu_bus_td(3); --all the I/Os must be inverted + hpv(10) <= not dtu_bus_td(2); + hpw(12) <= not dtu_bus_td(1); + hpv(12) <= not dtu_bus_td(0); + hpw(8) <= 'Z'; + ---------------------- + hpv(15) <= dtu_bus_ts; --With this connections all the DTU signals are + hpv(11) <= dtu_bus_td(3); --on one debug socket (hplv or hplw) that can conveniently + hpv(13) <= dtu_bus_td(1); --plugged to a logic analyzer. Be aware though, some signals + hpv(9) <= '0'; --are inverted + hpv(7 downto 0) <= x"00"; --unused + + hpw(15) <= dtu_bus_t; + hpw(11) <= dtu_bus_td(2); + hpw(13) <= dtu_bus_td(0); + hpw(9) <= '0'; + hpw(7 downto 0) <= x"00"; --unused + --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ + + SCALER_PTI1 <= SCALER_PTI1_count; + SCALER_PTI2 <= SCALER_PTI2_count; + SCALER_PTI3 <= SCALER_PTI3_count; + SCALER_PTI4 <= SCALER_PTI4_count; + SCALER_PTI5 <= SCALER_PTI5_count; + SCALER_TS <= SCALER_TS_count; + SCALER_VS <= SCALER_VS_count; + SCALER_dead <= SCALER_dead_count; + +TIN(16 downto 13) <= "0000"; + +--------------PTI5 & TS mux + +mdc_tof_mux: process(clk_300MHz) +begin + if rising_edge(clk_300MHz) then + +-- case tof_one_clock is --multiplicity 2 detector + case ecl(14 downto 9) is --multiplicity 2 detector + when "000011" => tof_mult_2 <= '1'; + when "000101" => tof_mult_2 <= '1'; + when "001001" => tof_mult_2 <= '1'; + when "010001" => tof_mult_2 <= '1'; + when "100001" => tof_mult_2 <= '1'; + when "000110" => tof_mult_2 <= '1'; + when "001010" => tof_mult_2 <= '1'; + when "010010" => tof_mult_2 <= '1'; + when "100010" => tof_mult_2 <= '1'; + when "001100" => tof_mult_2 <= '1'; + when "010100" => tof_mult_2 <= '1'; + when "100100" => tof_mult_2 <= '1'; + when "011000" => tof_mult_2 <= '1'; + when "101000" => tof_mult_2 <= '1'; + when "110000" => tof_mult_2 <= '1'; + when others => tof_mult_2 <= '0'; + end case; + + case PTI5_TS_ALTERNATIVE(4) is + when '0' => pti5_mux <= PTI5_ONE_CLOCK; + when '1' => pti5_mux <= tof_mult_2_one; + when others => pti5_mux <= 'X'; + end case; + + case PTI5_TS_ALTERNATIVE(0) is + when '0' => ts_mux <= TS_ONE_CLOCK; + when '1' => ts_mux <= tof_or; + when others => ts_mux <= 'X'; + end case; + end if; +end process mdc_tof_mux; + +--------------MDC & TOF scaler mux + +pti5_ts_mux: process(clk_300MHz) +begin + if rising_edge(clk_300MHz) then + case SCALER_MDC_TOF_SELECT(7 downto 4) is + when x"0" => mdc_mux <= mdc_s1(0); + when x"1" => mdc_mux <= mdc_s1(1); + when x"2" => mdc_mux <= mdc_s1(2); + when x"3" => mdc_mux <= mdc_s1(3); + when x"4" => mdc_mux <= mdc_s1(4); + when x"5" => mdc_mux <= mdc_s1(5); + when others => mdc_mux <= '0'; + end case; + + case SCALER_MDC_TOF_SELECT(3 downto 0) is + when x"0" => tof_mux <= tof_one_clock(0); + when x"1" => tof_mux <= tof_one_clock(1); + when x"2" => tof_mux <= tof_one_clock(2); + when x"3" => tof_mux <= tof_one_clock(3); + when x"4" => tof_mux <= tof_one_clock(4); + when x"5" => tof_mux <= tof_one_clock(5); + when others => tof_mux <= '0'; + end case; + end if; +end process pti5_ts_mux; + +-------------- TOF & MDC logic + +tof_mdc_logic: process(clk_300Mhz) +begin + if rising_edge(clk_300MHz) then + + mdc_s <= ECL(6 downto 1); + tof_s <= ECL(14 downto 9); + mdc_s1 <= mdc_s; + tof_s1 <= tof_s; ---------------bus communication - - inst_bus_data_com5 : bus_data_com5 port map( - clk_300mhz => clk_300mhz, - clk_100mhz => clk_100mhz, - gts_pulse => gts_to_databus, - cal_trigger => cal_trigger, - bus_busy => ioo(16), --not used - bus_ack => ioo(15), - bus_retx => ioo(14), - latch => eco_out(7 downto 1), - latch_dsc => eco_out(15 downto 9), - scaler_pti1 => scaler_pti1_count, - scaler_pti2 => scaler_pti2_count, - scaler_pti3 => scaler_pti3_count, - scaler_pti4 => scaler_pti4_count, - scaler_pti5 => scaler_pti5_count, - scaler_ts => scaler_ts_count, - scaler_vs => scaler_vs_count, - scaler_dead => scaler_dead_count, - bus_inhibit => bus_inhibit, - dtu_inhibit => dtu_inhibit, - ecl_bus_data => tin(11 downto 10), - ecl_bus_clk => tin(9), - com_run => com_run, - dtu_bus_t => dtu_bus_t, - dtu_bus_ts => dtu_bus_ts, - dtu_bus_td => dtu_bus_td, - out_inhibit => out_inhibit - ); - - --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ - hpv(14) <= not dtu_bus_t; --this is a "firmware patch": the vme connector - hpw(14) <= not dtu_bus_ts; --for dtu is reversed (mistake in pcb layout) so - hpw(10) <= not dtu_bus_td(3); --all the i/os must be inverted - hpv(10) <= not dtu_bus_td(2); - hpw(12) <= not dtu_bus_td(1); - hpv(12) <= not dtu_bus_td(0); - hpw(8) <= 'Z'; - ---------------------- - hpv(15) <= dtu_bus_ts; --with this connections all the dtu signals are - hpv(11) <= dtu_bus_td(3); --on one debug socket (hplv or hplw) that can conveniently - hpv(13) <= dtu_bus_td(1); --plugged to a logic analyzer. be aware though, some signals - hpv(9) <= '0'; --are inverted - hpv(7 downto 0) <= x"00"; --unused - - hpw(15) <= dtu_bus_t; - hpw(11) <= dtu_bus_td(2); - hpw(13) <= dtu_bus_td(0); - hpw(9) <= '0'; - hpw(7 downto 0) <= x"00"; --unused - --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ - - scaler_pti1 <= scaler_pti1_count; - scaler_pti2 <= scaler_pti2_count; - scaler_pti3 <= scaler_pti3_count; - scaler_pti4 <= scaler_pti4_count; - scaler_pti5 <= scaler_pti5_count; - scaler_ts <= scaler_ts_count; - scaler_vs <= scaler_vs_count; - scaler_dead <= scaler_dead_count; - - tin(16 downto 13) <= "0000"; - ---------------pti5 & ts mux - - mdc_tof_mux : process(clk_300mhz) - begin - if rising_edge(clk_300mhz) then - --- case tof_one_clock is --multiplicity 2 detector - case ecl(14 downto 9) is --multiplicity 2 detector - when "000011" => tof_mult_2 <= '1'; - when "000101" => tof_mult_2 <= '1'; - when "001001" => tof_mult_2 <= '1'; - when "010001" => tof_mult_2 <= '1'; - when "100001" => tof_mult_2 <= '1'; - when "000110" => tof_mult_2 <= '1'; - when "001010" => tof_mult_2 <= '1'; - when "010010" => tof_mult_2 <= '1'; - when "100010" => tof_mult_2 <= '1'; - when "001100" => tof_mult_2 <= '1'; - when "010100" => tof_mult_2 <= '1'; - when "100100" => tof_mult_2 <= '1'; - when "011000" => tof_mult_2 <= '1'; - when "101000" => tof_mult_2 <= '1'; - when "110000" => tof_mult_2 <= '1'; - when others => tof_mult_2 <= '0'; - end case; - - case pti5_ts_alternative(4) is - when '0' => pti5_mux <= pti5_one_clock; - when '1' => pti5_mux <= tof_mult_2_one; - when others => pti5_mux <= 'X'; - end case; - - case pti5_ts_alternative(0) is - when '0' => ts_mux <= ts_one_clock; - when '1' => ts_mux <= tof_or; - when others => ts_mux <= 'X'; - end case; - end if; - end process mdc_tof_mux; - ---------------mdc & tof scaler mux - - pti5_ts_mux : process(clk_300mhz) - begin - if rising_edge(clk_300mhz) then - case scaler_mdc_tof_select(7 downto 4) is - when x"0" => mdc_mux <= mdc_s1(0); - when x"1" => mdc_mux <= mdc_s1(1); - when x"2" => mdc_mux <= mdc_s1(2); - when x"3" => mdc_mux <= mdc_s1(3); - when x"4" => mdc_mux <= mdc_s1(4); - when x"5" => mdc_mux <= mdc_s1(5); - when others => mdc_mux <= '0'; - end case; - - case scaler_mdc_tof_select(3 downto 0) is - when x"0" => tof_mux <= tof_one_clock(0); - when x"1" => tof_mux <= tof_one_clock(1); - when x"2" => tof_mux <= tof_one_clock(2); - when x"3" => tof_mux <= tof_one_clock(3); - when x"4" => tof_mux <= tof_one_clock(4); - when x"5" => tof_mux <= tof_one_clock(5); - when others => tof_mux <= '0'; - end case; - end if; - end process pti5_ts_mux; - --------------- tof & mdc logic - - tof_mdc_logic : process(clk_300mhz) - begin - if rising_edge(clk_300mhz) then - - mdc_s <= ecl(6 downto 1); - tof_s <= ecl(14 downto 9); - mdc_s1 <= mdc_s; - tof_s1 <= tof_s; - - mdc_tof_or <= (((tof_del(0) and not mdc_s1(0)) or (tof_del(1) and not mdc_s1(1)) or - (tof_del(2) and not mdc_s1(2)) or (tof_del(3) and not mdc_s1(3)) or - (tof_del(4) and not mdc_s1(4)) or (tof_del(5) and not mdc_s1(5))) - and branch_en_with_mdc_tof_width(4)); - tof_or <= (ecl(9) or ecl(10) or ecl(11) or ecl(12) or ecl(13) or ecl(14)); - end if; - end process tof_mdc_logic; --------------- final and-or logic function - logic : process(clk_300mhz) - begin - if rising_edge(clk_300mhz) then - - -------------------------------------- gate select single - - pti1_and_gts <= ((pti1_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(1)) - or (pti1_self_coin and ts_gating_disable(1))); - pti2_and_gts <= ((pti2_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(2)) - or (pti2_self_coin and ts_gating_disable(2))); - pti3_and_gts <= ((pti3_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(3)) - or (pti3_self_coin and ts_gating_disable(3))); - pti4_and_gts <= ((pti4_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(4)) - or (pti4_self_coin and ts_gating_disable(4))); - pti5_and_gts <= ((pti5_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(5)) - or (pti5_self_coin and ts_gating_disable(5))); - or_out <= (pti1_and_gts and or_on_off(0)) or - (pti2_and_gts and or_on_off(1)) or - (pti3_and_gts and or_on_off(2)) or - (pti4_and_gts and or_on_off(3)) or - (pti5_and_gts and or_on_off(4)) or - (ts_ready and or_on_off(5)) or - (vs_ready and or_on_off(6)) or - (clock_ready and or_on_off(7)); - lemin_s <= lemin; - lemin_s1 <= lemin_s; - dtu_bus_tb_s <= not hpv(8); --dtu trigger busy - dead <= ts_delayed and (not out_inhibit); - out_inhibit <= lemin_s1(0) or beam_inhibit or bus_inhibit or dtu_inhibit or dtu_bus_tb_s; - global_timing_signal_out <= (cal_trigger and not out_inhibit) or (or_out and not out_inhibit and not cal_inhibit); - gts_to_databus <= or_out and not out_inhibit and not cal_inhibit; - end if; - end process logic; ----------------- outputs - - assign : process(clk_300mhz) - begin - if rising_edge(clk_300mhz) then - eco_s(1) <= pti1_delayed; -- latches before downscale - eco_s(2) <= pti2_delayed; - eco_s(3) <= pti3_delayed; - eco_s(4) <= pti4_delayed; - eco_s(5) <= pti5_delayed; - eco_s(6) <= ts_delayed; - eco_s(7) <= vs_delayed; --- eco(8) is mux 0 - eco_s(9) <= (or_on_off(0) and ((pti1_downscaled and ts_gating_disable(1)) - or (pti1_and_gts and not ts_gating_disable(1)))); - eco_s(10) <= (or_on_off(1) and ((pti2_downscaled and ts_gating_disable(2)) - or (pti2_and_gts and not ts_gating_disable(2)))); - eco_s(11) <= (or_on_off(2) and ((pti3_downscaled and ts_gating_disable(3)) - or (pti3_and_gts and not ts_gating_disable(3)))); - eco_s(12) <= (or_on_off(3) and ((pti4_downscaled and ts_gating_disable(4)) - or (pti4_and_gts and not ts_gating_disable(4)))); - eco_s(13) <= (or_on_off(4) and ((pti5_downscaled and ts_gating_disable(5)) - or (pti5_and_gts and not ts_gating_disable(5)))); - eco_s(14) <= ts_ready and or_on_off(5); - eco_s(15) <= vs_ready and or_on_off(6); --- eco(16) is mux 1 - ------------------ multiplexers - case mux_selector_1 is --0x5c - when "0000" => mux_out(0) <= pti1_delayed; --0 - when "0001" => mux_out(0) <= pti2_delayed; - when "0010" => mux_out(0) <= pti3_delayed; --2 - when "0011" => mux_out(0) <= pti4_delayed; - when "0100" => mux_out(0) <= pti5_delayed; --4 - when "0101" => mux_out(0) <= ts_delayed; - when "0110" => mux_out(0) <= vs_delayed; --6 - when "0111" => mux_out(0) <= pti1_and_gts; - when "1000" => mux_out(0) <= pti2_and_gts; --8 - when "1001" => mux_out(0) <= pti3_and_gts; - when "1010" => mux_out(0) <= pti4_and_gts; --a - when "1011" => mux_out(0) <= pti5_and_gts; - when "1100" => mux_out(0) <= ts_ready; --c - when "1101" => mux_out(0) <= vs_ready; - when "1110" => mux_out(0) <= or_out; --e - when "1111" => mux_out(0) <= global_timing_signal_out; - when others => mux_out(0) <= 'X'; - end case; - case mux_selector_2 is --0x60 - when "0000" => mux_out(1) <= pti1_delayed; --0 - when "0001" => mux_out(1) <= pti2_delayed; - when "0010" => mux_out(1) <= pti3_delayed; --2 - when "0011" => mux_out(1) <= pti4_delayed; - when "0100" => mux_out(1) <= pti5_delayed; --4 - when "0101" => mux_out(1) <= ts_delayed; - when "0110" => mux_out(1) <= vs_delayed; --6 - when "0111" => mux_out(1) <=tof_mux; --pti1_ready; - when "1000" => mux_out(1) <='0'; --pti2_ready; --8 - when "1001" => mux_out(1) <='0'; --pti3_ready; - when "1010" => mux_out(1) <='0'; --pti4_ready; --a - when "1011" => mux_out(1) <=mdc_tof_trigger_width_set;--pti5_ready; - when "1100" => mux_out(1) <= ts_ready; --c - when "1101" => mux_out(1) <= vs_ready; - when "1110" => mux_out(1) <= clock_ready; --e - when "1111" => mux_out(1) <=mdc_mux; --vs_width_set; - when others => mux_out(1) <= 'X'; - end case; - end if; - end process assign; -end rtl; + mdc_tof_or <= (((tof_del(0) and not mdc_s1(0)) or (tof_del(1) and not mdc_s1(1)) or + (tof_del(2) and not mdc_s1(2)) or (tof_del(3) and not mdc_s1(3)) or + (tof_del(4) and not mdc_s1(4)) or (tof_del(5) and not mdc_s1(5))) + and BRANCH_EN_with_MDC_TOF_WIDTH(4)); + + tof_or <= (ecl(9) or ecl(10) or ecl(11) or ecl(12) or ecl(13) or ecl(14)); + + end if; +end process tof_mdc_logic; + +-------------- Final AND-OR logic function + +logic: process(clk_300MHz) +begin + if rising_edge(clk_300MHz) then + + -------------------------------------- GATE SELECT SINGLE + + PTI1_and_GTS <= ((PTI1_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(1)) + or (PTI1_SELF_COIN and TS_GATING_DISABLE(1))); + PTI2_and_GTS <= ((PTI2_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(2)) + or (PTI2_SELF_COIN and TS_GATING_DISABLE(2))); + PTI3_and_GTS <= ((PTI3_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(3)) + or (PTI3_SELF_COIN and TS_GATING_DISABLE(3))); + PTI4_and_GTS <= ((PTI4_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(4)) + or (PTI4_SELF_COIN and TS_GATING_DISABLE(4))); + PTI5_and_GTS <= ((PTI5_READY and (TS_DELAYED and not VS_WIDTH_SET) and mdc_tof_trigger_width_set and not TS_GATING_DISABLE(5)) + or (PTI5_SELF_COIN and TS_GATING_DISABLE(5))); + + OR_out <= (PTI1_and_GTS and OR_ON_OFF(0)) or + (PTI2_and_GTS and OR_ON_OFF(1)) or + (PTI3_and_GTS and OR_ON_OFF(2)) or + (PTI4_and_GTS and OR_ON_OFF(3)) or + (PTI5_and_GTS and OR_ON_OFF(4)) or + (TS_READY and OR_ON_OFF(5)) or + (VS_READY and OR_ON_OFF(6)) or + (CLOCK_READY and OR_ON_OFF(7)); + + lemin_s <= LEMIN; + lemin_s1 <= lemin_s; + dtu_bus_tb_s <= not hpv(8); --dtu trigger busy + + dead <= TS_DELAYED and (not out_inhibit); + + out_inhibit <= lemin_s1(0) or beam_inhibit or bus_inhibit or dtu_inhibit;-- + --or dtu_bus_tb_s;-- + --or (not com_run); + TIN(9) <= cal_trigger; + GLOBAL_TIMING_SIGNAL_OUT <= (OR_out and (not out_inhibit) and (not cal_inhibit)); +-- and not out_inhibit) or (OR_out and (not out_inhibit) and (not cal_inhibit)); + GTS_to_databus <= OR_out and not out_inhibit and not cal_inhibit; + + + end if; +end process logic; +DEBUG_REG_00(31 downto 29) <= OR_out & out_inhibit & cal_inhibit; +DEBUG_REG_00(28 downto 24) <= lemin_s1(0) & beam_inhibit & bus_inhibit & dtu_inhibit & dtu_bus_tb_s; +---------------- Outputs + +assign: process(clk_300MHz) +begin + if rising_edge(clk_300MHz) then + + eco_s(1) <= PTI1_DELAYED; -- Latches before downscale + eco_s(2) <= PTI2_DELAYED; + eco_s(3) <= PTI3_DELAYED; + eco_s(4) <= PTI4_DELAYED; + eco_s(5) <= PTI5_DELAYED; + eco_s(6) <= TS_DELAYED; + eco_s(7) <= VS_DELAYED; +-- ECO(8) is mux 0 + eco_s(9) <= (OR_ON_OFF(0) and ((PTI1_DOWNSCALED and TS_GATING_DISABLE(1)) + or (PTI1_and_GTS and not TS_GATING_DISABLE(1)))); + eco_s(10) <= (OR_ON_OFF(1) and ((PTI2_DOWNSCALED and TS_GATING_DISABLE(2)) + or (PTI2_and_GTS and not TS_GATING_DISABLE(2)))); + eco_s(11) <= (OR_ON_OFF(2) and ((PTI3_DOWNSCALED and TS_GATING_DISABLE(3)) + or (PTI3_and_GTS and not TS_GATING_DISABLE(3)))); + eco_s(12) <= (OR_ON_OFF(3) and ((PTI4_DOWNSCALED and TS_GATING_DISABLE(4)) + or (PTI4_and_GTS and not TS_GATING_DISABLE(4)))); + eco_s(13) <= (OR_ON_OFF(4) and ((PTI5_DOWNSCALED and TS_GATING_DISABLE(5)) + or (PTI5_and_GTS and not TS_GATING_DISABLE(5)))); + + eco_s(14) <= TS_READY and OR_ON_OFF(5); + eco_s(15) <= VS_READY and OR_ON_OFF(6); +-- ECO(16) is mux 1 + +----------------- Multiplexers + + case MUX_SELECTOR_1 is --0x5c + + when "0000" => mux_out(0) <= PTI1_DELAYED; --0 + when "0001" => mux_out(0) <= PTI2_DELAYED; + when "0010" => mux_out(0) <= PTI3_DELAYED; --2 + when "0011" => mux_out(0) <= PTI4_DELAYED; + when "0100" => mux_out(0) <= PTI5_DELAYED; --4 + when "0101" => mux_out(0) <= TS_DELAYED; + when "0110" => mux_out(0) <= VS_DELAYED; --6 + when "0111" => mux_out(0) <= PTI1_and_GTS; + when "1000" => mux_out(0) <= PTI2_and_GTS; --8 + when "1001" => mux_out(0) <= PTI3_and_GTS; + when "1010" => mux_out(0) <= PTI4_and_GTS; --a + when "1011" => mux_out(0) <= PTI5_and_GTS; + when "1100" => mux_out(0) <= TS_READY; --c + when "1101" => mux_out(0) <= VS_READY; + when "1110" => mux_out(0) <= OR_out; --e + when "1111" => mux_out(0) <= GLOBAL_TIMING_SIGNAL_OUT; + when others => mux_out(0) <= 'X'; + + end case; + + + case MUX_SELECTOR_2 is --0x60 + + when "0000" => mux_out(1) <= PTI1_DELAYED; --0 + when "0001" => mux_out(1) <= PTI2_DELAYED; + when "0010" => mux_out(1) <= PTI3_DELAYED; --2 + when "0011" => mux_out(1) <= PTI4_DELAYED; + when "0100" => mux_out(1) <= PTI5_DELAYED; --4 + when "0101" => mux_out(1) <= TS_DELAYED; + when "0110" => mux_out(1) <= VS_DELAYED; --6 + when "0111" => mux_out(1) <=tof_mux; --PTI1_READY; + when "1000" => mux_out(1) <='0'; --PTI2_READY; --8 + when "1001" => mux_out(1) <='0'; --PTI3_READY; + when "1010" => mux_out(1) <='0'; --PTI4_READY; --a + when "1011" => mux_out(1) <=mdc_tof_trigger_width_set;--PTI5_READY; + when "1100" => mux_out(1) <= TS_READY; --c + when "1101" => mux_out(1) <= VS_READY; + when "1110" => mux_out(1) <= CLOCK_READY; --e + when "1111" => mux_out(1) <=mdc_mux; --VS_WIDTH_SET; + when others => mux_out(1) <= 'X'; + + end case; + + end if; +end process assign; + +end RTL; diff --git a/oldfiles/vulom3/ulogic.vhd b/oldfiles/vulom3/ulogic.vhd index 0162ad7..cfb8306 100644 --- a/oldfiles/vulom3/ulogic.vhd +++ b/oldfiles/vulom3/ulogic.vhd @@ -52,9 +52,11 @@ signal or_on_off : std_logic_vector(7 downto 0); signal ts_gating_disable : std_logic_vector(7 downto 1); signal pti5_ts_alternative, delay_register_beam, width_inhibit_register_beam, width_external_register_beam : std_logic_vector(7 downto 0); signal mux_selector_1, mux_selector_2 : std_logic_vector(3 downto 0); -signal branch_en_with_mdc_tof_width : std_logic_vector(4 downto 0); +signal branch_en_with_mdc_tof_width, dtu_code_select_i: std_logic_vector(4 downto 0); --signal u_data_o_s : std_logic_vector(31 downto 0); signal cal_trigger_disable, com_run, dtu_error : std_logic; +signal debug_1 : std_logic_vector(31 downto 0); +signal trb_busy_enable : std_logic; component trig_box1 port (CLK_50MHZ : in std_logic; CLK_300MHz : in std_logic; @@ -119,11 +121,14 @@ component trig_box1 SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); SCALER_MUX1 : out std_logic_vector(31 downto 0); SCALER_MUX2 : out std_logic_vector(31 downto 0); + DTU_CODE_SELECT : in std_logic_vector(4 downto 0); CAL_TRIGGER_DISABLE : in std_logic; COM_RUN : in std_logic; DTU_ERROR : out std_logic; HPV : inout std_logic_vector(15 downto 0); - HPW : inout std_logic_vector(15 downto 0) + HPW : inout std_logic_vector(15 downto 0); + DEBUG_REG_00 : out std_logic_vector(31 downto 0); + TRB_BUSY_ENABLE : in std_logic ); end component; begin @@ -191,11 +196,14 @@ begin SCALER_VS_ACCEPTED => scaler_vs_accepted, SCALER_MUX1 => scaler_mux1, SCALER_MUX2 => scaler_mux2, + DTU_CODE_SELECT => dtu_code_select_i, CAL_TRIGGER_DISABLE => cal_trigger_disable, COM_RUN => com_run, DTU_ERROR => dtu_error, HPV => HPV, - HPW => HPW + HPW => HPW, + DEBUG_REG_00 => debug_1, + TRB_BUSY_ENABLE => trb_busy_enable ); ---------------------I/O ecl port settings and led configuration --------------------------------- -- tin(16 downto 9) <= (others => '0'); @@ -251,6 +259,8 @@ begin -- scalers must not be written by command when x"0037" => cal_trigger_disable <= U_DAT_IN(0); when x"0038" => dtu_error <= U_DAT_IN(0); + when x"0039" => dtu_code_select_i <= U_DAT_IN(4 downto 0); + when x"0041" => trb_busy_enable <= U_DAT_IN(0); when others => null; end case; elsif OECSR = '1' then --write to VME bus @@ -312,6 +322,9 @@ begin when x"0036" => U_DATA_O <= scaler_mux2; when x"0037" => U_DATA_O <= x"0000000" & "000" & cal_trigger_disable; when x"0038" => U_DATA_O <= x"0000000" & "000" & dtu_error; + when x"0039" => U_DATA_O <= x"000000" & "000" & dtu_code_select_i; + when x"0040" => U_DATA_O <= debug_1; + when x"0041" => U_DATA_O <= x"0000000" & "000" & trb_busy_enable; when others => null; end case; end if; diff --git a/oldfiles/vulom3/vlogic_1.vhd b/oldfiles/vulom3/vlogic_1.vhd index 7cb8e81..c21450d 100644 --- a/oldfiles/vulom3/vlogic_1.vhd +++ b/oldfiles/vulom3/vlogic_1.vhd @@ -143,7 +143,18 @@ signal hplb : std_logic_vector (15 downto 0); -- signal prova, to_LED6, SOFT_RESET : std_logic; ---------------------------- signal rst, clk2x, clk0, ck50, ck300, ck100, locked : std_logic; -- internal acknowledge -begin +------------------------------------------------------------------------------- +signal clk : std_logic; +begin + -- CLK ---------------------------------------------------------------------- +-- IBUFGDS_CLK : IBUFGDS +-- generic map ( +-- IOSTANDARD => "LVDS_25_DCI") +-- port map ( +-- O => clk,--CLK, +-- I => CKFPL, +-- IB => CKFNL -- Diff_n clock buffer input (connect to top-level port) +-- ); Inst_clocking : clocking port map( CLKIN_IN => CKFPL, CLKDV_OUT => ck50, --50MHz clock @@ -214,7 +225,7 @@ begin DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 33h "3" ascii else AI <= "10"; - DI <= CONV_STD_LOGIC_VECTOR(50, 7); -- 32h "2" ascii + DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 32h "2" ascii end if; end if; end process; -- 2.43.0