From 5b34f99dbf4776c8b8227db0550f365d408c0a40 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 31 Jan 2018 11:53:37 +0100 Subject: [PATCH] update sync media interface and longer network reset --- media_interfaces/med_ecp3_sfp_sync_4.vhd | 10 ++++++---- media_interfaces/sync/med_sync_control.vhd | 4 +++- media_interfaces/sync/med_sync_define.vhd | 1 + media_interfaces/sync/rx_control.vhd | 17 ++++++++--------- media_interfaces/sync/tx_control.vhd | 5 ++++- trb_net16_hub_streaming_port_sctrl_record.vhd | 6 +++--- 6 files changed, 25 insertions(+), 18 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 9501288..17745db 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -66,6 +66,7 @@ signal clk_tx_full, clk_tx_half : std_logic_vector(3 downto 0); signal tx_data : std_logic_vector(4*8-1 downto 0); signal tx_k : std_logic_vector(3 downto 0); +signal tx_cd : std_logic_vector(3 downto 0); signal rx_data : std_logic_vector(4*8-1 downto 0); signal rx_k : std_logic_vector(3 downto 0); signal rx_error : std_logic_vector(3 downto 0); @@ -125,7 +126,7 @@ SD_TXDIS_OUT <= (others => RESET); fpga_rxrefclk_ch0 => CLK_INTERNAL_FULL, txdata_ch0 => tx_data(0*8+7 downto 0*8), tx_k_ch0 => tx_k(0), - tx_force_disp_ch0 => '0', + tx_force_disp_ch0 => tx_cd(0), tx_disp_sel_ch0 => '0', rxdata_ch0 => rx_data(0*8+7 downto 0*8), rx_k_ch0 => rx_k(0), @@ -157,7 +158,7 @@ SD_TXDIS_OUT <= (others => RESET); fpga_rxrefclk_ch1 => CLK_INTERNAL_FULL, txdata_ch1 => tx_data(1*8+7 downto 1*8), tx_k_ch1 => tx_k(1), - tx_force_disp_ch1 => '0', + tx_force_disp_ch1 => tx_cd(1), tx_disp_sel_ch1 => '0', rxdata_ch1 => rx_data(1*8+7 downto 1*8), rx_k_ch1 => rx_k(1), @@ -189,7 +190,7 @@ SD_TXDIS_OUT <= (others => RESET); fpga_rxrefclk_ch2 => CLK_INTERNAL_FULL, txdata_ch2 => tx_data(2*8+7 downto 2*8), tx_k_ch2 => tx_k(2), - tx_force_disp_ch2 => '0', + tx_force_disp_ch2 => tx_cd(2), tx_disp_sel_ch2 => '0', rxdata_ch2 => rx_data(2*8+7 downto 2*8), rx_k_ch2 => rx_k(2), @@ -221,7 +222,7 @@ SD_TXDIS_OUT <= (others => RESET); fpga_rxrefclk_ch3 => CLK_INTERNAL_FULL, txdata_ch3 => tx_data(3*8+7 downto 3*8), tx_k_ch3 => tx_k(3), - tx_force_disp_ch3 => '0', + tx_force_disp_ch3 => tx_cd(3), tx_disp_sel_ch3 => '0', rxdata_ch3 => rx_data(3*8+7 downto 3*8), rx_k_ch3 => rx_k(3), @@ -296,6 +297,7 @@ gen_control : for i in 0 to 3 generate TX_DATA => tx_data(i*8+7 downto i*8), TX_K => tx_k(i), + TX_CD => tx_cd(i), RX_DATA => rx_data(i*8+7 downto i*8), RX_K => rx_k(i), diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index 715b236..1ed066e 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -37,6 +37,7 @@ entity med_sync_control is TX_DATA : out std_logic_vector(7 downto 0); TX_K : out std_logic; + TX_CD : out std_logic; RX_DATA : in std_logic_vector(7 downto 0); RX_K : in std_logic; @@ -63,7 +64,7 @@ architecture med_sync_control_arch of med_sync_control is signal rx_fsm_state : std_logic_vector(3 downto 0); signal tx_fsm_state : std_logic_vector(3 downto 0); signal wa_position_rx : std_logic_vector(3 downto 0); -signal start_timer : unsigned(20 downto 0) := (others => '0'); +signal start_timer : unsigned(21 downto 0) := (others => '0'); signal request_retr_i : std_logic; signal start_retr_i : std_logic; @@ -201,6 +202,7 @@ THE_TX : tx_control TX_DATA_OUT => TX_DATA, TX_K_OUT => TX_K, + TX_CD_OUT => TX_CD, REQUEST_RETRANSMIT_IN => request_retr_i, --TODO REQUEST_POSITION_IN => request_retr_position_i, --TODO diff --git a/media_interfaces/sync/med_sync_define.vhd b/media_interfaces/sync/med_sync_define.vhd index c5cf348..9eaf330 100644 --- a/media_interfaces/sync/med_sync_define.vhd +++ b/media_interfaces/sync/med_sync_define.vhd @@ -65,6 +65,7 @@ component tx_control is TX_DATA_OUT : out std_logic_vector( 7 downto 0); TX_K_OUT : out std_logic; + TX_CD_OUT : out std_logic; REQUEST_RETRANSMIT_IN : in std_logic := '0'; REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index ccc72b0..2a04916 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -64,7 +64,7 @@ signal ct_fifo_afull : std_logic; signal last_ct_fifo_empty : std_logic; signal last_ct_fifo_read : std_logic; -signal tmp_link_ready_i : std_logic := '0'; +signal idle_hist_i : std_logic_vector(3 downto 0) := x"0"; signal got_link_ready_i : std_logic := '0'; signal start_retr_i : std_logic; signal start_retr_pos_i : std_logic_vector(7 downto 0); @@ -139,6 +139,8 @@ PROC_RX_FSM : process begin ct_fifo_write <= '0'; start_retr_i <= '0'; rx_dlm_i <= '0'; + idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); + idle_hist_i(0) <= got_link_ready_i; case rx_state is when SLEEP => @@ -177,13 +179,10 @@ PROC_RX_FSM : process begin rx_state_bits <= x"3"; rx_state <= FIRST; next_sop <= '1'; - if reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE0 then - tmp_link_ready_i <= '0'; - got_link_ready_i <= tmp_link_ready_i; - elsif reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then - got_link_ready_i <= '1'; - tmp_link_ready_i <= '1'; - else + if reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then + idle_hist_i(0) <= '1'; + got_link_ready_i <= got_link_ready_i or (idle_hist_i(1) and idle_hist_i(3)); + elsif reg_rx_k_in = '1' then rx_state <= SLEEP; end if; @@ -271,7 +270,7 @@ STAT_REG_OUT(4) <= got_link_ready_i; STAT_REG_OUT(5) <= ct_fifo_afull; STAT_REG_OUT(6) <= ct_fifo_empty; STAT_REG_OUT(7) <= ct_fifo_write; -STAT_REG_OUT(15 downto 8) <= rx_data(7 downto 0); +STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0); STAT_REG_OUT(16) <= rx_data(16); STAT_REG_OUT(17) <= '0'; STAT_REG_OUT(31 downto 18) <= (others => '0'); diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 78e9776..298e8d2 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -103,6 +103,7 @@ architecture arch of tx_control is signal crc_en : std_logic; signal crc_data : std_logic_vector(7 downto 0); signal first_idle : std_logic; + signal toggle_idle : std_logic; begin ---------------------------------------------------------------------- @@ -248,10 +249,12 @@ begin first_idle <= first_idle; when SEND_IDLE_H => - if rx_allow_qtx = '1' then + if rx_allow_qtx = '1' or toggle_idle = '1' then TX_DATA_OUT <= D_IDLE1; + toggle_idle <= rx_allow_qtx; else TX_DATA_OUT <= D_IDLE0; + toggle_idle <= '1'; end if; TX_CD_OUT <= first_idle; first_idle <= '0'; diff --git a/trb_net16_hub_streaming_port_sctrl_record.vhd b/trb_net16_hub_streaming_port_sctrl_record.vhd index 5cca33b..0dfa337 100644 --- a/trb_net16_hub_streaming_port_sctrl_record.vhd +++ b/trb_net16_hub_streaming_port_sctrl_record.vhd @@ -223,11 +223,11 @@ begin make_gbe_reset : process begin wait until rising_edge(CLK); - if(EXTERNAL_SEND_RESET = '1') then + if EXTERNAL_SEND_RESET = '1' or med_stat_op((MII_NUMBER-1)*16+15) = '1' then external_send_reset_long <= '1'; external_send_reset_timer <= '1'; end if; - if timer_ticks(0) = '1' then + if timer_ticks(1) = '1' then external_send_reset_timer <= '0'; external_send_reset_long <= external_send_reset_timer; end if; @@ -691,4 +691,4 @@ end generate; -- STAT_DEBUG(7) <= '0'; -end architecture; \ No newline at end of file +end architecture; -- 2.43.0