From 5b64422a453054081db7466d33d7cf5f160df1e5 Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Mon, 8 Jan 2024 09:15:29 +0100 Subject: [PATCH] started vldb projecta --- mimosis/code/InputStage.vhd | 94 +-- mimosis/code/WordAlign.vhd | 30 +- mimosis/trb5sc_mimosis.vhd | 142 ++--- vldb/code/InputStage.vhd | 231 ++++++++ vldb/code/MimosisInput.vhd | 353 +++++++++++ vldb/code/WordAlign.vhd | 165 ++++++ vldb/compile.pl | 1 + vldb/config.vhd | 122 ++++ vldb/config_compile_frankfurt.pl | 25 + vldb/cores/mimosis_inp.fdc | 2 + vldb/cores/mimosis_inp.lpc | 66 +++ vldb/cores/mimosis_inp.sbx | 322 ++++++++++ vldb/cores/mimosis_inp.vhd | 205 +++++++ vldb/cores/pll_200_160/pll_200_160.fdc | 2 + vldb/cores/pll_200_160/pll_200_160.ipx | 8 + vldb/cores/pll_200_160/pll_200_160.lpc | 93 +++ vldb/cores/pll_200_160/pll_200_160.sbx | 430 ++++++++++++++ vldb/cores/pll_200_160/pll_200_160.vhd | 81 +++ vldb/cores/testout.lpc | 66 +++ vldb/cores/testout.sbx | 322 ++++++++++ vldb/cores/testout.vhd | 219 +++++++ vldb/par.p2t | 69 +++ vldb/trb5sc_vldb.lpf | 49 ++ vldb/trb5sc_vldb.prj | 284 +++++++++ vldb/trb5sc_vldb.vhd | 778 +++++++++++++++++++++++++ vldb/trb5sc_vldb_OLD.vhd | 759 ++++++++++++++++++++++++ 26 files changed, 4785 insertions(+), 133 deletions(-) create mode 100644 vldb/code/InputStage.vhd create mode 100644 vldb/code/MimosisInput.vhd create mode 100644 vldb/code/WordAlign.vhd create mode 120000 vldb/compile.pl create mode 100644 vldb/config.vhd create mode 100644 vldb/config_compile_frankfurt.pl create mode 100644 vldb/cores/mimosis_inp.fdc create mode 100644 vldb/cores/mimosis_inp.lpc create mode 100644 vldb/cores/mimosis_inp.sbx create mode 100644 vldb/cores/mimosis_inp.vhd create mode 100644 vldb/cores/pll_200_160/pll_200_160.fdc create mode 100644 vldb/cores/pll_200_160/pll_200_160.ipx create mode 100644 vldb/cores/pll_200_160/pll_200_160.lpc create mode 100644 vldb/cores/pll_200_160/pll_200_160.sbx create mode 100644 vldb/cores/pll_200_160/pll_200_160.vhd create mode 100644 vldb/cores/testout.lpc create mode 100644 vldb/cores/testout.sbx create mode 100644 vldb/cores/testout.vhd create mode 100644 vldb/par.p2t create mode 100644 vldb/trb5sc_vldb.lpf create mode 100644 vldb/trb5sc_vldb.prj create mode 100644 vldb/trb5sc_vldb.vhd create mode 100644 vldb/trb5sc_vldb_OLD.vhd diff --git a/mimosis/code/InputStage.vhd b/mimosis/code/InputStage.vhd index 0b1456e..a120718 100644 --- a/mimosis/code/InputStage.vhd +++ b/mimosis/code/InputStage.vhd @@ -11,12 +11,12 @@ entity InputStage is CLK : in std_logic; CLK_SYS : in std_logic; RESET : in std_logic; - + DIN : in std_logic_vector(7 downto 0); DOUT : out std_logic_vector(15 downto 0); - + ACTIVE : out std_logic; - + BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX ); @@ -31,38 +31,38 @@ architecture arch of InputStage is signal data_i : std_logic_vector(15 downto 0); signal add_reg : std_logic_vector(31 downto 0); - + type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT); type state_arrt is array (0 to 7) of state_t; - + type unsigned_arr is array(0 to 7) of unsigned(6 downto 0); signal sample_good, sample_bad : unsigned_arr := (others => (others => '0')); signal first_good, first_bad : unsigned_arr := (others => (others => '1')); signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0')); signal active_i : std_logic_vector(7 downto 0); - + begin reset_i <= RESET when rising_edge(CLK); THE_IN : entity work.mimosis_inp port map ( - clkin=>CLK, - reset=>reset_i, - sclk=>clk_rx, - data_cflag(7 downto 0)=>s_cflag, - data_direction(7 downto 0)=>(others => '0'), - data_loadn(7 downto 0)=>s_loadn, - data_move(7 downto 0)=>s_move, - datain(7 downto 0)=>DIN, + clkin=>CLK, + reset=>reset_i, + sclk=>clk_rx, + data_cflag(7 downto 0)=>s_cflag, + data_direction(7 downto 0)=>(others => '0'), + data_loadn(7 downto 0)=>s_loadn, + data_move(7 downto 0)=>s_move, + datain(7 downto 0)=>DIN, q(15 downto 0)=>data_i ); - + DOUT <= data_i; ACTIVE <= and(active_i); -gen_finders : for i in 0 to 7 generate +gen_finders : for i in 0 to 7 generate signal timer : unsigned(14 downto 0); signal state : state_t; signal count : unsigned(11 downto 0); @@ -70,8 +70,8 @@ gen_finders : for i in 0 to 7 generate signal lastsample : std_logic; signal train : unsigned(3 downto 0); signal last : std_logic_vector(1 downto 0); - -begin + +begin PROC_FIND : process begin wait until rising_edge(CLK); s_loadn(i) <= not add_reg(i+16); @@ -83,7 +83,7 @@ begin count <= 0; s_move(i) <= '0'; state <= LISTEN; - + when LISTEN => if timer(timer'left) = '1' then state <= STEP; @@ -96,35 +96,35 @@ begin if last_bad(i) < pos and lastsample = '0' then last_bad(i) <= pos; end if; - + else lastsample <= '0'; - sample_bad(i) <= sample_bad(i) + 1; + sample_bad(i) <= sample_bad(i) + 1; if first_bad(i) > pos then first_bad(i) <= pos; end if; if last_good(i) < pos and lastsample = '1' then last_good(i) <= pos; - end if; + end if; end if; - else + else timer <= timer + 1; end if; - + last <= data_i(i*2+1 downto i*2); - - if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and + + if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and data_i(i*2+1 downto i*2) = last then train <= train + 1; else train <= x"0"; end if; - + if train = x"3" then count <= count + 1; end if; - - + + when STEP => if s_cflag(i) = '0' then s_move(i) <= '1'; @@ -132,43 +132,43 @@ begin state <= START; else state <= CALC; - s_loadn(i) <= '0'; - end if; - + s_loadn(i) <= '0'; + end if; + when CALC => if first_good(i) = "0000000" then pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000"; - else + else pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1); - end if; + end if; state <= SET0; - + when SET0 => posi(i) <= pos; state <= SET1; - + when SET1 => state <= SET2; s_move(i) <= '1'; - + when SET2 => s_move(i) <= '0'; if pos = 0 then state <= ENDWAIT; - else + else state <= SET3; pos <= pos - 1; - end if; + end if; when SET3 => state <= SET1; - + when ENDWAIT => active_i(i) <= '1'; state <= ENDWAIT; - + end case; - + if reset_i = '1' or add_reg(0) = '1' then state <= START; pos <= 0; @@ -178,13 +178,13 @@ begin sample_bad(i) <= 0; last_good(i) <= 0; last_bad(i) <= 0; - first_good(i) <= (others => '1'); - first_bad(i) <= (others => '1'); + first_good(i) <= (others => '1'); + first_bad(i) <= (others => '1'); end if; end process; -end generate; +end generate; -PROC_REGS : process +PROC_REGS : process variable addr : integer range 0 to 7; begin wait until rising_edge(CLK_SYS); @@ -220,7 +220,7 @@ begin else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; - + end if; end if; end process; diff --git a/mimosis/code/WordAlign.vhd b/mimosis/code/WordAlign.vhd index 1db39da..2502428 100644 --- a/mimosis/code/WordAlign.vhd +++ b/mimosis/code/WordAlign.vhd @@ -11,13 +11,13 @@ entity WordAlign is CLK : in std_logic; CLK_SYS : in std_logic; RESET : in std_logic; - + DIN : in std_logic_vector(15 downto 0); DOUT : out std_logic_vector(31 downto 0); VALID : out std_logic; - + ACTIVE : in std_logic; - + BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX ); @@ -27,28 +27,28 @@ end entity; architecture arch of WordAlign is constant IDLE_WORD : std_logic_vector(15 downto 0) := x"FCAA"; constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; - - + + signal reset_i : std_logic; type word_arr is array(0 to 7) of std_logic_vector(23 downto 0); signal shift_reg, words, data_reg : word_arr; - + signal doubleword : std_logic_vector(31 downto 0); signal doubleword_valid : std_logic; - + signal control_reg : std_logic_vector(31 downto 0); alias CONF_channel_enable : std_logic_vector is control_reg(7 downto 0); alias CONF_fixalign : std_logic is control_reg(8); alias CONF_writeall : std_logic is control_reg(9); alias CONF_ignoreactive : std_logic is control_reg(10); - + signal bittime : integer range 0 to 31 := 0; signal word_update : std_logic_vector(7 downto 0); signal found_idle : std_logic_vector(7 downto 0) := (others => '0'); signal last_word_update, next_last_word_update : std_logic; signal copycnt : integer range 0 to 4; - + begin bittime <= bittime + 1 when rising_edge(CLK); @@ -63,7 +63,7 @@ begin bitcnt <= bitcnt + 1; word_update(i) <= '0'; shift_reg <= shift_reg(14 downto 0) & DIN(i*2) & DIN(i*2+1); - + if CONF_fixalign = '0' and (ACTIVE = '1' or CONF_ignoreactive = '1') then if shift_reg(15 downto 0) = IDLE_WORD then oddeven <= '1'; @@ -75,7 +75,7 @@ begin found_idle(i) <= '1'; end if; end if; - + if bitcnt = 0 then word_update(i) <= '1'; if oddeven = '1' then @@ -84,7 +84,7 @@ begin words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(16 downto 1); end if; end if; - + end process; end generate; @@ -110,7 +110,7 @@ PROC_COPY_MUX : process begin elsif copycnt = 3 then doubleword <= data_reg(6)(15 downto 0) & data_reg(7)(15 downto 0); doubleword_valid <= '1'; - elsif copycnt = 4 then + elsif copycnt = 4 then copycnt <= copycnt; end if; end process; @@ -125,7 +125,7 @@ PROC_FIFO_WRITE : process begin end process; -PROC_REGS : process +PROC_REGS : process variable addr : integer range 0 to 7; begin wait until rising_edge(CLK_SYS); @@ -155,7 +155,7 @@ begin else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; - + end if; end if; end process; diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index 3b027ec..abac92e 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -15,18 +15,18 @@ entity trb5sc_mimosis is CLK_200 : in std_logic; CLK_125 : in std_logic; CLK_EXT : in std_logic; - + TRIG_IN_BACKPL : in std_logic; --Reference Time TRIG_IN_RJ45 : in std_logic; --Reference Time IN_SELECT_EXT_CLOCK : in std_logic; SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 - + SFP_TX_DIS : out std_logic; SFP_LOS : in std_logic; SFP_MOD_0 : in std_logic; - + --AddOn -- FE_GPIO : inout std_logic_vector(11 downto 0); -- FE_CLK : out std_logic_vector( 2 downto 1); @@ -38,7 +38,7 @@ entity trb5sc_mimosis is LED_ADDON_RJ : out std_logic_vector(1 downto 0); SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); SFP_ADDON_LOS : in std_logic_vector(1 downto 0); - + RJ : inout std_logic_vector(3 downto 0); H1 : inout std_logic_vector(4 downto 0); H2 : inout std_logic_vector(4 downto 0); @@ -47,11 +47,11 @@ entity trb5sc_mimosis is H5 : inout std_logic_vector(3 downto 0); H6 : inout std_logic_vector(4 downto 0); H7 : inout std_logic_vector(4 downto 0); - + PIN : out std_logic_vector(8 downto 1); - + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; - + --ADC ADC_SCLK : out std_logic; ADC_NCS : out std_logic; @@ -78,7 +78,7 @@ entity trb5sc_mimosis is LED_RJ_GREEN : out std_logic_vector(1 downto 0); LED_RJ_RED : out std_logic_vector(1 downto 0); LED_EXT_CLOCK : out std_logic; - + --Other Connectors TEST : inout std_logic_vector(14 downto 1); --on v1 only --COMMON_SDA, COMMON_SCL : inout std_logic @@ -104,10 +104,10 @@ architecture arch of trb5sc_mimosis is signal reset_i : std_logic; signal clear_i : std_logic; signal trigger_in_i : std_logic; - - + + attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; signal debug_clock_reset : std_logic_vector(31 downto 0); signal external_clock_lock : std_logic := '0'; @@ -118,7 +118,7 @@ architecture arch of trb5sc_mimosis is signal int2med : int2med_array_t(0 to 0); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; - + signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); @@ -137,15 +137,15 @@ architecture arch of trb5sc_mimosis is signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); signal header_io_i : std_logic_vector(10 downto 1); signal timer : TIMERS; - signal add_reg : std_logic_vector(31 downto 0); + signal add_reg : std_logic_vector(31 downto 0); alias led_off : std_logic is add_reg(0); - + signal out_data : std_logic_vector(15 downto 0); signal out_i : std_logic_vector( 7 downto 0); signal inp_i : std_logic_vector( 7 downto 0); signal gbe_status : std_logic_vector(15 downto 0); - - + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); signal i2c_reg_2 : std_logic_vector(31 downto 0); signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); @@ -161,10 +161,10 @@ architecture arch of trb5sc_mimosis is --signal fwd_sop : std_logic; --signal fwd_eop : std_logic; --signal fwd_ready : std_logic; - --signal fwd_full : std_logic; + --signal fwd_full : std_logic; --signal fwd_length : std_logic_vector(15 downto 0); - --signal fwd_do_send : std_logic; - + --signal fwd_do_send : std_logic; + begin @@ -247,15 +247,15 @@ RJ(0) <= clk_40; gen_sfp_con : if SERDES_NUM = 1 generate sfp_los_i <= SFP_LOS; - sfp_prsnt_i <= SFP_MOD_0; + sfp_prsnt_i <= SFP_MOD_0; SFP_TX_DIS <= sfp_txdis_i; - end generate; + end generate; gen_bpl_con : if SERDES_NUM = 0 generate sfp_los_i <= BACK_GPIO(1); - sfp_prsnt_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); BACK_GPIO(0) <= sfp_txdis_i; - end generate; - + end generate; + --------------------------------------------------------------------------- -- Endpoint @@ -336,7 +336,7 @@ RJ(0) <= clk_40; BUS_RX(3) => busmimosis_rx, BUS_RX(4) => busi2c_rx, --BUS_RX(5) => busgbeip_rx, - --BUS_RX(6) => busgbereg_rx, + --BUS_RX(6) => busgbereg_rx, --BUS_RX(7) => busfwd_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, @@ -358,7 +358,7 @@ RJ(0) <= clk_40; ADC_CMD_2 => x"1d5cb", ADC_CMD_3 => x"1e3cb", ADC_CMD_4 => x"2f5cb", - ADC_CMD_T => x"1F393" + ADC_CMD_T => x"1F393" ) port map( CLK => clk_sys, @@ -386,7 +386,7 @@ RJ(0) <= clk_40; ADC_MOSI => ADC_MOSI, ADC_MISO => ADC_MISO, ADC_CLK => ADC_SCLK, - --Trigger & Monitor + --Trigger & Monitor MONITOR_INPUTS => (others => '0'), TRIG_GEN_INPUTS => (others => '0'), TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), @@ -409,14 +409,14 @@ RJ(0) <= clk_40; --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; - + FLASH_HOLD <= '1'; FLASH_WP <= '1'; - + --------------------------------------------------------------------------- -- I2C --------------------------------------------------------------------------- -THE_I2C : entity work.i2c_slim2 +THE_I2C : entity work.i2c_slim2 port map( CLOCK => clk_40, RESET => reset_i, @@ -463,7 +463,7 @@ PROC_I2C_REGS : process begin busi2c_tx.nack <= '0'; busi2c_tx.data <= (others => '0'); i2c_go_100 <= '0'; - + if busi2c_rx.write = '1' then busi2c_tx.ack <= '1'; if busi2c_rx.addr(3 downto 0) = x"0" then @@ -497,7 +497,7 @@ PROC_I2C_REGS : process begin else busi2c_tx.ack <= '0'; busi2c_tx.unknown <= '1'; - + end if; end if; end process; @@ -512,7 +512,7 @@ end process; PULSE_B_OUT => i2c_go ); - THE_MIMOSIS_SIGNAL_SYNC : signal_sync + THE_MIMOSIS_SIGNAL_SYNC : signal_sync generic map( WIDTH => 32, DEPTH => 2 @@ -524,7 +524,7 @@ end process; D_IN => i2c_reg_5, D_OUT => i2c_reg_5_40 ); - + --------------------------------------------------------------------------- @@ -540,18 +540,18 @@ end process; LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used - + TEST(13 downto 1) <= (others => '0'); TEST(14) <= flash_ncs_i; --for v1 boards - FLASH_NCS <= flash_ncs_i; + FLASH_NCS <= flash_ncs_i; LED_ADDON_RJ <= "00"; LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2)); LED_ADDON_SFP_GREEN(1) <= '0'; LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); LED_ADDON_SFP_ORANGE(1) <= '0'; - + ----------------------------------------------------------------------------- ---- GbE ----------------------------------------------------------------------------- @@ -586,7 +586,7 @@ end process; --RESET => reset_i, --GSR_N => GSR_N, ---- Trigger - --TRIGGER_IN => '0', + --TRIGGER_IN => '0', ---- SFP --SD_PRSNT_N_IN(0) => SFP_MOD_0, --SD_LOS_IN(0) => SFP_LOS, @@ -598,13 +598,13 @@ end process; --CTS_INFORMATION_IN => (others => '0'), --CTS_READOUT_TYPE_IN => (others => '0'), --CTS_START_READOUT_IN => '0', - --CTS_DATA_OUT => open, - --CTS_DATAREADY_OUT => open, + --CTS_DATA_OUT => open, + --CTS_DATAREADY_OUT => open, --CTS_READOUT_FINISHED_OUT => open, - --CTS_READ_IN => '1', - --CTS_LENGTH_OUT => open, + --CTS_READ_IN => '1', + --CTS_LENGTH_OUT => open, --CTS_ERROR_PATTERN_OUT => open, - ---- data channel + ---- data channel ---- only for LINK_HAS_READOUT --FEE_DATA_IN => (others => '0'), --FEE_DATAREADY_IN => '0', @@ -616,15 +616,15 @@ end process; --MY_TRBNET_ADDRESS_IN => timer.network_address, --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected ---- slow control by GbE - --GSC_CLK_IN => open, - --GSC_INIT_DATAREADY_OUT => open, - --GSC_INIT_DATA_OUT => open, - --GSC_INIT_PACKET_NUM_OUT => open, - --GSC_INIT_READ_IN => '1', - --GSC_REPLY_DATAREADY_IN => '0', - --GSC_REPLY_DATA_IN => (others => '0'), - --GSC_REPLY_PACKET_NUM_IN => (others => '0'), - --GSC_REPLY_READ_OUT => open, + --GSC_CLK_IN => open, + --GSC_INIT_DATAREADY_OUT => open, + --GSC_INIT_DATA_OUT => open, + --GSC_INIT_PACKET_NUM_OUT => open, + --GSC_INIT_READ_IN => '1', + --GSC_REPLY_DATAREADY_IN => '0', + --GSC_REPLY_DATA_IN => (others => '0'), + --GSC_REPLY_PACKET_NUM_IN => (others => '0'), + --GSC_REPLY_READ_OUT => open, --GSC_BUSY_IN => '0', ---- readout --BUS_IP_RX => busgbeip_rx, -- registers inside GbE @@ -647,18 +647,18 @@ end process; --STATUS_OUT => open, --DEBUG_OUT => open --); - + ----------------------------------------------------------------------------- ---- Test registers ------------------------------------------------------------------------------ +----------------------------------------------------------------------------- --THE_REGS : process begin --wait until rising_edge(clk_sys); --busfwd_tx.ack <= '0'; --busfwd_tx.nack <= '0'; --busfwd_tx.unknown <= '0'; - + --if busfwd_rx.write = '1' then --busfwd_tx.ack <= '1'; --case busfwd_rx.addr(7 downto 0) is @@ -680,17 +680,17 @@ end process; --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; - --end case; + --end case; --end if; --if reset_i = '1' then --fwd_do_send <= '0'; --end if; ---end process; - - +--end process; + + --------------------------------------------------------------------------- -- Output stage ---------------------------------------------------------------------------- +--------------------------------------------------------------------------- THE_OUT : entity work.testout port map( clkout => open, @@ -703,13 +703,13 @@ end process; data_move => (others => '0'), dout => out_i ); - - PROC_OUT : process + + PROC_OUT : process variable cnt : integer range 0 to 7; begin wait until rising_edge(clk_160); cnt := cnt + 1; - case cnt is + case cnt is when 0 => out_data <= x"ffff"; when 1 => out_data <= x"ffff"; when 2 => out_data <= x"ffff"; @@ -719,12 +719,12 @@ end process; when 6 => out_data <= x"5555"; when 7 => out_data <= x"5555"; end case; - end process; + end process; H3(3 downto 0) <= out_i(3 downto 0); H4(3 downto 0) <= out_i(7 downto 4); - + --------------------------------------------------------------------------- -- Input stage --------------------------------------------------------------------------- @@ -733,12 +733,12 @@ end process; CLK => clk_160, CLK_SYS => clk_sys, RESET => reset_i, - + INPUT => inp_i, - + BUSRDO_RX => readout_rx, BUSRDO_TX => readout_tx(0), - + BUS_RX => busmimosis_rx, BUS_TX => busmimosis_tx ); @@ -750,9 +750,9 @@ end process; ------------------------------------------------------------------------------- -- readout_tx(0).data_finished <= '1'; -- readout_tx(0).data_write <= '0'; --- readout_tx(0).busy_release <= '1'; - -SFP_ADDON_TX_DIS <= (others => '0'); +-- readout_tx(0).busy_release <= '1'; + +SFP_ADDON_TX_DIS <= (others => '0'); end architecture; diff --git a/vldb/code/InputStage.vhd b/vldb/code/InputStage.vhd new file mode 100644 index 0000000..a120718 --- /dev/null +++ b/vldb/code/InputStage.vhd @@ -0,0 +1,231 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity InputStage is + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + DIN : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(15 downto 0); + + ACTIVE : out std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of InputStage is + + signal clk_rx : std_logic; + signal reset_i : std_logic; + signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0'); + + signal data_i : std_logic_vector(15 downto 0); + signal add_reg : std_logic_vector(31 downto 0); + + type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT); + type state_arrt is array (0 to 7) of state_t; + + type unsigned_arr is array(0 to 7) of unsigned(6 downto 0); + signal sample_good, sample_bad : unsigned_arr := (others => (others => '0')); + signal first_good, first_bad : unsigned_arr := (others => (others => '1')); + signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0')); + signal active_i : std_logic_vector(7 downto 0); + +begin + +reset_i <= RESET when rising_edge(CLK); + +THE_IN : entity work.mimosis_inp + port map ( + clkin=>CLK, + reset=>reset_i, + sclk=>clk_rx, + data_cflag(7 downto 0)=>s_cflag, + data_direction(7 downto 0)=>(others => '0'), + data_loadn(7 downto 0)=>s_loadn, + data_move(7 downto 0)=>s_move, + datain(7 downto 0)=>DIN, + q(15 downto 0)=>data_i + ); + + +DOUT <= data_i; +ACTIVE <= and(active_i); + +gen_finders : for i in 0 to 7 generate + signal timer : unsigned(14 downto 0); + signal state : state_t; + signal count : unsigned(11 downto 0); + signal pos : unsigned(6 downto 0); + signal lastsample : std_logic; + signal train : unsigned(3 downto 0); + signal last : std_logic_vector(1 downto 0); + +begin + PROC_FIND : process begin + wait until rising_edge(CLK); + s_loadn(i) <= not add_reg(i+16); + active_i(i) <= '0'; + + case state is + when START => + timer <= 0; + count <= 0; + s_move(i) <= '0'; + state <= LISTEN; + + when LISTEN => + if timer(timer'left) = '1' then + state <= STEP; + if count >= 2047 and count <= 2049 then + sample_good(i) <= sample_good(i) + 1; + lastsample <= '1'; + if first_good(i) > pos then + first_good(i) <= pos; + end if; + if last_bad(i) < pos and lastsample = '0' then + last_bad(i) <= pos; + end if; + + else + lastsample <= '0'; + sample_bad(i) <= sample_bad(i) + 1; + if first_bad(i) > pos then + first_bad(i) <= pos; + end if; + if last_good(i) < pos and lastsample = '1' then + last_good(i) <= pos; + end if; + end if; + else + timer <= timer + 1; + end if; + + last <= data_i(i*2+1 downto i*2); + + if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and + data_i(i*2+1 downto i*2) = last then + train <= train + 1; + else + train <= x"0"; + end if; + + if train = x"3" then + count <= count + 1; + end if; + + + when STEP => + if s_cflag(i) = '0' then + s_move(i) <= '1'; + pos <= pos + 1; + state <= START; + else + state <= CALC; + s_loadn(i) <= '0'; + end if; + + when CALC => + if first_good(i) = "0000000" then + pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000"; + else + pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1); + end if; + state <= SET0; + + when SET0 => + posi(i) <= pos; + state <= SET1; + + when SET1 => + state <= SET2; + s_move(i) <= '1'; + + when SET2 => + s_move(i) <= '0'; + if pos = 0 then + state <= ENDWAIT; + else + state <= SET3; + pos <= pos - 1; + end if; + + when SET3 => + state <= SET1; + + when ENDWAIT => + active_i(i) <= '1'; + state <= ENDWAIT; + + end case; + + if reset_i = '1' or add_reg(0) = '1' then + state <= START; + pos <= 0; + s_loadn(i) <= '0'; + active_i(i) <= '0'; + sample_good(i) <= 0; + sample_bad(i) <= 0; + last_good(i) <= 0; + last_bad(i) <= 0; + first_good(i) <= (others => '1'); + first_bad(i) <= (others => '1'); + end if; + end process; +end generate; + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + addr := to_integer(unsigned(BUS_RX.addr(2 downto 0))); + if BUS_RX.write = '1' then + if BUS_RX.addr(15 downto 0) = x"0010" then + BUS_TX.ack <= '1'; + add_reg <= BUS_RX.data; + else + BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr(15 downto 0) = x"0010" then + BUS_TX.data <= add_reg; + elsif BUS_RX.addr(15 downto 4) = x"000" then + if BUS_RX.addr(3) = '0' then + BUS_TX.data(6 downto 0) <= std_logic_vector(sample_good(addr)); + BUS_TX.data(14 downto 8) <= std_logic_vector(sample_bad(addr)); + BUS_TX.data(16) <= s_cflag(addr); + BUS_TX.data(20) <= active_i(addr); + BUS_TX.data(30 downto 24)<= std_logic_vector(posi(addr)); + else + BUS_TX.data(6 downto 0) <= std_logic_vector(first_good(addr)); + BUS_TX.data(14 downto 8) <= std_logic_vector(last_good(addr)); + BUS_TX.data(22 downto 16) <= std_logic_vector(first_bad(addr)); + BUS_TX.data(30 downto 24) <= std_logic_vector(last_bad(addr)); + end if; + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + + end if; + end if; +end process; + + + + +end architecture; diff --git a/vldb/code/MimosisInput.vhd b/vldb/code/MimosisInput.vhd new file mode 100644 index 0000000..5935f82 --- /dev/null +++ b/vldb/code/MimosisInput.vhd @@ -0,0 +1,353 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity MimosisInput is + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic_vector(7 downto 0); + + BUSRDO_RX : in READOUT_RX; + BUSRDO_TX : out READOUT_TX; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of MimosisInput is + constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; + constant WORD_LIMIT : integer := 8500; + signal input_active_i : std_logic; + signal data_i : std_logic_vector(15 downto 0); + signal inp_i : std_logic_vector(7 downto 0); + signal word_i : std_logic_vector(31 downto 0); + signal word_valid : std_logic; + + signal businp_rx, busword_rx, busmimosis_rx : CTRLBUS_RX; + signal businp_tx, busword_tx, busmimosis_tx : CTRLBUS_TX; + + signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic; + signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic; + signal ct_fifo_data_out : std_logic_vector(31 downto 0); + + signal buffer_empty, buffer_full : std_logic; + signal buffer_write, buffer_read : std_logic; + signal buffer_valid, buffer_nextvalid : std_logic; + signal buffer_din, buffer_dout : std_logic_vector(31 downto 0); + signal buffer_fill : std_logic_vector(13 downto 0); + + type state_t is (IDLE,START_COPY, START_COPY2, COPY,FINISH,DONE); + signal state : state_t; + signal word_count : integer range 0 to 8191; + + signal frame_number : std_logic_vector(31 downto 0); + signal frame_length : std_logic_vector(15 downto 0); + signal count_words : unsigned(15 downto 0); + signal count_header : unsigned(31 downto 0); + signal count_trailer : unsigned(31 downto 0); + signal count_fe : unsigned(31 downto 0); + signal count_ff : unsigned(31 downto 0); + signal count_oof : unsigned(31 downto 0); + signal pulse_stats : std_logic_vector(31 downto 0); + signal buffer_blocked : std_logic; + type frame_state_t is (IDLE,HDR1,HDR2,HDR3,WRITING); + signal frame_state : frame_state_t; + + +begin + + THE_IN : entity work.InputStage + port map ( + CLK => CLK, + CLK_SYS => CLK_SYS, + RESET => RESET, + + DIN => INPUT, + DOUT => data_i, + ACTIVE => input_active_i, + + BUS_RX => businp_rx, + BUS_TX => businp_tx + ); + + + THE_WORDS: entity work.WordAlign + port map( + CLK => CLK, + CLK_SYS => CLK_SYS, + RESET => RESET, + + DIN => data_i, + DOUT => word_i, + VALID => word_valid, + + ACTIVE => input_active_i, + + BUS_RX => busword_rx, + BUS_TX => busword_tx + ); + + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg + port map( + Data(31 downto 0) => word_i(31 downto 0), + Data(35 downto 32) => "0000", + WrClock => CLK, + RdClock => CLK_SYS, + WrEn => word_valid, + RdEn => ct_fifo_read, + Reset => RESET, + RPReset => RESET, + Q(31 downto 0) => ct_fifo_data_out(31 downto 0), + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + + ct_fifo_read <= '1'; + ct_fifo_nextvalid <= ct_fifo_read and not ct_fifo_empty when rising_edge(CLK_SYS); + ct_fifo_valid <= ct_fifo_nextvalid when rising_edge(CLK_SYS); + +---------------------------------------------------------------------- +-- Frame Copy +---------------------------------------------------------------------- + +PROC_FRAMES : process begin + wait until rising_edge(CLK_SYS); + buffer_write <= '0'; + buffer_din <= ct_fifo_data_out; + + if ct_fifo_valid = '1' then + count_words <= count_words + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then + count_fe <= count_fe + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then + count_ff <= count_ff + 1; + end if; + + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) < x"FC" and frame_state = IDLE then + count_oof <= count_oof + 1; + end if; + + case frame_state is + when IDLE => + count_words <= (others => '0'); + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then + frame_state <= HDR1; + frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= '1' when buffer_full = '0' and state = IDLE else '0'; + buffer_blocked <= '0' when buffer_full = '0' and state = IDLE else '1'; + count_header <= count_header + 1; + end if; + when HDR1 => + if ct_fifo_valid = '1' then + frame_state <= HDR2; + frame_number(31 downto 16) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= not buffer_blocked; + end if; + when HDR2 => + if ct_fifo_valid = '1' then + frame_state <= HDR3; + buffer_din(23 downto 16) <= pulse_stats(7 downto 0); + buffer_din(7 downto 0) <= pulse_stats(15 downto 8); + buffer_write <= not buffer_blocked; + end if; + when HDR3 => + if ct_fifo_valid = '1' then + frame_state <= WRITING; + buffer_din(23 downto 16) <= pulse_stats(23 downto 16); + buffer_din(7 downto 0) <= pulse_stats(31 downto 24); + buffer_write <= not buffer_blocked; + end if; + when WRITING => + buffer_write <= ct_fifo_valid and not buffer_blocked; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then + frame_state <= IDLE; + frame_length <= std_logic_vector(count_words); + count_trailer <= count_trailer + 1; + end if; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" and count_words >= x"0004" then + frame_state <= HDR1; + count_header <= count_header + 1; + frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); + buffer_write <= not buffer_full; + buffer_blocked <= buffer_full; + end if; + end case; + + end process; + + + +---------------------------------------------------------------------- +-- Main Fifo +---------------------------------------------------------------------- +THE_FIFO : entity work.fifo_36x8k_oreg + port map( + Data(31 downto 0) => buffer_din, + Clock => CLK_SYS, + WrEn => buffer_write, + RdEn => buffer_read, + Reset => RESET, + AmFullThresh => "1000000000000", + Q(31 downto 0) => buffer_dout, + WCNT => buffer_fill, + Empty => buffer_empty, + Full => open, + AlmostFull => buffer_full + ); + + buffer_nextvalid <= buffer_read and not buffer_empty when rising_edge(CLK_SYS); + buffer_valid <= buffer_nextvalid when rising_edge(CLK_SYS); + +--------------------------------------------------------------------------- +-- Buffer Handler +--------------------------------------------------------------------------- +PROC_RDO : process begin + wait until rising_edge(CLK_SYS); +-- if state = IDLE and buffer_full = '1' then +-- buffer_read <= '1'; +-- else + buffer_read <= '0'; +-- end if; + + + BUSRDO_TX.busy_release <= '0'; + BUSRDO_TX.data_write <= '0'; + BUSRDO_TX.data_finished <= '0'; + + case state is + when IDLE => + if BUSRDO_RX.valid_timing_trg = '1' or BUSRDO_RX.valid_notiming_trg = '1' then + state <= START_COPY; + buffer_read <= '1'; + word_count <= 0; + end if; + if BUSRDO_RX.invalid_trg = '1' then + state <= FINISH; + end if; + + when START_COPY => + state <= START_COPY2; + buffer_read <= '1'; + word_count <= word_count + 1; + + when START_COPY2 => + state <= COPY; + buffer_read <= '1'; + word_count <= word_count + 1; + + when COPY => + + if word_count = WORD_LIMIT or buffer_valid = '0' then + state <= FINISH; + else + buffer_read <= '1'; + word_count <= word_count + 1; + BUSRDO_TX.data <= buffer_dout; + BUSRDO_TX.data_write <= '1'; + end if; + + when FINISH => + BUSRDO_TX.data_finished <= '1'; + state <= DONE; + + when DONE => + BUSRDO_TX.busy_release <= '1'; + state <= IDLE; + end case; + +end process; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", others => x"0000"), + PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 4, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => CLK_SYS, + RESET => RESET, + + REGIO_RX => BUS_RX, + REGIO_TX => BUS_TX, + + BUS_RX(0) => businp_rx, + BUS_RX(1) => busword_rx, + BUS_RX(2) => busmimosis_rx, + + BUS_TX(0) => businp_tx, + BUS_TX(1) => busword_tx, + BUS_TX(2) => busmimosis_tx, + STAT_DEBUG => open + ); + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + busmimosis_tx.ack <= '0'; + busmimosis_tx.unknown <= '0'; + busmimosis_tx.nack <= '0'; + busmimosis_tx.data <= (others => '0'); + + if busmimosis_rx.write = '1' then + if busmimosis_rx.addr = x"0009" then + pulse_stats <= busmimosis_rx.data; + busmimosis_tx.ack <= '1'; + else + busmimosis_tx.unknown <= '1'; + end if; + elsif busmimosis_rx.read = '1' then + busmimosis_tx.ack <= '1'; + if busmimosis_rx.addr = x"0000" then + busmimosis_tx.data <= std_logic_vector(count_header); + elsif busmimosis_rx.addr = x"0001" then + busmimosis_tx.data <= std_logic_vector(count_trailer); + elsif busmimosis_rx.addr = x"0002" then + busmimosis_tx.data <= x"0000" & frame_length; + elsif busmimosis_rx.addr = x"0003" then + busmimosis_tx.data <= frame_number; + elsif busmimosis_rx.addr = x"0004" then + busmimosis_tx.data <= x"0000" & std_logic_vector(count_words); + elsif busmimosis_rx.addr = x"0005" then + busmimosis_tx.data <= x"0000" & "00" & buffer_fill; + elsif busmimosis_rx.addr = x"0006" then + busmimosis_tx.data <= std_logic_vector(count_fe); + elsif busmimosis_rx.addr = x"0007" then + busmimosis_tx.data <= std_logic_vector(count_ff); + elsif busmimosis_rx.addr = x"0008" then + busmimosis_tx.data <= std_logic_vector(count_oof); + elsif busmimosis_rx.addr = x"0009" then + busmimosis_tx.data <= pulse_stats; + else + busmimosis_tx.ack <= '0'; + busmimosis_tx.unknown <= '1'; + + end if; + end if; +end process; + +end architecture; diff --git a/vldb/code/WordAlign.vhd b/vldb/code/WordAlign.vhd new file mode 100644 index 0000000..2502428 --- /dev/null +++ b/vldb/code/WordAlign.vhd @@ -0,0 +1,165 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; + + +entity WordAlign is + port ( + CLK : in std_logic; + CLK_SYS : in std_logic; + RESET : in std_logic; + + DIN : in std_logic_vector(15 downto 0); + DOUT : out std_logic_vector(31 downto 0); + VALID : out std_logic; + + ACTIVE : in std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end entity; + + +architecture arch of WordAlign is + constant IDLE_WORD : std_logic_vector(15 downto 0) := x"FCAA"; + constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; + + + signal reset_i : std_logic; + type word_arr is array(0 to 7) of std_logic_vector(23 downto 0); + signal shift_reg, words, data_reg : word_arr; + + signal doubleword : std_logic_vector(31 downto 0); + signal doubleword_valid : std_logic; + + signal control_reg : std_logic_vector(31 downto 0); + alias CONF_channel_enable : std_logic_vector is control_reg(7 downto 0); + alias CONF_fixalign : std_logic is control_reg(8); + alias CONF_writeall : std_logic is control_reg(9); + alias CONF_ignoreactive : std_logic is control_reg(10); + + signal bittime : integer range 0 to 31 := 0; + + signal word_update : std_logic_vector(7 downto 0); + signal found_idle : std_logic_vector(7 downto 0) := (others => '0'); + signal last_word_update, next_last_word_update : std_logic; + signal copycnt : integer range 0 to 4; + +begin + +bittime <= bittime + 1 when rising_edge(CLK); + +gen_links: for i in 0 to 7 generate + signal bitcnt : integer range 0 to 7 := 0; + signal oddeven : std_logic; + signal shift_reg : std_logic_vector(16 downto 0); +begin + process begin + wait until rising_edge(CLK); + bitcnt <= bitcnt + 1; + word_update(i) <= '0'; + shift_reg <= shift_reg(14 downto 0) & DIN(i*2) & DIN(i*2+1); + + if CONF_fixalign = '0' and (ACTIVE = '1' or CONF_ignoreactive = '1') then + if shift_reg(15 downto 0) = IDLE_WORD then + oddeven <= '1'; + bitcnt <= 1; + found_idle(i) <= '1'; + elsif shift_reg(16 downto 1) = IDLE_WORD then + oddeven <= '0'; + bitcnt <= 1; + found_idle(i) <= '1'; + end if; + end if; + + if bitcnt = 0 then + word_update(i) <= '1'; + if oddeven = '1' then + words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(15 downto 0); + else + words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(16 downto 1); + end if; + end if; + + end process; +end generate; + +next_last_word_update <= word_update(0) when rising_edge(CLK); +last_word_update <= next_last_word_update when rising_edge(CLK); + +PROC_COPY_MUX : process begin + wait until rising_edge(CLK); + doubleword_valid <= '0'; + copycnt <= copycnt + 1; + if last_word_update = '1' then + data_reg <= words; + copycnt <= 0; + elsif copycnt = 0 then + doubleword <= data_reg(0)(15 downto 0) & data_reg(1)(15 downto 0); + doubleword_valid <= '1'; + elsif copycnt = 1 then + doubleword <= data_reg(2)(15 downto 0) & data_reg(3)(15 downto 0); + doubleword_valid <= '1'; + elsif copycnt = 2 then + doubleword <= data_reg(4)(15 downto 0) & data_reg(5)(15 downto 0); + doubleword_valid <= '1'; + elsif copycnt = 3 then + doubleword <= data_reg(6)(15 downto 0) & data_reg(7)(15 downto 0); + doubleword_valid <= '1'; + elsif copycnt = 4 then + copycnt <= copycnt; + end if; +end process; + +PROC_FIFO_WRITE : process begin + wait until rising_edge(CLK); + DOUT <= doubleword; + VALID <= '0'; + if doubleword_valid = '1' and (doubleword /= IDLE_WORD & IDLE_WORD or CONF_writeall = '1') then + VALID <= '1'; + end if; +end process; + + +PROC_REGS : process + variable addr : integer range 0 to 7; +begin + wait until rising_edge(CLK_SYS); + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.data <= (others => '0'); + addr := to_integer(unsigned(BUS_RX.addr(2 downto 0))); + if BUS_RX.write = '1' then + if BUS_RX.addr(15 downto 0) = x"0000" then + BUS_TX.ack <= '1'; + control_reg <= BUS_RX.data; + else + BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr(15 downto 0) = x"0000" then + BUS_TX.data <= control_reg; + elsif BUS_RX.addr(15 downto 4) = x"001" then + if BUS_RX.addr(3) = '0' then + BUS_TX.data <= "000" & found_idle(addr) & x"0" & words(addr); + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end if; + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + + end if; + end if; +end process; + + + +end architecture; diff --git a/vldb/compile.pl b/vldb/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/vldb/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/vldb/config.vhd b/vldb/config.vhd new file mode 100644 index 0000000..5374934 --- /dev/null +++ b/vldb/config.vhd @@ -0,0 +1,122 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant FPGA_SIZE : string := "85KUM"; +-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement +-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module +-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons +-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 +-- -- 0: single edge only, +-- -- 1: same channel, +-- -- 2: alternating channels, +-- -- 3: same channel with stretcher +-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size +-- -- mode: 0, 1, 2, 3, 7 +-- -- size: 32, 64, 96, 128, dyn +-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC +-- -- 0: Single fine time as the sum of the two transitions +-- -- 1: Double fine time, individual transitions +-- -- 13: Debug - fine time + (if 0x3ff full chain) +-- -- 14: Debug - single fine time and the ROM addresses for the two transitions +-- -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 15; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 15000; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + constant USE_GBE : integer := c_YES; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F575"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82"; + + constant INCLUDE_UART : integer := c_NO; + constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_ADC : integer := c_YES; + constant INCLUDE_I2C : integer := c_YES; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1'); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + +-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); +-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); +-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); +-- t(15) := '1'; --TDC +-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1)); + + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/vldb/config_compile_frankfurt.pl b/vldb/config_compile_frankfurt.pl new file mode 100644 index 0000000..36b1f28 --- /dev/null +++ b/vldb/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_vldb", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_hdmi', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/vldb/cores/mimosis_inp.fdc b/vldb/cores/mimosis_inp.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/vldb/cores/mimosis_inp.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/vldb/cores/mimosis_inp.lpc b/vldb/cores/mimosis_inp.lpc new file mode 100644 index 0000000..30827bf --- /dev/null +++ b/vldb/cores/mimosis_inp.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=mimosis_inp +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/03/2019 +Time=14:45:56 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +trioddr=0 +io_type=LVDS +width=8 +freq_in=160 +bandwidth=2560 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Receive +trioddr2=0 +io_type2=LVDS +freq_in2=160 +gear=2:1 +aligned2=Centered +width2=8 +DataLane=By Lane +EnECLK=0 +Interface=GDDRX1_RX.SCLK.Centered +Delay=Dynamic User Defined +DelVal=1 +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane diff --git a/vldb/cores/mimosis_inp.sbx b/vldb/cores/mimosis_inp.sbx new file mode 100644 index 0000000..e0c4c05 --- /dev/null +++ b/vldb/cores/mimosis_inp.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./mimosis_inp.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./mimosis_inp.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-05-31.19:33:04 + 2019-06-03.14:45:58 + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/03/2019 + + + ModuleName + mimosis_inp + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 14:45:56 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Lane + + + DelVal + 1 + + + Delay + Dynamic User Defined + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX1_RX.SCLK.Centered + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Edge-to-Edge + + + aligned2 + Centered + + + bandwidth + 2560 + + + enClkIBuf + 0 + + + freq_in + 160 + + + freq_in2 + 160 + + + gear + 2:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Receive + + + mode2 + Receive + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 8 + + + width2 + 8 + + + + cmd_line + -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane + + + + + + + LATTICE + LOCAL + mimosis_inp + 1.0 + + + + diff --git a/vldb/cores/mimosis_inp.vhd b/vldb/cores/mimosis_inp.vhd new file mode 100644 index 0000000..c6ce890 --- /dev/null +++ b/vldb/cores/mimosis_inp.vhd @@ -0,0 +1,205 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/mimosis_inp/mimosis_inp.fdc + +-- Mon Jun 3 14:45:58 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity mimosis_inp is + port ( + clkin: in std_logic; + reset: in std_logic; + sclk: out std_logic; + data_cflag: out std_logic_vector(7 downto 0); + data_direction: in std_logic_vector(7 downto 0); + data_loadn: in std_logic_vector(7 downto 0); + data_move: in std_logic_vector(7 downto 0); + datain: in std_logic_vector(7 downto 0); + q: out std_logic_vector(15 downto 0)); +end mimosis_inp; + +architecture Structure of mimosis_inp is + + -- internal signal declarations + signal buf_clkin: std_logic; + signal qb7: std_logic; + signal qa7: std_logic; + signal qb6: std_logic; + signal qa6: std_logic; + signal qb5: std_logic; + signal qa5: std_logic; + signal qb4: std_logic; + signal qa4: std_logic; + signal qb3: std_logic; + signal qa3: std_logic; + signal qb2: std_logic; + signal qa2: std_logic; + signal qb1: std_logic; + signal qa1: std_logic; + signal qb0: std_logic; + signal qa0: std_logic; + signal sclk_t: std_logic; + signal dataini_t7: std_logic; + signal dataini_t6: std_logic; + signal dataini_t5: std_logic; + signal dataini_t4: std_logic; + signal dataini_t3: std_logic; + signal dataini_t2: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_dataini7: std_logic; + signal buf_dataini6: std_logic; + signal buf_dataini5: std_logic; + signal buf_dataini4: std_logic; + signal buf_dataini3: std_logic; + signal buf_dataini2: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; + + attribute IO_TYPE : string; +-- attribute IO_TYPE of Inst3_IB : label is "LVDS"; + attribute IO_TYPE of Inst1_IB7 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB6 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB5 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements +-- Inst3_IB: IB +-- port map (I=>clkin, O=>buf_clkin); +buf_clkin <= clkin; + + Inst2_IDDRX1F7: IDDRX1F + port map (D=>dataini_t7, SCLK=>sclk_t, RST=>reset, Q0=>qa7, + Q1=>qb7); + + Inst2_IDDRX1F6: IDDRX1F + port map (D=>dataini_t6, SCLK=>sclk_t, RST=>reset, Q0=>qa6, + Q1=>qb6); + + Inst2_IDDRX1F5: IDDRX1F + port map (D=>dataini_t5, SCLK=>sclk_t, RST=>reset, Q0=>qa5, + Q1=>qb5); + + Inst2_IDDRX1F4: IDDRX1F + port map (D=>dataini_t4, SCLK=>sclk_t, RST=>reset, Q0=>qa4, + Q1=>qb4); + + Inst2_IDDRX1F3: IDDRX1F + port map (D=>dataini_t3, SCLK=>sclk_t, RST=>reset, Q0=>qa3, + Q1=>qb3); + + Inst2_IDDRX1F2: IDDRX1F + port map (D=>dataini_t2, SCLK=>sclk_t, RST=>reset, Q0=>qa2, + Q1=>qb2); + + Inst2_IDDRX1F1: IDDRX1F + port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1, + Q1=>qb1); + + Inst2_IDDRX1F0: IDDRX1F + port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0, + Q1=>qb0); + + udel_dataini7: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini7, LOADN=>data_loadn(7), + MOVE=>data_move(7), DIRECTION=>data_direction(7), + Z=>dataini_t7, CFLAG=>data_cflag(7)); + + udel_dataini6: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini6, LOADN=>data_loadn(6), + MOVE=>data_move(6), DIRECTION=>data_direction(6), + Z=>dataini_t6, CFLAG=>data_cflag(6)); + + udel_dataini5: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini5, LOADN=>data_loadn(5), + MOVE=>data_move(5), DIRECTION=>data_direction(5), + Z=>dataini_t5, CFLAG=>data_cflag(5)); + + udel_dataini4: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini4, LOADN=>data_loadn(4), + MOVE=>data_move(4), DIRECTION=>data_direction(4), + Z=>dataini_t4, CFLAG=>data_cflag(4)); + + udel_dataini3: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini3, LOADN=>data_loadn(3), + MOVE=>data_move(3), DIRECTION=>data_direction(3), + Z=>dataini_t3, CFLAG=>data_cflag(3)); + + udel_dataini2: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini2, LOADN=>data_loadn(2), + MOVE=>data_move(2), DIRECTION=>data_direction(2), + Z=>dataini_t2, CFLAG=>data_cflag(2)); + + udel_dataini1: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini1, LOADN=>data_loadn(1), + MOVE=>data_move(1), DIRECTION=>data_direction(1), + Z=>dataini_t1, CFLAG=>data_cflag(1)); + + udel_dataini0: DELAYF + generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_dataini0, LOADN=>data_loadn(0), + MOVE=>data_move(0), DIRECTION=>data_direction(0), + Z=>dataini_t0, CFLAG=>data_cflag(0)); + + Inst1_IB7: IB + port map (I=>datain(7), O=>buf_dataini7); + + Inst1_IB6: IB + port map (I=>datain(6), O=>buf_dataini6); + + Inst1_IB5: IB + port map (I=>datain(5), O=>buf_dataini5); + + Inst1_IB4: IB + port map (I=>datain(4), O=>buf_dataini4); + + Inst1_IB3: IB + port map (I=>datain(3), O=>buf_dataini3); + + Inst1_IB2: IB + port map (I=>datain(2), O=>buf_dataini2); + + Inst1_IB1: IB + port map (I=>datain(1), O=>buf_dataini1); + + Inst1_IB0: IB + port map (I=>datain(0), O=>buf_dataini0); + + sclk <= sclk_t; + q(15) <= qb7; + q(14) <= qa7; + q(13) <= qb6; + q(12) <= qa6; + q(11) <= qb5; + q(10) <= qa5; + q(9) <= qb4; + q(8) <= qa4; + q(7) <= qb3; + q(6) <= qa3; + q(5) <= qb2; + q(4) <= qa2; + q(3) <= qb1; + q(2) <= qa1; + q(1) <= qb0; + q(0) <= qa0; + sclk_t <= buf_clkin; +end Structure; diff --git a/vldb/cores/pll_200_160/pll_200_160.fdc b/vldb/cores/pll_200_160/pll_200_160.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/vldb/cores/pll_200_160/pll_200_160.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/vldb/cores/pll_200_160/pll_200_160.ipx b/vldb/cores/pll_200_160/pll_200_160.ipx new file mode 100644 index 0000000..43fe758 --- /dev/null +++ b/vldb/cores/pll_200_160/pll_200_160.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/vldb/cores/pll_200_160/pll_200_160.lpc b/vldb/cores/pll_200_160/pll_200_160.lpc new file mode 100644 index 0000000..defee1c --- /dev/null +++ b/vldb/cores/pll_200_160/pll_200_160.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_200_160 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/12/2021 +Time=15:18:43 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=200 +CLKI_DIV=5 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=160 +CLKOP_TOL=0.0 +CLKOP_DIV=4 +CLKOP_ACTUAL_FREQ=160.000000 +CLKOP_MUXA=DISABLED +CLKOS_Enable=ENABLED +CLKOS_FREQ=320 +CLKOS_TOL=0.0 +CLKOS_DIV=2 +CLKOS_ACTUAL_FREQ=320.000000 +CLKOS_MUXB=DISABLED +CLKOS2_Enable=ENABLED +CLKOS2_FREQ=40.00 +CLKOS2_TOL=0.0 +CLKOS2_DIV=16 +CLKOS2_ACTUAL_FREQ=40.000000 +CLKOS2_MUXC=DISABLED +CLKOS3_Enable=DISABLED +CLKOS3_FREQ=100.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=1 +CLKOS3_ACTUAL_FREQ= +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=CLKOP +CLKFB_DIV=4 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=640.000 +PLL_BW=4.655 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=DISABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 diff --git a/vldb/cores/pll_200_160/pll_200_160.sbx b/vldb/cores/pll_200_160/pll_200_160.sbx new file mode 100644 index 0000000..2c7f06c --- /dev/null +++ b/vldb/cores/pll_200_160/pll_200_160.sbx @@ -0,0 +1,430 @@ + + + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.8 + + + Diamond_Simulation + simulation + + ./pll_200_160.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./pll_200_160.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-06-04.11:21:55 + 2021-07-02.12:08:04 + 3.11.2.446 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 07/02/2021 + + + ModuleName + pll_200_160 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 12:07:59 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 4 + + + CLKI_DIV + 5 + + + CLKI_FREQ + 200 + + + CLKOP_ACTUAL_FREQ + 160.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 4 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 160 + + + CLKOP_MUXA + DISABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + DISABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + DISABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 100.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + 320.000000 + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 2 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + ENABLED + + + CLKOS_FREQ + 320 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + CLKOP + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 4.655 + + + PLL_LOCK_MODE + DISABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 640.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1 + + + + + + + LATTICE + LOCAL + pll_200_160 + 1.0 + + + + diff --git a/vldb/cores/pll_200_160/pll_200_160.vhd b/vldb/cores/pll_200_160/pll_200_160.vhd new file mode 100644 index 0000000..6759858 --- /dev/null +++ b/vldb/cores/pll_200_160/pll_200_160.vhd @@ -0,0 +1,81 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 + +-- Fri Nov 12 15:18:43 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_200_160 is + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic); +end pll_200_160; + +architecture Structure of pll_200_160 is + + -- internal signal declarations + signal REFCLK: std_logic; + signal LOCK: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "40.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "12"; + attribute LPF_RESISTOR of PLLInst_0 : label is "8"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 15, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 16, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4, + CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>open); + + CLKOS2 <= CLKOS2_t; + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; diff --git a/vldb/cores/testout.lpc b/vldb/cores/testout.lpc new file mode 100644 index 0000000..c705e50 --- /dev/null +++ b/vldb/cores/testout.lpc @@ -0,0 +1,66 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=6.0 +ModuleName=testout +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=06/05/2019 +Time=14:55:39 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Transmit +trioddr=0 +io_type=LVDS +width=8 +freq_in=160 +bandwidth=2560 +aligned=Edge-to-Edge +pre-configuration=DISABLED +mode2=Transmit +trioddr2=0 +io_type2=LVDS +freq_in2=160 +gear=2:1 +aligned2=Edge-to-Edge +width2=8 +DataLane=By Lane +EnECLK=0 +Interface=GDDRX1_TX.SCLK.Aligned +Delay=Dynamic User Defined +DelVal=1 +EnInEdge= +NumEdge=BOTH +EnDynamic=0 +GenPll=0 +Freq= +AFreq= +Reference=0 +IOBUF= +ReceiverSync=0 +EnDynamicAlign= +DynamicAlign= +MIPIFilter=0 +enClkIBuf=0 +ClkIBuf=LVDS + +[Command] +cmd_line= -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane diff --git a/vldb/cores/testout.sbx b/vldb/cores/testout.sbx new file mode 100644 index 0000000..7b87c2e --- /dev/null +++ b/vldb/cores/testout.sbx @@ -0,0 +1,322 @@ + + + + Lattice Semiconductor Corporation + LEGACY + DDR_GENERIC + 6.0 + + + Diamond_Simulation + simulation + + ./testout.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./testout.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2019-06-05.14:55:41 + 2019-06-05.14:55:41 + 3.10.3.144 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + DDR_GENERIC + + + CoreRevision + 6.0 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 06/05/2019 + + + ModuleName + testout + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 14:55:39 + + + VendorName + Lattice Semiconductor Corporation + + + + AFreq + + + + ClkIBuf + LVDS + + + DataLane + By Lane + + + DelVal + 1 + + + Delay + Dynamic User Defined + + + Destination + Synplicity + + + DynamicAlign + + + + EDIF + 1 + + + EnDynamic + 0 + + + EnDynamicAlign + + + + EnECLK + 0 + + + EnInEdge + + + + Expression + BusA(0 to 7) + + + Freq + + + + GenPll + 0 + + + IO + 0 + + + IOBUF + + + + Interface + GDDRX1_TX.SCLK.Aligned + + + MIPIFilter + 0 + + + NumEdge + BOTH + + + Order + Big Endian [MSB:LSB] + + + ReceiverSync + 0 + + + Reference + 0 + + + VHDL + 1 + + + Verilog + 0 + + + aligned + Edge-to-Edge + + + aligned2 + Edge-to-Edge + + + bandwidth + 2560 + + + enClkIBuf + 0 + + + freq_in + 160 + + + freq_in2 + 160 + + + gear + 2:1 + + + io_type + LVDS + + + io_type2 + LVDS + + + mode + Transmit + + + mode2 + Transmit + + + pre-configuration + DISABLED + + + trioddr + 0 + + + trioddr2 + 0 + + + width + 8 + + + width2 + 8 + + + + cmd_line + -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane + + + + + + + LATTICE + LOCAL + testout + 1.0 + + + + diff --git a/vldb/cores/testout.vhd b/vldb/cores/testout.vhd new file mode 100644 index 0000000..7c1451c --- /dev/null +++ b/vldb/cores/testout.vhd @@ -0,0 +1,219 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/testout/testout.fdc + +-- Wed Jun 5 14:55:41 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity testout is + port ( + clkout: out std_logic; + refclk: in std_logic; + reset: in std_logic; + data: in std_logic_vector(15 downto 0); + data_cflag: out std_logic_vector(7 downto 0); + data_direction: in std_logic_vector(7 downto 0); + data_loadn: in std_logic_vector(7 downto 0); + data_move: in std_logic_vector(7 downto 0); + dout: out std_logic_vector(7 downto 0)); +end testout; + +architecture Structure of testout is + + -- internal signal declarations + signal db7: std_logic; + signal da7: std_logic; + signal db6: std_logic; + signal da6: std_logic; + signal db5: std_logic; + signal da5: std_logic; + signal db4: std_logic; + signal da4: std_logic; + signal db3: std_logic; + signal da3: std_logic; + signal db2: std_logic; + signal da2: std_logic; + signal db1: std_logic; + signal da1: std_logic; + signal db0: std_logic; + signal da0: std_logic; + signal scuba_vlo: std_logic; + signal scuba_vhi: std_logic; + signal sclk_t: std_logic; + signal clkos: std_logic; + signal clkop: std_logic; + signal buf_clkout: std_logic; + signal douto_t7: std_logic; + signal buf_douto7: std_logic; + signal douto_t6: std_logic; + signal buf_douto6: std_logic; + signal douto_t5: std_logic; + signal buf_douto5: std_logic; + signal douto_t4: std_logic; + signal buf_douto4: std_logic; + signal douto_t3: std_logic; + signal buf_douto3: std_logic; + signal douto_t2: std_logic; + signal buf_douto2: std_logic; + signal douto_t1: std_logic; + signal buf_douto1: std_logic; + signal douto_t0: std_logic; + signal buf_douto0: std_logic; + + attribute IO_TYPE : string; + attribute IO_TYPE of Inst2_OB : label is "LVDS"; + attribute IO_TYPE of Inst1_OB7 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB6 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB5 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB4 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB3 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB2 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB1 : label is "LVDS"; + attribute IO_TYPE of Inst1_OB0 : label is "LVDS"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + Inst4_ODDRX1F7: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da7, D1=>db7, + Q=>buf_douto7); + + Inst4_ODDRX1F6: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da6, D1=>db6, + Q=>buf_douto6); + + Inst4_ODDRX1F5: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da5, D1=>db5, + Q=>buf_douto5); + + Inst4_ODDRX1F4: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da4, D1=>db4, + Q=>buf_douto4); + + Inst4_ODDRX1F3: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da3, D1=>db3, + Q=>buf_douto3); + + Inst4_ODDRX1F2: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da2, D1=>db2, + Q=>buf_douto2); + + Inst4_ODDRX1F1: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da1, D1=>db1, + Q=>buf_douto1); + + Inst4_ODDRX1F0: ODDRX1F + port map (SCLK=>sclk_t, RST=>reset, D0=>da0, D1=>db0, + Q=>buf_douto0); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst3_ODDRX1F: ODDRX1F + port map (SCLK=>clkos, RST=>reset, D0=>scuba_vhi, D1=>scuba_vlo, + Q=>buf_clkout); + + Inst2_OB: OB + port map (I=>buf_clkout, O=>clkout); + + Inst1_OB7: OB + port map (I=>douto_t7, O=>dout(7)); + + Inst1_OB6: OB + port map (I=>douto_t6, O=>dout(6)); + + Inst1_OB5: OB + port map (I=>douto_t5, O=>dout(5)); + + Inst1_OB4: OB + port map (I=>douto_t4, O=>dout(4)); + + Inst1_OB3: OB + port map (I=>douto_t3, O=>dout(3)); + + Inst1_OB2: OB + port map (I=>douto_t2, O=>dout(2)); + + Inst1_OB1: OB + port map (I=>douto_t1, O=>dout(1)); + + Inst1_OB0: OB + port map (I=>douto_t0, O=>dout(0)); + + udel_douto7: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto7, LOADN=>data_loadn(7), + MOVE=>data_move(7), DIRECTION=>data_direction(7), + Z=>douto_t7, CFLAG=>data_cflag(7)); + + udel_douto6: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto6, LOADN=>data_loadn(6), + MOVE=>data_move(6), DIRECTION=>data_direction(6), + Z=>douto_t6, CFLAG=>data_cflag(6)); + + udel_douto5: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto5, LOADN=>data_loadn(5), + MOVE=>data_move(5), DIRECTION=>data_direction(5), + Z=>douto_t5, CFLAG=>data_cflag(5)); + + udel_douto4: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto4, LOADN=>data_loadn(4), + MOVE=>data_move(4), DIRECTION=>data_direction(4), + Z=>douto_t4, CFLAG=>data_cflag(4)); + + udel_douto3: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto3, LOADN=>data_loadn(3), + MOVE=>data_move(3), DIRECTION=>data_direction(3), + Z=>douto_t3, CFLAG=>data_cflag(3)); + + udel_douto2: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto2, LOADN=>data_loadn(2), + MOVE=>data_move(2), DIRECTION=>data_direction(2), + Z=>douto_t2, CFLAG=>data_cflag(2)); + + udel_douto1: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto1, LOADN=>data_loadn(1), + MOVE=>data_move(1), DIRECTION=>data_direction(1), + Z=>douto_t1, CFLAG=>data_cflag(1)); + + udel_douto0: DELAYF + generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED") + port map (A=>buf_douto0, LOADN=>data_loadn(0), + MOVE=>data_move(0), DIRECTION=>data_direction(0), + Z=>douto_t0, CFLAG=>data_cflag(0)); + + db7 <= data(15); + da7 <= data(14); + db6 <= data(13); + da6 <= data(12); + db5 <= data(11); + da5 <= data(10); + db4 <= data(9); + da4 <= data(8); + db3 <= data(7); + da3 <= data(6); + db2 <= data(5); + da2 <= data(4); + db1 <= data(3); + da1 <= data(2); + db0 <= data(1); + da0 <= data(0); + sclk_t <= clkop; + clkos <= refclk; + clkop <= refclk; +end Structure; diff --git a/vldb/par.p2t b/vldb/par.p2t new file mode 100644 index 0000000..f989847 --- /dev/null +++ b/vldb/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 6 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/vldb/trb5sc_vldb.lpf b/vldb/trb5sc_vldb.lpf new file mode 100644 index 0000000..1407584 --- /dev/null +++ b/vldb/trb5sc_vldb.lpf @@ -0,0 +1,49 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +BLOCK NET "THE_MIMOSIS/THE_IN/reset_i"; +BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i"; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns; + +BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*"; +BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*"; diff --git a/vldb/trb5sc_vldb.prj b/vldb/trb5sc_vldb.prj new file mode 100644 index 0000000..df0bfb1 --- /dev/null +++ b/vldb/trb5sc_vldb.prj @@ -0,0 +1,284 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mimosis" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mimosis.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + +add_file -vhdl -lib work "./cores/mimosis_inp.vhd" +add_file -vhdl -lib work "./cores/testout.vhd" +add_file -vhdl -lib work "./code/MimosisInput.vhd" +add_file -vhdl -lib work "./code/InputStage.vhd" +add_file -vhdl -lib work "./code/WordAlign.vhd" +add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" + + + + + + + + + +add_file -vhdl -lib work "./trb5sc_mimosis.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/vldb/trb5sc_vldb.vhd b/vldb/trb5sc_vldb.vhd new file mode 100644 index 0000000..55130db --- /dev/null +++ b/vldb/trb5sc_vldb.vhd @@ -0,0 +1,778 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn + --FE_GPIO : inout std_logic_vector(11 downto 0); + --FE_CLK : out std_logic_vector( 2 downto 1); + --FE_DIFF : inout std_logic_vector(63 downto 0); + --INP : inout std_logic_vector(63 downto 0); + --LED_ADDON : out std_logic_vector(5 downto 0); + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(4 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --GBTSCA + SCA_RX : in std_logic(1 downto 0); + SCA_TX : out std_logic(1 downto 0); + SCA_CLK : out std_logic(1 downto 0); + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + + +architecture arch of trb5sc_mimosis is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtsca_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtsca_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal out_data : std_logic_vector(15 downto 0); + signal out_i : std_logic_vector( 7 downto 0); + signal inp_i : std_logic_vector( 7 downto 0); + signal gbe_status : std_logic_vector(15 downto 0); + + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); + + --signal fwd_dst_mac : std_logic_vector(47 downto 0); + --signal fwd_dst_ip : std_logic_vector(31 downto 0); + --signal fwd_dst_port : std_logic_vector(15 downto 0); + --signal fwd_data : std_logic_vector(7 downto 0); + --signal fwd_datavalid : std_logic; + --signal fwd_sop : std_logic; + --signal fwd_eop : std_logic; + --signal fwd_ready : std_logic; + --signal fwd_full : std_logic; + --signal fwd_length : std_logic_vector(15 downto 0); + --signal fwd_do_send : std_logic; + + -- -- GBTSCA + -- -- Clock & reset + -- signal gbtsc_tx_clk_i : in std_logic; --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency + -- signal gbtsc_tx_clk_en : in std_logic := '1'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled + -- signal gbtsc_rx_clk_i : in std_logic; --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency + -- signal gbtsc_rx_clk_en : in std_logic := '1'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled + -- signal gbtsc_rx_reset_i : in std_logic; --! Reset RX datapath + -- signal gbtsc_tx_reset_i : in std_logic; --! Reset TX datapath + -- -- IC control + -- signal gbtsc_tx_start_write_i : in std_logic; --! Request a write config. to the GBTx (IC) + -- signal gbtsc_tx_start_read_i : in std_logic; --! Request a read config. to the GBTx (IC) + -- -- IC configuration + -- signal gbtsc_tx_GBTx_address_i : in std_logic_vector(7 downto 0); --! I2C address of the GBTx + -- signal gbtsc_tx_register_addr_i : in std_logic_vector(15 downto 0); --! Address of the first register to be accessed + -- signal gbtsc_tx_nb_to_be_read_i : in std_logic_vector(15 downto 0); --! Number of words/bytes to be read (only for read transactions) + -- -- IC FIFO control + -- signal gbtsc_wr_clk_i : in std_logic; --! Fifo's writing clock + -- signal gbtsc_tx_wr_i : in std_logic; --! Request a write operation into the internal FIFO (Data to GBTx) + -- signal gbtsc_tx_data_to_gbtx_i : in std_logic_vector(7 downto 0); --! Data to be written into the internal FIFO + -- signal gbtsc_rd_clk_i : in std_logic; + -- signal gbtsc_rx_rd_i : in std_logic; --! Request a read operation of the internal FIFO (GBTx reply) + -- signal gbtsc_rx_data_from_gbtx_o : out std_logic_vector(7 downto 0); --! Data from the FIFO + -- -- IC Status + -- signal gbtsc_tx_ready_o : out std_logic; --! IC core ready for a transaction + -- signal gbtsc_rx_empty_o : out std_logic; --! Rx FIFO is empty (no reply from GBTx) + -- -- SCA control + -- signal gbtsc_sca_enable_i : in std_logic_vector((g_SCA_COUNT-1) downto 0); --! Enable flag to select SCAs + -- signal gbtsc_start_reset_cmd_i : in std_logic; --! Send a reset command to the enabled SCAs + -- signal gbtsc_start_connect_cmd_i : in std_logic; --! Send a connect command to the enabled SCAs + -- signal gbtsc_start_command_i : in std_logic; --! Send the command set in input to the enabled SCAs + -- signal gbtsc_inject_crc_error : in std_logic; --! Emulate a CRC error + -- -- SCA command + -- signal gbtsc_tx_address_i : in std_logic_vector(7 downto 0); --! Command: address field (According to the SCA manual) + -- signal gbtsc_tx_transID_i : in std_logic_vector(7 downto 0); --! Command: transaction ID field (According to the SCA manual) + -- signal gbtsc_tx_channel_i : in std_logic_vector(7 downto 0); --! Command: channel field (According to the SCA manual) + -- signal gbtsc_tx_command_i : in std_logic_vector(7 downto 0); --! Command: command field (According to the SCA manual) + -- signal gbtsc_tx_data_i : in std_logic_vector(31 downto 0); --! Command: data field (According to the SCA manual) + -- signal gbtsc_rx_received_o : out std_logic_vector((g_SCA_COUNT-1) downto 0); --! Reply received flag (pulse) + -- signal gbtsc_rx_address_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: address field (According to the SCA manual) + -- signal gbtsc_rx_control_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: control field (According to the SCA manual) + -- signal gbtsc_rx_transID_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: transaction ID field (According to the SCA manual) + -- signal gbtsc_rx_channel_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: channel field (According to the SCA manual) + -- signal gbtsc_rx_len_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: len field (According to the SCA manual) + -- signal gbtsc_rx_error_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: error field (According to the SCA manual) + -- signal gbtsc_rx_data_o : out reg32_arr((g_SCA_COUNT-1) downto 0); --! Reply: data field (According to the SCA manual) + -- -- EC line + -- signal gbtsc_ec_data_o : out reg2_arr((g_SCA_COUNT-1) downto 0); --! (TX) Array of bits to be mapped to the TX GBT-Frame + -- signal gbtsc_ec_data_i : in reg2_arr((g_SCA_COUNT-1) downto 0); --! (RX) Array of bits to be mapped to the RX GBT-Frame + -- -- IC lines + -- signal gbtsc_ic_data_o : out std_logic_vector(1 downto 0); --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84) + -- signal gbtsc_ic_data_i : in std_logic_vector(1 downto 0) --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84) + + + -- GBT-SCA + variable g_SCA_COUNT : integer := 1; + signal sca_clk : std_logic; --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency + signal sca_reset_i : std_logic := '0'; --! Reset RX datapath + + signal sca_enable_i : std_logic := '0'; --! Enable flag, bit position correspond to the SCA ID ('1': enabled / '0': Disabled) + signal sca_start_reset_cmd_i : std_logic; --! Send a reset command to the enabled SCAs + signal sca_start_connect_cmd_i : std_logic; --! Send a connect command to the enabled SCAs + signal sca_start_command_i : std_logic; --! Send the command set in input to the enabled SCAs + + signal sca_tx_address_i : std_logic_vector(7 downto 0); --! Command: address field (According to the SCA manual) + signal sca_tx_transID_i : std_logic_vector(7 downto 0); --! Command: transaction ID field (According to the SCA manual) + signal sca_tx_channel_i : std_logic_vector(7 downto 0); --! Command: channel field (According to the SCA manual) + signal sca_tx_len_i : std_logic_vector(7 downto 0); --! Command: Len field (not used anymore, fixed to 4 bytes) + signal sca_tx_command_i : std_logic_vector(7 downto 0); --! Command: command field (According to the SCA manual) + signal sca_tx_data_i : std_logic_vector(31 downto 0); --! Command: data field (According to the SCA manual) + + signal sca_rx_received_o : std_logic; --! Reply received flag (pulse), bit position correspond to the SCA ID + signal sca_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual) + signal sca_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual) + signal sca_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual) + signal sca_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual) + signal sca_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual) + signal sca_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual) + signal sca_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual) + + signal sca_out : std_logic_vector(1 downto 0); --! (TX) Array of 2 bits to be mapped to the TX GBT-Frame + signal sca_in : std_logic_vector(1 downto 0); --! (RX) Array of 2 bits to be mapped to the RX GBT-Frame + + signal shiftreg2 : std_logic_vector(1 downto 0) := "00"; + +begin + + +trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + +THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40 + ); + +H5(3) <= clk_320; +RJ(0) <= clk_40; + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + USE_NEW_ECP5_RESET => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => BROADCAST_BITMASK, + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16, + USE_GBE => USE_GBE + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_125 => CLK_125, + CLEAR_N => GSR_N, + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer, + STATUS_GBE_OUT=> gbe_status + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busmimosis_rx, + BUS_RX(4) => busgbtsca_rx, + -- BUS_RX(4) => busi2c_rx, + -- BUS_RX(5) => busgbeip_rx, + -- BUS_RX(6) => busgbereg_rx, + -- BUS_RX(7) => busfwd_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busmimosis_tx, + BUS_TX(4) => busgbtsca_tx, + -- BUS_TX(4) => busi2c_tx, + -- BUS_TX(5) => busgbeip_tx, + -- BUS_TX(6) => busgbereg_tx, + -- BUS_TX(7) => busfwd_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + HEADER_IO(7) => HDR_IO(6), + HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + +--counter <= counter + '1' when rising_edge(clk_sys); +--HDR_IO <= std_logic_vector(counter(15 downto 0)); +--LED <= std_logic_vector(counter(23 downto 16)); + + --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; + --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- GBT-SCA +--------------------------------------------------------------------------- +-- THE_GBTSCA : entity work.gbtsc_top +-- generic map( +-- -- IC configuration +-- -- g_IC_FIFO_DEPTH => , -- : integer := 20; --! Defines the depth of the FIFO used to handle the Internal control (Max. number of words/bytes can be read/write from/to a GBTx) +-- -- g_ToLpGBT => , -- : integer range 0 to 1 := 0; --! 1 to use LpGBT. Otherwise, it should be 0 +-- -- g_LPGBT_VERS => , -- : std_logic := '1'; --! Select lpGBT version ('0': 0, '1': 1) + +-- -- EC configuration +-- g_SCA_COUNT => 1, -- : integer := 1 --! Defines the maximum number of SCA that can be connected to this module +-- ) +-- port map( +-- -- Clock & reset +-- tx_clk_i => gbtsc_tx_clk_i, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency +-- tx_clk_en => gbtsc_tx_clk_e, --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled + +-- rx_clk_i => gbtsc_rx_clk_i, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency +-- rx_clk_en => gbtsc_rx_clk_e, --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled + +-- rx_reset_i => gbtsc_rx_reset_i, --! Reset RX datapath +-- tx_reset_i => gbtsc_tx_reset_i, --! Reset TX datapath + +-- -- IC control +-- tx_start_write_i => gbtsc_tx_start_write_i, --! Request a write config. to the GBTx (IC) +-- tx_start_read_i => gbtsc_tx_start_read_i, --! Request a read config. to the GBTx (IC) + +-- -- IC configuration +-- tx_GBTx_address_i => gbtsc_tx_GBTx_address_i, --! I2C address of the GBTx +-- tx_register_addr_i => gbtsc_tx_register_addr_i, --! Address of the first register to be accessed +-- tx_nb_to_be_read_i => gbtsc_tx_nb_to_be_read_i, --! Number of words/bytes to be read (only for read transactions) + +-- -- IC FIFO control +-- wr_clk_i => gbtsc_wr_clk_i, --! Fifo's writing clock +-- tx_wr_i => gbtsc_tx_wr_i, --! Request a write operation into the internal FIFO (Data to GBTx) +-- tx_data_to_gbtx_i => gbtsc_tx_data_to_gbtx_i, --! Data to be written into the internal FIFO + +-- rd_clk_i => gbtsc_rd_clk_i, -- +-- rx_rd_i => gbtsc_rx_rd_i, --! Request a read operation of the internal FIFO (GBTx reply) +-- rx_data_from_gbtx_o => gbtsc_rx_data_from_gbtx_o, --! Data from the FIFO + +-- -- IC Status +-- tx_ready_o => gbtsc_tx_ready_o, --! IC core ready for a transaction +-- rx_empty_o => gbtsc_rx_empty_o, --! Rx FIFO is empty (no reply from GBTx) + +-- -- SCA control +-- sca_enable_i => gbtsc_sca_enable_i, --! Enable flag to select SCAs +-- start_reset_cmd_i => gbtsc_start_reset_cmd_i, --! Send a reset command to the enabled SCAs +-- start_connect_cmd_i => gbtsc_start_connect_cmd_i, --! Send a connect command to the enabled SCAs +-- start_command_i => gbtsc_start_command_i, --! Send the command set in input to the enabled SCAs +-- inject_crc_error => gbtsc_inject_crc_e, --! Emulate a CRC error + +-- -- SCA command +-- tx_address_i => gbtsc_tx_address_i, --! Command: address field (According to the SCA manual) +-- tx_transID_i => gbtsc_tx_transID_i, --! Command: transaction ID field (According to the SCA manual) +-- tx_channel_i => gbtsc_tx_channel_i, --! Command: channel field (According to the SCA manual) +-- tx_command_i => gbtsc_tx_command_i, --! Command: command field (According to the SCA manual) +-- tx_data_i => gbtsc_tx_data_i, --! Command: data field (According to the SCA manual) + +-- rx_received_o => gbtsc_rx_received_o, --! Reply received flag (pulse) +-- rx_address_o => gbtsc_rx_address_o, --! Reply: address field (According to the SCA manual) +-- rx_control_o => gbtsc_rx_control_o, --! Reply: control field (According to the SCA manual) +-- rx_transID_o => gbtsc_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual) +-- rx_channel_o => gbtsc_rx_channel_o, --! Reply: channel field (According to the SCA manual) +-- rx_len_o => gbtsc_rx_len_o, --! Reply: len field (According to the SCA manual) +-- rx_error_o => gbtsc_rx_error_o, --! Reply: error field (According to the SCA manual) +-- rx_data_o => gbtsc_rx_data_o, --! Reply: data field (According to the SCA manual) + +-- -- EC line +-- ec_data_o => gbtsc_ec_data_o, --! (TX) Array of bits to be mapped to the TX GBT-Frame +-- ec_data_i => gbtsc_ec_data_i, --! (RX) Array of bits to be mapped to the RX GBT-Frame + +-- -- IC lines +-- ic_data_o => open, --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84) +-- ic_data_i => "00" --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84) +-- ); + + +PROC_GEN_CLK80 : process begin + wait until rising_edge(clk_160); + sca_clk <= shiftreg2(1); + shiftreg2 = shiftreg2 + 1; +end process + +THE_GBTSCA : entity work.sca_top + generic map( + g_SCA_COUNT => g_SCA_COUNT, --! Number of SCAs to be controlled through the link (up to 41) + ) + port map( + rx_clk_en => '1', --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled + tx_clk_en => '1', --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled + + rx_clk_i => sca_clk, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency + tx_clk_i => sca_clk, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency + + rx_reset_i => sca_reset_i, --! Reset RX datapath + tx_reset_i => sca_reset_i, --! Reset TX datapath + + enable_i(0) => sca_enable_i, --! Enable flag, bit position correspond to the SCA ID ('1': enabled / '0': Disabled) + start_reset_cmd_i => sca_start_reset_cmd_i, --! Send a reset command to the enabled SCAs + start_connect_cmd_i => sca_start_connect_cmd_i, --! Send a connect command to the enabled SCAs + start_command_i => sca_start_command_i, --! Send the command set in input to the enabled SCAs + inject_crc_error => '0', --! Emulate a CRC error + + tx_address_i => sca_tx_address_i, --! Command: address field (According to the SCA manual) + tx_transID_i => sca_tx_transID_i, --! Command: transaction ID field (According to the SCA manual) + tx_channel_i => sca_tx_channel_i, --! Command: channel field (According to the SCA manual) + tx_len_i => sca_tx_len_i, --! Command: Len field (not used anymore, fixed to 4 bytes) + tx_command_i => sca_tx_command_i, --! Command: command field (According to the SCA manual) + tx_data_i => sca_tx_data_i, --! Command: data field (According to the SCA manual) + + rx_received_o(0) => sca_rx_received_o, --! Reply received flag (pulse), bit position correspond to the SCA ID + rx_address_o(0) => sca_rx_address_o, --! Reply: address field (According to the SCA manual) + rx_control_o(0) => sca_rx_control_o, --! Reply: control field (According to the SCA manual) + rx_transID_o(0) => sca_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual) + rx_channel_o(0) => sca_rx_channel_o, --! Reply: channel field (According to the SCA manual) + rx_len_o(0) => sca_rx_len_o, --! Reply: len field (According to the SCA manual) + rx_error_o(0) => sca_rx_error_o, --! Reply: error field (According to the SCA manual) + rx_data_o(0) => sca_rx_data_o, --! Reply: data field (According to the SCA manual) + + tx_data_o(0) => sca_out, --! (TX) Array of 2 bits to be mapped to the TX GBT-Frame + rx_data_i(0) => sca_in, --! (RX) Array of 2 bits to be mapped to the RX GBT-Frame + ); + + +PROC_GBTSCA_REGS : process begin + wait until rising_edge(CLK_SYS); + busgbtsca_tx.ack <= '0'; + busgbtsca_tx.unknown <= '0'; + busgbtsca_tx.nack <= '0'; + busgbtsca_tx.data <= (others => '0'); + sca_enable_i <= '0'; + sca_reset_i <= '0'; + + if busgbtsca_rx.write = '1' then + busgbtsca_tx.ack <= '1'; + if busgbtsca_rx.addr(3 downto 0) = x"0" then + sca_tx_address_i <= busgbtsca_rx.data(7 downto 0); + sca_enable_i <= busgbtsca_rx.data(8); + sca_start_reset_cmd_i <= busgbtsca_rx.data(9); + sca_start_connect_i <= busgbtsca_rx.data(10); + sca_reset_i <= busgbtsca_rx.data(11); + elsif busgbtsca_rx.addr(3 downto 0) = x"1" then + sca_tx_transID_i <= busgbtsca_rx.data(7 downto 0); + sca_tx_channel_i <= busgbtsca_rx.data(15 downto 8); + sca_tx_len_i <= busgbtsca_rx.data(23 downto 16); + sca_tx_command_i <= busgbtsca_rx.data(31 downto 24); + elsif busgbtsca_rx.addr(3 downto 0) = x"2" then + sca_tx_data_i <= busgbtsca_rx.data(31 downto 0); + else + busgbtsca_tx.ack <= '0'; + busgbtsca_tx.unknown <= '1'; + end if; + + elsif busgbtsca_rx.read = '1' then + busgbtsca_tx.ack <= '1'; + if busgbtsca_rx.addr(3 downto 0) = x"0" then + busgbtsca_tx.data(7 downto 0) <= sca_rx_address_o; + elsif busgbtsca_rx.addr(3 downto 0) = x"1" then + busgbtsca_tx.data( 7 downto 0 ) <= sca_rx_transID_o; + busgbtsca_tx.data(15 downto 8 ) <= sca_rx_channel_o; + busgbtsca_tx.data(23 downto 16) <= sca_rx_len_o; + -- busgbtsca_tx.data(31 downto 24) <= sca_rx_len_o; + elsif busgbtsca_rx.addr(3 downto 0) = x"2" then + busgbtsca_tx.data(31 downto 0) <= sca_rx_data_o; + elsif busgbtsca_rx.addr(3 downto 0) = x"3" then + busgbtsca_tx.data(7 downto 0) <= sca_rx_control_o; + busgbtsca_tx.data(15 downto 8) <= sca_rx_error_o; + busgbtsca_tx.data(16) <= sca_rx_received_o; + else + busgbtsca_tx.ack <= '0'; + busgbtsca_tx.unknown <= '1'; + end if; + end if; +end process; + +sca_in <= SCA_RX; +SCA_TX <= sca_out; +SCA_CLK <= sca_clk & not sca_clk; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9); + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + + LED_ADDON_RJ <= "00"; + LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2)); + LED_ADDON_SFP_GREEN(1) <= '0'; + LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); + LED_ADDON_SFP_ORANGE(1) <= '0'; + + +--------------------------------------------------------------------------- +-- Output stage +--------------------------------------------------------------------------- + THE_OUT : entity work.testout + port map( + clkout => open, + refclk => clk_160, + reset => reset_i, + data => out_data, + data_cflag => open, + data_direction => (others => '0'), + data_loadn => (others => '1'), + data_move => (others => '0'), + dout => out_i + ); + + PROC_OUT : process + variable cnt : integer range 0 to 7; + begin + wait until rising_edge(clk_160); + cnt := cnt + 1; + case cnt is + when 0 => out_data <= x"ffff"; + when 1 => out_data <= x"ffff"; + when 2 => out_data <= x"ffff"; + when 3 => out_data <= x"0000"; + when 4 => out_data <= x"5555"; + when 5 => out_data <= x"5555"; + when 6 => out_data <= x"5555"; + when 7 => out_data <= x"5555"; + end case; + end process; + + H3(3 downto 0) <= out_i(3 downto 0); + H4(3 downto 0) <= out_i(7 downto 4); + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + THE_MIMOSIS : entity work.MimosisInput + port map( + CLK => clk_160, + CLK_SYS => clk_sys, + RESET => reset_i, + + INPUT => inp_i, + + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + + BUS_RX => busmimosis_rx, + BUS_TX => busmimosis_tx + ); + +-- inp_i <= H2(3 downto 0) & H1(3 downto 0); + inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +SFP_ADDON_TX_DIS <= (others => '0'); +end architecture; diff --git a/vldb/trb5sc_vldb_OLD.vhd b/vldb/trb5sc_vldb_OLD.vhd new file mode 100644 index 0000000..abac92e --- /dev/null +++ b/vldb/trb5sc_vldb_OLD.vhd @@ -0,0 +1,759 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn +-- FE_GPIO : inout std_logic_vector(11 downto 0); +-- FE_CLK : out std_logic_vector( 2 downto 1); +-- FE_DIFF : inout std_logic_vector(63 downto 0); + --INP : inout std_logic_vector(63 downto 0); + --LED_ADDON : out std_logic_vector(5 downto 0); + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(4 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_mimosis is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal out_data : std_logic_vector(15 downto 0); + signal out_i : std_logic_vector( 7 downto 0); + signal inp_i : std_logic_vector( 7 downto 0); + signal gbe_status : std_logic_vector(15 downto 0); + + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); + --signal fwd_dst_mac : std_logic_vector(47 downto 0); + --signal fwd_dst_ip : std_logic_vector(31 downto 0); + --signal fwd_dst_port : std_logic_vector(15 downto 0); + --signal fwd_data : std_logic_vector(7 downto 0); + --signal fwd_datavalid : std_logic; + --signal fwd_sop : std_logic; + --signal fwd_eop : std_logic; + --signal fwd_ready : std_logic; + --signal fwd_full : std_logic; + --signal fwd_length : std_logic_vector(15 downto 0); + --signal fwd_do_send : std_logic; + +begin + + +trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + +THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40 + ); + +H5(3) <= clk_320; +RJ(0) <= clk_40; + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + USE_NEW_ECP5_RESET => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => BROADCAST_BITMASK, + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16, + USE_GBE => USE_GBE + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_125 => CLK_125, + CLEAR_N => GSR_N, + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer, + STATUS_GBE_OUT=> gbe_status + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busmimosis_rx, + BUS_RX(4) => busi2c_rx, + --BUS_RX(5) => busgbeip_rx, + --BUS_RX(6) => busgbereg_rx, + --BUS_RX(7) => busfwd_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busmimosis_tx, + BUS_TX(4) => busi2c_tx, + --BUS_TX(5) => busgbeip_tx, + --BUS_TX(6) => busgbereg_tx, + --BUS_TX(7) => busfwd_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + HEADER_IO(7) => HDR_IO(6), + HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + +--counter <= counter + '1' when rising_edge(clk_sys); +--HDR_IO <= std_logic_vector(counter(15 downto 0)); +--LED <= std_logic_vector(counter(23 downto 16)); + + --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; + --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + +--------------------------------------------------------------------------- +-- I2C +--------------------------------------------------------------------------- +THE_I2C : entity work.i2c_slim2 + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + DIRECT_IN => i2c_reg_1(4), -- don't send command + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(27 downto 24) +); + +-- I2C signal open collector driver +-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; + +PIN(4) <= MIMOSIS_SDA; +PIN(3) <= MIMOSIS_SCL; +MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z'; +MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z'; + +H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC +PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START +PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + +PROC_I2C_REGS : process begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + + end if; + end if; +end process; + + THE_I2C_GO_SYNC : pulse_sync + port map( + CLK_A_IN => clk_sys, + RESET_A_IN => reset_i, + PULSE_A_IN => i2c_go_100, + CLK_B_IN => clk_40, + RESET_B_IN => reset_i, + PULSE_B_OUT => i2c_go + ); + + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); + + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9); + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + + LED_ADDON_RJ <= "00"; + LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2)); + LED_ADDON_SFP_GREEN(1) <= '0'; + LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); + LED_ADDON_SFP_ORANGE(1) <= '0'; + +----------------------------------------------------------------------------- +---- GbE +----------------------------------------------------------------------------- + --GBE : entity work.gbe_wrapper + --generic map( + --DO_SIMULATION => 0, + --INCLUDE_DEBUG => 0, + --USE_INTERNAL_TRBNET_DUMMY => 0, + --USE_EXTERNAL_TRBNET_DUMMY => 0, + --RX_PATH_ENABLE => 1, + --FIXED_SIZE_MODE => 1, + --INCREMENTAL_MODE => 1, + --FIXED_SIZE => 100, + --FIXED_DELAY_MODE => 1, + --UP_DOWN_MODE => 0, + --UP_DOWN_LIMIT => 100, + --FIXED_DELAY => 100, + + --NUMBER_OF_GBE_LINKS => 1, + --LINKS_ACTIVE => "0001", + + --LINK_HAS_READOUT => "0000", + --LINK_HAS_SLOWCTRL => "0000", + --LINK_HAS_DHCP => "0001", + --LINK_HAS_ARP => "0001", + --LINK_HAS_PING => "0001", + --LINK_HAS_FWD => "0001" + --) + --port map( + --CLK_SYS_IN => clk_sys, + --CLK_125_IN => CLK_125, + --RESET => reset_i, + --GSR_N => GSR_N, + ---- Trigger + --TRIGGER_IN => '0', + ---- SFP + --SD_PRSNT_N_IN(0) => SFP_MOD_0, + --SD_LOS_IN(0) => SFP_LOS, + --SD_TXDIS_OUT(0) => SFP_TX_DIS, + ---- trigger channel + ---- only for LINK_HAS_READOUT + --CTS_NUMBER_IN => (others => '0'), + --CTS_CODE_IN => (others => '0'), + --CTS_INFORMATION_IN => (others => '0'), + --CTS_READOUT_TYPE_IN => (others => '0'), + --CTS_START_READOUT_IN => '0', + --CTS_DATA_OUT => open, + --CTS_DATAREADY_OUT => open, + --CTS_READOUT_FINISHED_OUT => open, + --CTS_READ_IN => '1', + --CTS_LENGTH_OUT => open, + --CTS_ERROR_PATTERN_OUT => open, + ---- data channel + ---- only for LINK_HAS_READOUT + --FEE_DATA_IN => (others => '0'), + --FEE_DATAREADY_IN => '0', + --FEE_READ_OUT => open, + --FEE_STATUS_BITS_IN => (others => '0'), + --FEE_BUSY_IN => '0', + ---- unique adresses + --MC_UNIQUE_ID_IN => timer.uid, + --MY_TRBNET_ADDRESS_IN => timer.network_address, + --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected + ---- slow control by GbE + --GSC_CLK_IN => open, + --GSC_INIT_DATAREADY_OUT => open, + --GSC_INIT_DATA_OUT => open, + --GSC_INIT_PACKET_NUM_OUT => open, + --GSC_INIT_READ_IN => '1', + --GSC_REPLY_DATAREADY_IN => '0', + --GSC_REPLY_DATA_IN => (others => '0'), + --GSC_REPLY_PACKET_NUM_IN => (others => '0'), + --GSC_REPLY_READ_OUT => open, + --GSC_BUSY_IN => '0', + ---- readout + --BUS_IP_RX => busgbeip_rx, -- registers inside GbE + --BUS_IP_TX => busgbeip_tx, -- registers inside GbE + --BUS_REG_RX => busgbereg_rx, -- registers inside GbE + --BUS_REG_TX => busgbereg_tx, -- registers inside GbE + ---- Forwarder + --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac, + --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip, + --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port, + --FWD_DATA_IN(7 downto 0) => fwd_data, + --FWD_DATA_VALID_IN(0) => fwd_datavalid, + --FWD_SOP_IN(0) => fwd_sop, + --FWD_EOP_IN(0) => fwd_eop, + --FWD_READY_OUT(0) => fwd_ready, + --FWD_FULL_OUT(0) => fwd_full, + ---- reset + --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected + ---- debug and status + --STATUS_OUT => open, + --DEBUG_OUT => open + --); + + + +----------------------------------------------------------------------------- +---- Test registers +----------------------------------------------------------------------------- +--THE_REGS : process begin + --wait until rising_edge(clk_sys); + --busfwd_tx.ack <= '0'; + --busfwd_tx.nack <= '0'; + --busfwd_tx.unknown <= '0'; + + --if busfwd_rx.write = '1' then + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => fwd_dst_ip <= busfwd_rx.data; + --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0); + --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data; + --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0); + --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0); + --when x"05" => fwd_do_send <= busfwd_rx.data(0); + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; + --elsif busfwd_rx.read = '1' then + --busfwd_tx.ack <= '1'; + --case busfwd_rx.addr(7 downto 0) is + --when x"00" => busfwd_tx.data <= fwd_dst_ip; + --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port; + --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0); + --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32); + --when x"04" => busfwd_tx.data <= x"0000" & fwd_length; + --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send; + --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1'; + --end case; + --end if; + --if reset_i = '1' then + --fwd_do_send <= '0'; + --end if; +--end process; + + +--------------------------------------------------------------------------- +-- Output stage +--------------------------------------------------------------------------- + THE_OUT : entity work.testout + port map( + clkout => open, + refclk => clk_160, + reset => reset_i, + data => out_data, + data_cflag => open, + data_direction => (others => '0'), + data_loadn => (others => '1'), + data_move => (others => '0'), + dout => out_i + ); + + PROC_OUT : process + variable cnt : integer range 0 to 7; + begin + wait until rising_edge(clk_160); + cnt := cnt + 1; + case cnt is + when 0 => out_data <= x"ffff"; + when 1 => out_data <= x"ffff"; + when 2 => out_data <= x"ffff"; + when 3 => out_data <= x"0000"; + when 4 => out_data <= x"5555"; + when 5 => out_data <= x"5555"; + when 6 => out_data <= x"5555"; + when 7 => out_data <= x"5555"; + end case; + end process; + + H3(3 downto 0) <= out_i(3 downto 0); + H4(3 downto 0) <= out_i(7 downto 4); + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + THE_MIMOSIS : entity work.MimosisInput + port map( + CLK => clk_160, + CLK_SYS => clk_sys, + RESET => reset_i, + + INPUT => inp_i, + + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + + BUS_RX => busmimosis_rx, + BUS_TX => busmimosis_tx + ); + +-- inp_i <= H2(3 downto 0) & H1(3 downto 0); + inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +SFP_ADDON_TX_DIS <= (others => '0'); +end architecture; + + + -- 2.43.0