From 5b73c0e18394340c28c42dfaa42a40c01ddff206 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 25 Apr 2013 15:52:18 +0200 Subject: [PATCH] added switch for padiwa flavours --- base/trb3_components.vhd | 2 +- wasa/panda_dirc_wasa.prj | 2 +- wasa/panda_dirc_wasa.vhd | 9 +++++---- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 97c63da..741d307 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -526,7 +526,7 @@ package trb3_components is generic( SERDES_NUM : integer range 0 to 3 := 0; -- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO - IS_SYNC_SLAVE : integer := c_NO --select slave mode + IS_SYNC_SLAVE : integer := 0 --select slave mode ); port( CLK : in std_logic; -- _internal_ 200 MHz reference clock diff --git a/wasa/panda_dirc_wasa.prj b/wasa/panda_dirc_wasa.prj index c3c97dc..d5444e6 100644 --- a/wasa/panda_dirc_wasa.prj +++ b/wasa/panda_dirc_wasa.prj @@ -6,8 +6,8 @@ #project files add_file -vhdl -lib work "/d/jspc29/lattice/diamond/1.4.2.105/cae_library/synthesis/vhdl/machxo2.vhd" -add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/base/trb3_components.vhd" add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/base/trb3_components.vhd" add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_components.vhd" add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd" add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd" diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd index 319ef8f..a1a94f0 100644 --- a/wasa/panda_dirc_wasa.vhd +++ b/wasa/panda_dirc_wasa.vhd @@ -14,7 +14,7 @@ use machxo2.all; entity panda_dirc_wasa is generic( - NORMAL_ORDER : integer := 0 + PADIWA_FLAVOUR : integer := 2 ); port( CON : out std_logic_vector(16 downto 1); @@ -261,12 +261,13 @@ clk_source: OSCH --------------------------------------------------------------------------- -- Input re-ordering --------------------------------------------------------------------------- -gen_outputs_1 : if NORMAL_ORDER = 1 generate +gen_outputs_1 : if PADIWA_FLAVOUR = 2 generate INP_i <= INP; PWM <= pwm_i(15 downto 0); end generate; -gen_outputs_2 : if NORMAL_ORDER = 0 generate + +gen_outputs_2 : if PADIWA_FLAVOUR = 1 generate INP_i <= INP(16) & INP(8) & INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & INP(12) & INP(4) & INP(11) & INP(3) & INP(10) & INP(2) & INP(9) & INP(1); PWM <= pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & pwm_i(12) & pwm_i(4) & @@ -506,7 +507,7 @@ THE_IO_REG_READ : process begin case spi_channel_i(3 downto 0) is when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); - when x"2" => spi_reg20_i <= x"000" & "000" & std_logic_vector(to_unsigned(NORMAL_ORDER,1)); + when x"2" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(PADIWA_FLAVOUR,4)); when others => null; end case; end if; -- 2.43.0