From 5c4fd2677459ee2a23f6884616933ca7d6f05163 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 20 Nov 2007 13:32:14 +0000 Subject: [PATCH] first working hub version, Jan --- testbench/trb_net16_dummy_apl.vhd | 14 +- trb_net16_hub_base.vhd | 56 ++- trb_net16_hub_logic.vhd | 797 +++++++++++++++++++++++------- trb_net16_io_multiplexer.vhd | 34 +- trb_net16_iobuf.vhd | 8 +- trb_net_priority_arbiter.vhd | 6 - xilinx/trb_net16_bram_fifo.vhd | 3 +- 7 files changed, 679 insertions(+), 239 deletions(-) diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd index 2aa45e5..7906db3 100644 --- a/testbench/trb_net16_dummy_apl.vhd +++ b/testbench/trb_net16_dummy_apl.vhd @@ -94,9 +94,7 @@ begin next_state <= RUNNING; next_APL_SEND_OUT <= '0'; else - if buf_APL_SEND_OUT = '1' or APL_RUN_IN = '0' then - next_APL_SEND_OUT <= '1'; - end if; + next_APL_SEND_OUT <= buf_APL_SEND_OUT; next_state <= WRITING; next_APL_DATA_OUT <= (1 => '1', others => '0'); next_APL_WRITE_OUT <= '1'; @@ -106,6 +104,7 @@ begin -- WRITING ------------------------------------------------------------------------- elsif current_state = WRITING then + next_APL_SEND_OUT <= '1'; next_state <= WRITING; if packet_counter = "01" then next_APL_WRITE_OUT <= '1'; @@ -115,9 +114,8 @@ begin next_APL_WRITE_OUT <= '1'; next_APL_DATA_OUT <= reg_counter; next_packet_counter <= "11"; - elsif packet_counter <= "11" then + elsif packet_counter = "11" then next_state <= IDLE; - next_packet_counter <= "01"; next_counter <= reg_counter +1; end if; ----------------------------------------------------------------------- @@ -144,9 +142,7 @@ begin next_counter <= (others => '0'); end if; end if; -- end state switch - if RESET = '1' then - next_APL_WRITE_OUT <= '0'; - end if; + end process; APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT; @@ -160,7 +156,7 @@ APL_WRITE_OUT <= buf_APL_WRITE_OUT; if RESET = '1' then current_state <= IDLE; reg_counter <= (others => '0'); - packet_counter <= "01"; + packet_counter <= "00"; buf_APL_DATA_OUT <= (others => '0'); buf_APL_PACKET_NUM_OUT <= "00"; buf_APL_WRITE_OUT <= '0'; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 27235f2..e59541c 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -1,6 +1,5 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; USE IEEE.numeric_std.ALL; @@ -17,8 +16,8 @@ entity trb_net16_hub_base is NUM_WIDTH : integer range 2 to 2 := 2; --media interfaces MII_NUMBER : integer range 2 to 16 := 2; - MII_INIT_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; - MII_REPLY_DEPTH : bit_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; + MII_INIT_DEPTH : std_logic_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; + MII_REPLY_DEPTH : std_logic_vector(MII_NUMBER*2**(MUX_WIDTH-1)*4-1 downto 0) := x"66110000"; -- settings for apis API_NUMBER : integer range 0 to 16 := 1; API_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"3"; @@ -29,8 +28,8 @@ entity trb_net16_hub_base is API_FIFO_TO_INT_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; API_FIFO_TO_APL_DEPTH : bit_vector(API_NUMBER*4-1 downto 0) := x"1"; --trigger reading interfaces - TRG_NUMBER : integer range 0 to 16 := 2; - TRG_CHANNELS : bit_vector(API_NUMBER*4-1 downto 0) := x"10" + TRG_NUMBER : integer range 0 to 16 := 1; + TRG_CHANNELS : bit_vector(TRG_NUMBER*4-1 downto 0) := x"0" ); port ( CLK : in std_logic; @@ -39,15 +38,15 @@ entity trb_net16_hub_base is --Media interfacces --each port is one bit bigger than actually necessary to avoid error messages - MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); - MED_READ_IN : in std_logic_vector (MII_NUMBER downto 0); - MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH downto 0); - MED_READ_OUT : out std_logic_vector (MII_NUMBER downto 0); -- buffer reads a word from media - MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3 downto 0); + MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER+1 downto 0); + MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH+1 downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH+1 downto 0); + MED_READ_IN : in std_logic_vector (MII_NUMBER+1 downto 0); + MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER+1 downto 0); + MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH+1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH+1 downto 0); + MED_READ_OUT : out std_logic_vector (MII_NUMBER+1 downto 0); -- buffer reads a word from media + MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3+1 downto 0); --API: interfaces APL_DATA_IN : in std_logic_vector (API_NUMBER*DATA_WIDTH downto 0); APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*NUM_WIDTH downto 0); @@ -77,9 +76,10 @@ entity trb_net16_hub_base is HUB_STAT_CHANNEL : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); HUB_STAT_GEN : out std_logic_vector (31 downto 0); HUB_CTRL_CHANNEL : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); + HUB_CTRL_activepoints : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); HUB_CTRL_GEN : in std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); + MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); + MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); IOBUF_STAT_GEN : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); IOBUF_STAT_LOCKED : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); IOBUF_STAT_INIT_BUFFER : out std_logic_vector (2**(MUX_WIDTH-1)*MII_NUMBER*32-1 downto 0); @@ -129,8 +129,6 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is generic ( --media interfaces POINT_NUMBER : integer range 2 to 16 := 2; - INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; --general settings DATA_WIDTH : integer range 16 to 16 := 16; NUM_WIDTH : integer range 2 to 2 := 2 @@ -157,7 +155,8 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); STAT : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (31 downto 0) + CTRL : in std_logic_vector (31 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) ); end component; @@ -317,6 +316,14 @@ end component; begin +--set unused signals + MED_DATAREADY_OUT(MII_NUMBER+1 downto MII_NUMBER) <= "00"; + MED_DATA_OUT(MII_NUMBER*DATA_WIDTH+1 downto MII_NUMBER*DATA_WIDTH) <= "00"; + MED_PACKET_NUM_OUT(MII_NUMBER*NUM_WIDTH+1 downto MII_NUMBER*NUM_WIDTH) <= "00"; + MED_READ_OUT(MII_NUMBER+1 downto MII_NUMBER) <= "00"; + + + --generate multiplexers gen_muxes: for i in 0 to MII_NUMBER-1 generate MPLEX: trb_net16_io_multiplexer @@ -355,8 +362,8 @@ begin gen_iobufs: for i in 0 to 2**(MUX_WIDTH-1)*MII_NUMBER-1 generate IOBUF: trb_net16_iobuf generic map ( - INIT_DEPTH => conv_integer(to_stdlogicvector(MII_INIT_DEPTH((i+1)*4-1 downto i*4))), - REPLY_DEPTH => conv_integer(to_stdlogicvector(MII_REPLY_DEPTH((i+1)*4-1 downto i*4))) + INIT_DEPTH => 1, --conv_integer(MII_INIT_DEPTH((i+1)*4-1 downto i*4)), + REPLY_DEPTH => 1 --conv_integer(MII_REPLY_DEPTH((i+1)*4-1 downto i*4)) ) port map ( -- Misc @@ -426,8 +433,6 @@ begin generic map ( --media interfaces POINT_NUMBER => MII_NUMBER, - INIT_DEPTH => MII_INIT_DEPTH((i+1)*4 downto i*4), - REPLY_DEPTH => MII_REPLY_DEPTH((i+1)*4 downto i*4), --general settings DATA_WIDTH => DATA_WIDTH, NUM_WIDTH => NUM_WIDTH @@ -452,9 +457,10 @@ begin REPLY_DATAREADY_OUT => hub_to_buf_REPLY_DATAREADY((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), REPLY_DATA_OUT => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH*MII_NUMBER-1 downto i*DATA_WIDTH*MII_NUMBER), REPLY_PACKET_NUM_OUT => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH*MII_NUMBER-1 downto i*NUM_WIDTH*MII_NUMBER), - REPLY_READ_IN => hub_to_buf_REPLY_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER*MII_NUMBER), + REPLY_READ_IN => hub_to_buf_REPLY_READ((i+1)*MII_NUMBER-1 downto i*MII_NUMBER), STAT => HUB_STAT_CHANNEL((i+1)*32-1 downto i*32), - CTRL => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32) + CTRL => HUB_CTRL_CHANNEL((i+1)*32-1 downto i*32), + CTRL_activepoints => HUB_CTRL_activepoints((i+1)*32-1 downto i*32) ); end generate; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 42641c7..47d3693 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -1,179 +1,618 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - -use work.trb_net_std.all; - - -entity trb_net16_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to 16 := 10; - INIT_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - REPLY_DEPTH : bit_vector(POINT_NUMBER*8-1 downto 0) := x"1111"; - --general settings - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - --Internal interfaccs to IOBufs - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - --Status ports (for debugging) - STAT : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (31 downto 0) - ); -end entity; - -architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is - ---signals init_pool - signal INIT_POOL_DATAREADY : std_logic; - signal INIT_POOL_READ : std_logic; - signal INIT_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal INIT_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); - signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0); - signal saved_INIT_TYPE, current_INIT_TYPE : std_logic_vector(2 downto 0); - - - signal REPLY_POOL_DATAREADY : std_logic; - signal REPLY_POOL_READ : std_logic; - signal REPLY_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal REPLY_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); - signal saved_REPLY_TYPE , current_REPLY_TYPE : std_logic_vector(2 downto 0); - ---general signals - signal locked, next_locked : std_logic; - signal get_locked, release_locked : std_logic; - signal locking_point, next_locking_point : std_logic_vector(POINT_NUMBER-1 downto 0); - -begin - -STAT <= (others => '0'); - - ---Datapool for Init-Channel - INIT_POOL_DATAREADY <= or_all(INIT_DATAREADY_IN(POINT_NUMBER-1 downto 0)); - INIT_POOL_READ <= - and_all(INIT_READ_IN(POINT_NUMBER-1 downto 0) or init_has_read_from_pool(POINT_NUMBER-1 downto 0)); - - gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate - process(INIT_DATA_IN) - variable VAR_INIT_POOL_DATA : std_logic; - begin - VAR_INIT_POOL_DATA := '0'; - gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop - VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or INIT_DATA_IN(j*DATA_WIDTH+i); - end loop; - INIT_POOL_DATA(i) <= VAR_INIT_POOL_DATA; - end process; - end generate; - - gen_init_pool_data2: for i in 0 to NUM_WIDTH-1 generate - process(INIT_PACKET_NUM_IN) - variable VAR_INIT_POOL_PACKET_NUM : std_logic; - begin - VAR_INIT_POOL_PACKET_NUM := '0'; - gen_init_pool_data3: for j in 0 to POINT_NUMBER-1 loop - VAR_INIT_POOL_PACKET_NUM := VAR_INIT_POOL_PACKET_NUM or INIT_PACKET_NUM_IN(j*NUM_WIDTH+i); - end loop; - INIT_POOL_PACKET_NUM(i) <= VAR_INIT_POOL_PACKET_NUM; - end process; - end generate; - ---has-read signal - gen_hasread: for i in 0 to POINT_NUMBER-1 generate - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or INIT_POOL_READ = '1' then - init_has_read_from_pool(i) <= '0'; - else - if INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1' then - init_has_read_from_pool(i) <= '1'; - end if; - end if; - end if; - end process; - end generate; - ---signals to ibufs - INIT_READ_OUT <= (others => INIT_POOL_READ); - ---signals to obufs - gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate - INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i); - INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA; - INIT_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= INIT_POOL_PACKET_NUM; - end generate; - - - ---locked signals - release_locked <= '1' when (saved_REPLY_TYPE = TYPE_TRM) and REPLY_POOL_PACKET_NUM = "11" else '0'; - get_locked <= INIT_POOL_DATAREADY; - next_locked <= (get_locked or locked) and not release_locked; - next_locking_point <= INIT_DATAREADY_IN when locked = '0' else locking_point; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - locked <= '0'; - locking_point <= (others => '0'); - else - locked <= next_locked; - locking_point <= next_locking_point; - end if; - end if; - end process; - ---saving packet types - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_INIT_TYPE <= TYPE_ILLEGAL; - elsif INIT_POOL_DATAREADY = '1' and INIT_POOL_PACKET_NUM = "00" then - saved_INIT_TYPE <= INIT_POOL_DATA(2 downto 0); - end if; - end if; - end process; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_REPLY_TYPE <= TYPE_ILLEGAL; - elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" then - saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0); - end if; - end if; - end process; - current_INIT_TYPE <= INIT_POOL_DATA(2 downto 0) when INIT_POOL_DATAREADY = '1' and INIT_POOL_PACKET_NUM = "00" - else saved_INIT_TYPE; - current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" - else saved_REPLY_TYPE; - - - - -end architecture; \ No newline at end of file +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +use work.trb_net_std.all; + + +entity trb_net16_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 16 := 5; + + --general settings + DATA_WIDTH : integer range 16 to 16 := 16; + NUM_WIDTH : integer range 2 to 2 := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + --Internal interfaccs to IOBufs + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + --Status ports (for debugging) + STAT : out std_logic_vector (31 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') + ); +end entity; + +architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is + + component trb_net16_sbuf is + generic ( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + VERSION : integer := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in std_logic; --comb logic provides data word + COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle + COMB_READ_IN: in std_logic; --comb logic IS reading + COMB_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in std_logic_vector(NUM_WIDTH-1 downto 0); + -- Port to synchronous output. + SYN_DATAREADY_OUT: out std_logic; + SYN_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out std_logic_vector(NUM_WIDTH-1 downto 0); + SYN_READ_IN: in std_logic; + -- Status and control port + STAT_BUFFER: out std_logic + ); + end component; + component trb_net_priority_arbiter is + generic (WIDTH : integer := POINT_NUMBER); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + ENABLE : in std_logic; + CTRL: in STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + +--signals init_pool + signal INIT_POOL_DATAREADY : std_logic; + signal INIT_POOL_READ : std_logic; + signal INIT_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal INIT_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0); + signal saved_INIT_TYPE, current_INIT_TYPE : std_logic_vector(2 downto 0); + + signal buf_INIT_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + signal REPLY_POOL_DATAREADY : std_logic; + signal REPLY_POOL_READ : std_logic; + signal REPLY_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal REPLY_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal saved_REPLY_TYPE , current_REPLY_TYPE : std_logic_vector(2 downto 0); + signal REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal next_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_trmF1, reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0); + signal REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(DATA_WIDTH-1 downto 0); + signal REPLY_MUX_real_reading : std_logic; + +--general signals + signal locked, next_locked : std_logic; + signal get_locked, release_locked : std_logic; + signal got_trm : std_logic_vector(POINT_NUMBER-1 downto 0); + signal locking_point, next_locking_point : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reading_from_point : std_logic_vector(POINT_NUMBER-1 downto 0); + signal send_reply_trm : std_logic; + + signal init_locked, next_init_locked : std_logic; + signal get_init_locked, release_init_locked: std_logic; + + signal REPLY_MUX_reading : std_logic_vector(POINT_NUMBER-1 downto 0); + + type state_type is (IDLE, SENDING_DATA, SENDING_REPLY_TRM); + signal current_state, next_state : state_type; + signal packet_counter : std_logic_vector(1 downto 0); + signal data_counter : std_logic_vector(7 downto 0); + signal SEQ_NR : std_logic_vector(7 downto 0); + signal comb_REPLY_POOL_DATAREADY : std_logic; + signal comb_REPLY_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal comb_REPLY_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal REPLY_POOL_next_read : std_logic; + signal comb_REPLY_POOL_next_read : std_logic; + + + signal reply_point_lock : std_logic; + signal release_point_lock, get_point_lock : std_logic; + signal tmp_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); + + signal comb_REPLY_muxed_DATAREADY : std_logic; + signal comb_REPLY_muxed_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal comb_REPLY_muxed_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal reply_arbiter_CLK_EN : std_logic; + signal init_arbiter_CLK_EN : std_logic; + signal init_arbiter_read_out : std_logic_vector(POINT_NUMBER-1 downto 0); + signal reply_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); + + signal INIT_muxed_DATAREADY : std_logic; + signal INIT_muxed_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); + signal INIT_muxed_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal INIT_muxed_READ : std_logic; + signal comb_INIT_next_read : std_logic; + signal reply_fsm_state : std_logic; + +begin +REPLY_HEADER_OUT <= (others => '0'); + +STAT(23 downto 0) <= (others => '0'); +STAT(31 downto 24) <= data_counter; +STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm when locked = '1' else (others => '0'); +STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0'); +STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; + + INIT_POOL_SBUF: trb_net16_sbuf + generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => 0) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => INIT_muxed_DATAREADY, + COMB_next_READ_OUT => comb_INIT_next_read, + COMB_READ_IN => INIT_muxed_READ, + COMB_DATA_IN => INIT_muxed_DATA, + COMB_PACKET_NUM_IN => INIT_muxed_PACKET_NUM, + SYN_DATAREADY_OUT => INIT_POOL_DATAREADY, + SYN_DATA_OUT => INIT_POOL_DATA, + SYN_PACKET_NUM_OUT => INIT_POOL_PACKET_NUM, + SYN_READ_IN => INIT_POOL_READ + ); + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + INIT_muxed_READ <= '0'; + else + INIT_muxed_READ <= comb_INIT_next_read; + end if; + end if; + end process; + +--mux +--generates INIT_READ_OUT + +--choosing reply point + INIT_ARBITER: trb_net_priority_arbiter + generic map (WIDTH => POINT_NUMBER) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => init_arbiter_CLK_EN, + INPUT_IN => INIT_DATAREADY_IN, + RESULT_OUT => init_arbiter_read_out, + ENABLE => not init_locked, + CTRL => CTRL + ); + init_arbiter_CLK_EN <= not locked; + +--Datapool for Init-Channel + INIT_muxed_DATAREADY <= or_all(INIT_DATAREADY_IN) and not init_locked and INIT_muxed_READ; + INIT_POOL_READ <= and_all(INIT_READ_IN or init_has_read_from_pool or locking_point); + INIT_READ_OUT <= buf_INIT_READ_OUT; + + buf_INIT_READ_OUT <= init_arbiter_read_out when init_locked = '0' else (others => '0'); + + gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate + process(INIT_DATA_IN) + variable VAR_INIT_POOL_DATA : std_logic; + begin + VAR_INIT_POOL_DATA := '0'; + gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop + VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or (INIT_DATA_IN(j*DATA_WIDTH+i) and buf_INIT_READ_OUT(j)); + end loop; + INIT_muxed_DATA(i) <= VAR_INIT_POOL_DATA; + end process; + end generate; + + gen_init_pool_data2: for i in 0 to NUM_WIDTH-1 generate + process(INIT_PACKET_NUM_IN) + variable VAR_INIT_POOL_PACKET_NUM : std_logic; + begin + VAR_INIT_POOL_PACKET_NUM := '0'; + gen_init_pool_data3: for j in 0 to POINT_NUMBER-1 loop + VAR_INIT_POOL_PACKET_NUM := VAR_INIT_POOL_PACKET_NUM or (INIT_PACKET_NUM_IN(j*NUM_WIDTH+i) and buf_INIT_READ_OUT(j)); + end loop; + INIT_muxed_PACKET_NUM(i) <= VAR_INIT_POOL_PACKET_NUM; + end process; + end generate; + + +--init_has_read signal + gen_hasread: for i in 0 to POINT_NUMBER-1 generate + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or INIT_POOL_READ = '1' then + init_has_read_from_pool(i) <= '0'; + else + if INIT_POOL_DATAREADY = '1' and INIT_READ_IN(i) = '1' then + init_has_read_from_pool(i) <= '1'; + end if; + end if; + end if; + end process; + end generate; + + + +--signals to obufs + gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate + INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and CTRL_activepoints(i) and not locking_point(i); + INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA; + INIT_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= INIT_POOL_PACKET_NUM; + end generate; + + +--locked signals +--locked: transfer is running +--init_locked: waiting for reply channel to finish + send_reply_trm <= '1' when and_all(got_trm) = '1' + else '0'; + get_locked <= INIT_muxed_DATAREADY; + next_locked <= (get_locked or locked) and not release_locked; + next_locking_point <= (buf_INIT_READ_OUT and INIT_DATAREADY_IN) when (locked = '0' and REPLY_POOL_DATAREADY = '0') else locking_point; + + get_init_locked <= '1' when saved_INIT_TYPE = TYPE_TRM and INIT_muxed_PACKET_NUM = "11" else '0'; + release_init_locked <= release_locked; + next_init_locked <= (get_init_locked or init_locked) and not release_init_locked; + + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + locked <= '0'; + locking_point <= (others => '0'); + init_locked <= '0'; + else + locked <= next_locked; + locking_point <= next_locking_point; + init_locked <= next_init_locked; + end if; + end if; + end process; + + gen_reply_data_out: for i in 0 to POINT_NUMBER-1 generate + REPLY_DATAREADY_OUT(i) <= REPLY_POOL_DATAREADY and locking_point(i); + REPLY_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= REPLY_POOL_DATA; + REPLY_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= REPLY_POOL_PACKET_NUM; + end generate; + REPLY_POOL_READ <= or_all(REPLY_READ_IN and locking_point); + + buf_REPLY_READ_OUT <= REPLY_reading_trm or REPLY_MUX_reading when REPLY_POOL_next_read = '1' else + REPLY_reading_trm; + REPLY_READ_OUT <= buf_REPLY_READ_OUT; + + REPLY_MUX_real_reading <= or_all(REPLY_MUX_reading) and REPLY_POOL_next_read; + +--saving necessary data +---------------------------------- + save_INIT_TYPE : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or (INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = "11") then + saved_INIT_TYPE <= TYPE_ILLEGAL; + elsif INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = "00" then + saved_INIT_TYPE <= INIT_muxed_DATA(2 downto 0); + end if; + end if; + end process; + current_INIT_TYPE <= INIT_muxed_DATA(2 downto 0) when INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = "00" + else saved_INIT_TYPE; + + save_REPLY_TYPE : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "11") then + saved_REPLY_TYPE <= TYPE_ILLEGAL; + elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" then + saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0); + end if; + end if; + end process; + current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = "00" + else saved_REPLY_TYPE; + + save_SEQ_NR : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + SEQ_NR <= (others => '0'); + elsif INIT_POOL_PACKET_NUM = "11" and current_INIT_TYPE = TYPE_HDR then + SEQ_NR <= INIT_POOL_DATA(11 downto 4); + end if; + end if; + end process; + + + +--REPLY reading and merging TRM +---------------------------------- + gen_reading_trm : for i in 0 to POINT_NUMBER-1 generate + process(REPLY_reading_trm, REPLY_PACKET_NUM_IN, REPLY_DATA_IN) + begin + next_REPLY_reading_trm(i) <= REPLY_reading_trm(i); + if REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "11" then + next_REPLY_reading_trm(i) <= '0'; + elsif REPLY_DATA_IN(i*DATA_WIDTH+2 downto i*DATA_WIDTH) = TYPE_TRM + and REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "00" then + next_REPLY_reading_trm(i) <= '1'; + end if; + end process; + end generate; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + REPLY_reading_trm <= (others => '0'); + else + REPLY_reading_trm <= next_REPLY_reading_trm; + end if; + end if; + end process; + current_REPLY_reading_trm <= next_REPLY_reading_trm or REPLY_reading_trm; + + + gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate + reading_trmF1(i) <= '1' when REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "01" + and REPLY_reading_trm(i) = '1' + and REPLY_DATAREADY_IN(i) = '1' + else '0'; + reading_trmF2(i) <= '1' when REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "10" + and REPLY_reading_trm(i) = '1' + and REPLY_DATAREADY_IN(i) = '1' + else '0'; + end generate; + + gen_combining_trm : for j in 0 to DATA_WIDTH-1 generate + process(CLK) + variable tmpF1, tmpF2 : std_logic; + begin + if rising_edge(CLK) then + if RESET = '1' or locked = '0' then + REPLY_combined_trm_F1(j) <= '0'; + REPLY_combined_trm_F2(j) <= '0'; + else + tmpF1 := '0'; + tmpF2 := '0'; + for i in 0 to POINT_NUMBER-1 loop + tmpF1 := tmpF1 or (REPLY_DATA_IN(i*DATA_WIDTH+j) and reading_trmF1(i)); + tmpF2 := tmpF2 or (REPLY_DATA_IN(i*DATA_WIDTH+j) and reading_trmF2(i)); + end loop; + REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1; + REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2; + end if; + end if; + end process; + end generate; + + + +--count received TRM +---------------------------------- + gen_got_trm : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or send_reply_trm = '1' then + got_trm <= (others => '0'); + else + got_trm <= got_trm or locking_point or reading_trmF2 or not CTRL_activepoints(POINT_NUMBER-1 downto 0); + end if; + end if; + end process; + + + +--REPLY Count 16 and 64 bit packets +---------------------------------- + gen_packet_counter : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or locked = '0' then + packet_counter <= (others => '0'); + elsif comb_REPLY_POOL_DATAREADY = '1' then + packet_counter <= packet_counter + 1; + end if; + end if; + end process; + + gen_data_counter : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or reply_point_lock = '0' then + data_counter <= (others => '0'); + elsif comb_REPLY_POOL_PACKET_NUM="11" and comb_REPLY_POOL_DATAREADY = '1' then + data_counter <= data_counter + 1; + end if; + end if; + end process; + + + + +--REPLY mux select input +---------------------------------- + REPLY_ARBITER: trb_net_priority_arbiter + generic map (WIDTH => POINT_NUMBER) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => reply_arbiter_CLK_EN, + INPUT_IN => reply_arbiter_input, + RESULT_OUT => REPLY_MUX_reading, + ENABLE => '1', + CTRL => CTRL + ); + + reply_arbiter_input <= REPLY_DATAREADY_IN; + + -- we have to care to read multiples of four packets from every point + -- release is currently done after first packet of TRM + gen_reply_point_lock : process(comb_REPLY_POOL_PACKET_NUM, comb_REPLY_POOL_DATAREADY, + saved_REPLY_TYPE, comb_REPLY_muxed_PACKET_NUM, comb_REPLY_muxed_DATAREADY, + comb_REPLY_muxed_DATA) + begin + release_point_lock <= '0'; + get_point_lock <= '0'; + if comb_REPLY_muxed_PACKET_NUM = "00" and or_all(buf_REPLY_READ_OUT and REPLY_MUX_reading) = '1' then + if comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM then + release_point_lock <= '1'; + else + get_point_lock <= '1'; + end if; + end if; + end process; + + gen_point_lock : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or release_point_lock = '1' then + reply_point_lock <= '0'; + reading_from_point <= (others => '0'); + elsif get_point_lock = '1' then + reply_point_lock <= '1'; + reading_from_point <= REPLY_MUX_reading; + end if; + end if; + end process; + + reply_arbiter_CLK_EN <= not reply_point_lock; + + + +--REPLY mux +---------------------------------- + gen_reply_mux1 : for i in 0 to DATA_WIDTH-1 generate + data_mux : process(REPLY_DATA_IN, REPLY_MUX_reading) + variable tmp_data : std_logic; + begin + tmp_data := '0'; + gen_data_mux : for j in 0 to POINT_NUMBER-1 loop + tmp_data := tmp_data or (REPLY_DATA_IN(j*DATA_WIDTH+i) and REPLY_MUX_reading(j)); + end loop; + comb_REPLY_muxed_DATA(i) <= tmp_data; + end process; + end generate; + + gen_reply_mux2 : for i in 0 to NUM_WIDTH-1 generate + packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading) + variable tmp_pm : std_logic; + begin + tmp_pm := '0'; + gen_pm_mux : for j in 0 to POINT_NUMBER-1 loop + tmp_pm := tmp_pm or (REPLY_PACKET_NUM_IN(j*NUM_WIDTH+i) and REPLY_MUX_reading(j)); + end loop; + comb_REPLY_muxed_PACKET_NUM(i) <= tmp_pm; + end process; + end generate; + + comb_REPLY_muxed_DATAREADY <= or_all(REPLY_MUX_reading and REPLY_DATAREADY_IN and not current_REPLY_reading_trm) and REPLY_MUX_real_reading; + + +--REPLY POOL state machine +---------------------------------- + reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, + send_reply_trm, SEQ_NR, REPLY_combined_trm_F1, REPLY_combined_trm_F2, + comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, + comb_REPLY_muxed_PACKET_NUM) + begin + release_locked <= '0'; + next_state <= current_state; + comb_REPLY_POOL_DATAREADY <= '0'; + comb_REPLY_POOL_PACKET_NUM <= packet_counter; + comb_REPLY_POOL_DATA <= (others => '0'); + + + if current_state = SENDING_DATA then + comb_REPLY_POOL_DATAREADY <= comb_REPLY_muxed_DATAREADY; + comb_REPLY_POOL_DATA <= comb_REPLY_muxed_DATA; + comb_REPLY_POOL_PACKET_NUM <= comb_REPLY_muxed_PACKET_NUM; + if send_reply_trm = '1' and comb_REPLY_muxed_PACKET_NUM = "11" then + next_state <= SENDING_REPLY_TRM; + end if; + end if; + + if current_state = SENDING_REPLY_TRM then + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + case packet_counter is + when "00" => + comb_REPLY_POOL_DATA <= (others => '0'); + comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_TRM; + when "01" => + comb_REPLY_POOL_DATA <= REPLY_combined_trm_F1; + when "10" => + comb_REPLY_POOL_DATA <= REPLY_combined_trm_F2; + when "11" => + comb_REPLY_POOL_DATA <= "0000" & SEQ_NR & "0000"; + if REPLY_POOL_next_read = '1' then + release_locked <= '1'; + next_state <= SENDING_DATA; + end if; + when others => + comb_REPLY_POOL_DATA <= (others => '0'); + end case; + end if; + end process; + + reply_fsm_state <= '1' when current_state= SENDING_REPLY_TRM else '0'; + + +--REPLY sbuf +---------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= SENDING_DATA; + REPLY_POOL_next_read <= '0'; + else + current_state <= next_state; + REPLY_POOL_next_read <= comb_REPLY_POOL_next_read; + end if; + end if; + end process; + + REPLY_POOL_SBUF: trb_net16_sbuf + generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => 0) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => comb_REPLY_POOL_DATAREADY, + COMB_next_READ_OUT => comb_REPLY_POOL_next_read, + COMB_READ_IN => REPLY_POOL_next_read, + COMB_DATA_IN => comb_REPLY_POOL_DATA, + COMB_PACKET_NUM_IN => comb_REPLY_POOL_PACKET_NUM, + SYN_DATAREADY_OUT => REPLY_POOL_DATAREADY, + SYN_DATA_OUT => REPLY_POOL_DATA, + SYN_PACKET_NUM_OUT => REPLY_POOL_PACKET_NUM, + SYN_READ_IN => REPLY_POOL_READ + ); + + + + +end architecture; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 8e5c7e6..528c2c5 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -116,6 +116,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); signal current_mux_packet_number : std_logic_vector (1 downto 0); signal last_mux_enable : std_logic; + signal arbiter_CLK_EN : std_logic; begin ------------------------------------------------------------------------------- -- DEMUX @@ -229,14 +230,14 @@ ARBITER: trb_net_priority_arbiter port map ( CLK => CLK, RESET => RESET, - CLK_EN => CLK_EN, + CLK_EN => arbiter_CLK_EN, INPUT_IN => INT_DATAREADY_IN, - RESULT_OUT => tmp_INT_READ_OUT, + RESULT_OUT => final_INT_READ_OUT, ENABLE => mux_enable, CTRL => CTRL ); - + arbiter_CLK_EN <= CLK_EN and not endpoint_locked; -- we have to care to read four packets from every endpoint process(current_mux_buffer, mux_read, endpoint_locked, current_mux_packet_number) @@ -249,16 +250,16 @@ ARBITER: trb_net_priority_arbiter end if; end process; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - final_INT_READ_OUT <= (others => '0'); - elsif endpoint_locked = '0' then - final_INT_READ_OUT <= tmp_INT_READ_OUT; - end if; - end if; - end process; +-- process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- final_INT_READ_OUT <= (others => '0'); +-- elsif endpoint_locked = '0' then +-- final_INT_READ_OUT <= tmp_INT_READ_OUT; +-- end if; +-- end if; +-- end process; process(CLK) begin @@ -273,11 +274,7 @@ ARBITER: trb_net_priority_arbiter process(tmp_INT_READ_OUT, endpoint_locked, final_INT_READ_OUT, last_mux_enable) begin - if endpoint_locked = '0' then - current_INT_READ_OUT <= tmp_INT_READ_OUT; - else - current_INT_READ_OUT <= final_INT_READ_OUT; - end if; + current_INT_READ_OUT <= final_INT_READ_OUT; if last_mux_enable = '0' then current_INT_READ_OUT <= (others => '0'); end if; @@ -285,6 +282,7 @@ ARBITER: trb_net_priority_arbiter -- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0' -- else final_INT_READ_OUT; + STAT(17 downto 16) <= current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH) xor current_mux_packet_number; process(CLK) diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index c3ebd0b..4a3c1a2 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -114,7 +114,8 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is component trb_net16_ibuf is generic ( - DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) + DEPTH : integer range 0 to 7 := 1; + SBUF_VERSION : integer range 0 to 1 := 0 ); port( -- Misc @@ -142,6 +143,11 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is end component; component trb_net16_term_ibuf is + generic( + DATA_WIDTH : integer := 16; + NUM_WIDTH : integer := 2; + VERSION : integer range 0 to 1 := 0 + ); port( -- Misc CLK : in std_logic; diff --git a/trb_net_priority_arbiter.vhd b/trb_net_priority_arbiter.vhd index 79853eb..751e01d 100755 --- a/trb_net_priority_arbiter.vhd +++ b/trb_net_priority_arbiter.vhd @@ -161,12 +161,6 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is current_rr_mask <= next_rr_mask; current_final_pattern <= next_final_pattern; current_rr_mask <= next_rr_mask; - else - current_p1_pattern <= current_p1_pattern; - current_p2_pattern <= current_p2_pattern; - current_rr_mask <= current_rr_mask; - current_final_pattern <= current_final_pattern; - current_rr_mask <= current_rr_mask; end if; end if; end process; diff --git a/xilinx/trb_net16_bram_fifo.vhd b/xilinx/trb_net16_bram_fifo.vhd index 4879bde..c005425 100644 --- a/xilinx/trb_net16_bram_fifo.vhd +++ b/xilinx/trb_net16_bram_fifo.vhd @@ -218,7 +218,8 @@ end process proc3; -- -- --------------------------------------------------------------- -wa_or_fcnt0 <= (write_allow OR fcounter(0)); +--wa_or_fcnt0 <= (write_allow OR fcounter(0)); +wa_or_fcnt0 <= fcounter(0); fullg <= (and_all(fcounter(9 downto 1)) AND wa_or_fcnt0 AND NOT read_allow); proc4: process (clock, fifo_gsr) -- 2.43.0