From 5c95491b372bd0d9cb991a8e141712579fa977af Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Thu, 30 Jan 2014 17:16:21 +0100
Subject: [PATCH] added configuration register for trigger and clock fan-out

---
 trb3/HardwareProject.tex    |  0
 trb3/Trb3GeneralRemarks.tex | 12 ++++++++++++
 trb3/Trb3Hardware.tex       |  0
 trb3/main.tex               |  1 -
 4 files changed, 12 insertions(+), 1 deletion(-)
 delete mode 100644 trb3/HardwareProject.tex
 delete mode 100644 trb3/Trb3Hardware.tex

diff --git a/trb3/HardwareProject.tex b/trb3/HardwareProject.tex
deleted file mode 100644
index e69de29..0000000
diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 7afb333..ba0514a 100644
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -196,6 +196,18 @@ The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender
 \item[C] Unpack as CTS data
 \item[5] The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent.
 \end{description*}
+The data format is shown in later sections.
+
+
+\subsection{Trigger \& Clock Input}
+Both trigger and clock input (RJ-45 connectors) are equipped with a configurable fan-out chip. Its control signals can be set in slow-control register 0xd300 (currently in CTS only, but should also be present in other central FPGA).
+\begin{description*}
+ \item[Bit 0] Trigger select (local signal: 1, external signal: 0
+ \item[Bit 8] Clock select (Input 0 or 1)
+ \item[Bit 19 -- 16] 4 User signals on trigger fan-out
+ \item[Bit 27 -- 24] 4 User signals on clock fan-out
+\end{description*}
+
 
 
 %%% Local Variables: 
diff --git a/trb3/Trb3Hardware.tex b/trb3/Trb3Hardware.tex
deleted file mode 100644
index e69de29..0000000
diff --git a/trb3/main.tex b/trb3/main.tex
index 6757662..dc46671 100644
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -141,7 +141,6 @@
     \input{Trb3GeneralRemarks}
 \cleardoublepage
 \part{Hardware}
-  \input{Trb3Hardware}
   \section{Measurements}
     \subsection{FPGA I/O Performance}
     \clearpage
-- 
2.43.0