From 5e8a608b7304149bf0b59a70f894d0dca1ceb509 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Thu, 1 May 2014 15:52:53 +0200 Subject: [PATCH] nxyter working design, adc still slightly buggy... --- nxyter/compile_munich21.pl | 2 +- nxyter/source/adc_ad9228.vhd | 20 +- nxyter/source/nx_data_receiver.vhd | 272 +++++++++++++++++------- nxyter/source/nx_data_validate.vhd | 2 - nxyter/source/nx_fpga_timestamp.vhd | 66 +++--- nxyter/source/nx_histograms.vhd | 2 +- nxyter/source/nx_status.vhd | 69 +++--- nxyter/source/nx_trigger_generator.vhd | 16 +- nxyter/source/nx_trigger_handler.vhd | 114 ++++++---- nxyter/source/nx_trigger_validate.vhd | 44 +++- nxyter/source/nxyter_components.vhd | 6 +- nxyter/source/nxyter_fee_board.vhd | 13 +- nxyter/source/signal_async_to_pulse.vhd | 6 + nxyter/source/signal_async_trans.vhd | 6 + nxyter/trb3_periph.p2t | 21 +- nxyter/trb3_periph_constraints.lpf | 63 +++--- 16 files changed, 432 insertions(+), 290 deletions(-) mode change 100644 => 120000 nxyter/trb3_periph.p2t diff --git a/nxyter/compile_munich21.pl b/nxyter/compile_munich21.pl index 5f2a17b..1d7b458 100755 --- a/nxyter/compile_munich21.pl +++ b/nxyter/compile_munich21.pl @@ -112,7 +112,7 @@ execute($c); system("rm $TOPNAME.ncd"); -$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; execute($c); # IOR IO Timing Report diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 4e9789d..df005cd 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -52,7 +52,9 @@ entity adc_ad9228 is end adc_ad9228; architecture Behavioral of adc_ad9228 is - + attribute HGROUP : string; + attribute HGROUP of Behavioral : architecture is "SAMPLING_ADC_AD9228"; + -- DDR Generic Handler signal DDR_DATA_CLK : std_logic; signal q_0_ff : std_logic_vector(19 downto 0); @@ -136,7 +138,21 @@ architecture Behavioral of adc_ad9228 is -- Resets signal RESET_CLK_ADCDAT_IN : std_logic; signal RESET_DDR_DATA_CLK : std_logic; - + + -- + attribute syn_keep : boolean; + attribute syn_keep of q_0_ff : signal is true; + attribute syn_keep of q_0_f : signal is true; + attribute syn_keep of q_1_ff : signal is true; + attribute syn_keep of q_1_f : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of q_0_ff : signal is true; + attribute syn_preserve of q_0_f : signal is true; + attribute syn_preserve of q_1_ff : signal is true; + attribute syn_preserve of q_1_f : signal is true; + + begin PROC_DEBUG: process (DEBUG_IN) diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index cb2c97b..7d0b97b 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -15,7 +15,8 @@ entity nx_data_receiver is CLK_IN : in std_logic; RESET_IN : in std_logic; TRIGGER_IN : in std_logic; - + NX_ONLINE_IN : in std_logic; + -- nXyter Ports NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); @@ -168,8 +169,8 @@ architecture Behavioral of nx_data_receiver is signal rate_timer_ctr : unsigned(27 downto 0); -- Error - signal error_adc0 : std_logic; - signal error_adc1 : std_logic; + signal error_adc0_o : std_logic; + signal error_adc1_o : std_logic; signal error_o : std_logic; signal error_status_bits : std_logic_vector(11 downto 0); @@ -239,10 +240,16 @@ architecture Behavioral of nx_data_receiver is signal adc_notlock_ctr_r : unsigned(7 downto 0); signal merge_error_ctr_r : unsigned(11 downto 0); signal nx_frame_synced_r : std_logic; + signal disable_adc_r : std_logic; ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- + signal nx_online_ii : std_logic; + signal nx_online_i : std_logic; + signal error_adc0_ff : std_logic; + signal error_adc0_f : std_logic; + signal error_adc0 : std_logic; signal startup_reset : std_logic; signal rs_wait_timer_start : std_logic; signal rs_wait_timer_done : std_logic; @@ -254,10 +261,14 @@ architecture Behavioral of nx_data_receiver is signal fifo_reset_handler : std_logic; type R_STATES is (R_IDLE, - R_RESET_TIMESTAMP, + R_START, R_WAIT_0, - R_SET_ALL_RESETS, + R_WAIT_NX_ONLINE, R_WAIT_1, + R_RESET_TIMESTAMP, + R_WAIT_2, + R_SET_ALL_RESETS, + R_WAIT_3, R_WAIT_NX_FRAME_RATE_OK, R_PLL_WAIT_LOCK, R_WAIT_ADC_OK, @@ -270,6 +281,7 @@ architecture Behavioral of nx_data_receiver is signal adc_reset_handler : std_logic; signal adc_reset_p : std_logic; signal output_handler_reset : std_logic; + signal disable_adc_n : std_logic; signal reset_handler_counter : unsigned(15 downto 0); signal reset_handler_busy : std_logic; @@ -284,15 +296,50 @@ architecture Behavioral of nx_data_receiver is signal parity_error : std_logic; signal parity_error_c100 : std_logic; signal parity_error_counter : unsigned(11 downto 0); - - -- Reset Domain Transfers - signal RESET_NX_TIMESTAMP_CLK_IN : std_logic; + signal reset_nx_timestamp_clk_in_ff : std_logic; + signal reset_nx_timestamp_clk_in_f : std_logic; + signal RESET_NX_TIMESTAMP_CLK_IN : std_logic; signal debug_state : std_logic_vector(3 downto 0); signal debug_frame_on : std_logic; + -- Keep FlipFlops, do not change to shift registers ----------- + + + attribute syn_keep : boolean; + attribute syn_keep of nx_frame_word_ff : signal is true; + attribute syn_keep of nx_frame_word_f : signal is true; + + attribute syn_keep of reset_nx_timestamp_clk_in_ff : signal is true; + attribute syn_keep of reset_nx_timestamp_clk_in_f : signal is true; + + attribute syn_keep of nx_frame_clk_delayed_t : signal is true; + attribute syn_keep of nx_frame_word_delayed_t : signal is true; + + attribute syn_keep of error_adc0_ff : signal is true; + attribute syn_keep of error_adc0_f : signal is true; + + attribute syn_keep of nx_online_ii : signal is true; + attribute syn_keep of nx_online_i : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of nx_frame_word_ff : signal is true; + attribute syn_preserve of nx_frame_word_f : signal is true; + + attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true; + attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true; + + attribute syn_preserve of nx_frame_clk_delayed_t : signal is true; + attribute syn_preserve of nx_frame_word_delayed_t : signal is true; + + attribute syn_preserve of error_adc0_ff : signal is true; + attribute syn_preserve of error_adc0_f : signal is true; + + attribute syn_preserve of nx_online_ii : signal is true; + attribute syn_preserve of nx_online_i : signal is true; + begin DFALSE: if (DEBUG_ENABLE = false) generate @@ -350,7 +397,7 @@ begin DEBUG_OUT(5) <= nx_frame_rate_offline; DEBUG_OUT(6) <= nx_frame_rate_error; DEBUG_OUT(7) <= pll_adc_not_lock; - DEBUG_OUT(8) <= error_adc0; + DEBUG_OUT(8) <= error_adc0_o; DEBUG_OUT(9) <= adc_frame_rate_error; DEBUG_OUT(10) <= fifo_reset_handler; DEBUG_OUT(11) <= pll_adc_sampling_clk_reset; @@ -434,30 +481,30 @@ begin end process PROC_DEBUG_MULT; - PROC_SAMPLE_CLOCK: process(NX_TIMESTAMP_CLK_IN) - begin - if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (NX_TIMESTAMP_IN = x"06" and - nx_frame_word_ff = x"7f") then - debug_frame_on <= '1'; - else - debug_frame_on <= '0'; - end if; - end if; - end process PROC_SAMPLE_CLOCK; +-- PROC_SAMPLE_CLOCK: process(NX_TIMESTAMP_CLK_IN) +-- begin +-- if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then +-- if (NX_TIMESTAMP_IN = x"06" and +-- nx_frame_word_ff = x"7f") then +-- debug_frame_on <= '1'; +-- else +-- debug_frame_on <= '0'; +-- end if; +-- end if; +-- end process PROC_SAMPLE_CLOCK; end generate DTRUE; ----------------------------------------------------------------------------- -- Reset Domain Transfer ----------------------------------------------------------------------------- - signal_async_trans_RESET_IN: signal_async_trans - port map ( - CLK_IN => NX_TIMESTAMP_CLK_IN, - SIGNAL_A_IN => RESET_IN, - SIGNAL_OUT => RESET_NX_TIMESTAMP_CLK_IN - ); - + reset_nx_timestamp_clk_in_ff <= RESET_IN + when rising_edge(NX_TIMESTAMP_CLK_IN); + reset_nx_timestamp_clk_in_f <= reset_nx_timestamp_clk_in_ff + when rising_edge(NX_TIMESTAMP_CLK_IN); + RESET_NX_TIMESTAMP_CLK_IN <= reset_nx_timestamp_clk_in_f + when rising_edge(NX_TIMESTAMP_CLK_IN); + ----------------------------------------------------------------------------- -- PLL Handler ----------------------------------------------------------------------------- @@ -872,27 +919,33 @@ begin end loop; frame_word_delay_change <= '0'; frame_word_delay_set <= '0'; - if (nx_timestamp_delayed_clk = '1') then - case adc_data_clk_last is - when "0100" => - nx_frame_word_delay_f <= nx_frame_word_delay_f + 1; - frame_word_delay_change <= '1'; - - when "0010" => - nx_frame_word_delay_f <= nx_frame_word_delay_f + 2; - frame_word_delay_change <= '1'; - - when "0001" => - nx_frame_word_delay_f <= nx_frame_word_delay_f + 3; - frame_word_delay_change <= '1'; - when others => - null; - - end case; - - if (adc_data_s_clk = '1') then - frame_word_delay_set <= '1'; + if (disable_adc_n = '1') then + nx_frame_word_delay_f <= "10"; + frame_word_delay_set <= '1'; + else + if (nx_timestamp_delayed_clk = '1') then + case adc_data_clk_last is + when "0100" => + nx_frame_word_delay_f <= nx_frame_word_delay_f + 1; + frame_word_delay_change <= '1'; + + when "0010" => + nx_frame_word_delay_f <= nx_frame_word_delay_f + 2; + frame_word_delay_change <= '1'; + + when "0001" => + nx_frame_word_delay_f <= nx_frame_word_delay_f + 3; + frame_word_delay_change <= '1'; + + when others => + null; + + end case; + + if (adc_data_s_clk = '1') then + frame_word_delay_set <= '1'; + end if; end if; end if; end if; @@ -943,8 +996,8 @@ begin ADC0_NOTLOCK_COUNTER => adc_notlock_ctr, ADC1_NOTLOCK_COUNTER => open, - ERROR_ADC0_OUT => error_adc0, - ERROR_ADC1_OUT => error_adc1, + ERROR_ADC0_OUT => error_adc0_o, + ERROR_ADC1_OUT => error_adc1_o, DEBUG_IN => adc_debug_type, DEBUG_OUT => ADC_DEBUG ); @@ -974,11 +1027,12 @@ begin ----------------------------------------------------------------------------- -- Merge Data Streams Timestamps and ADC Value ----------------------------------------------------------------------------- - merge_handler_reset_i <= - output_handler_reset when rising_edge(NX_TIMESTAMP_CLK_IN); - merge_handler_reset <= - merge_handler_reset_i when rising_edge(NX_TIMESTAMP_CLK_IN); - + merge_handler_reset_i <= output_handler_reset + when rising_edge(NX_TIMESTAMP_CLK_IN); + merge_handler_reset <= merge_handler_reset_i + when rising_edge(NX_TIMESTAMP_CLK_IN); + disable_adc_n <= disable_adc_r when rising_edge(NX_TIMESTAMP_CLK_IN); + PROC_DATA_MERGE_HANDLER: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then @@ -987,9 +1041,15 @@ begin merge_timeout_error <= '0'; merge_error_ctr <= (others => '0'); else - if (nx_timestamp_delayed_clk = '1' and adc_data_s_clk = '1') then + if (nx_timestamp_delayed_clk = '1' and + (adc_data_s_clk = '1' or disable_adc_n = '1') + ) then data_frame(31 downto 0) <= nx_timestamp_delayed; - data_frame(43 downto 32) <= adc_data_s; + if (disable_adc_n = '0') then + data_frame(43 downto 32) <= adc_data_s; + else + data_frame(43 downto 32) <= x"dea"; + end if; data_frame_clk <= '1'; merge_timeout_ctr <= (others => '0'); else @@ -1321,6 +1381,13 @@ begin ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- + + error_adc0_ff <= error_adc0_o when rising_edge(CLK_IN); + error_adc0_f <= error_adc0_ff when rising_edge(CLK_IN); + error_adc0 <= error_adc0_f when rising_edge(CLK_IN); + + nx_online_ii <= NX_ONLINE_IN when rising_edge(CLK_IN); + nx_online_i <= nx_online_ii when rising_edge(CLK_IN); PROC_RESET_HANDLER: process(CLK_IN) begin @@ -1361,19 +1428,20 @@ begin if (reset_handler_start_r = '1') then -- Reset by register always wins, start it rs_timeout_timer_reset <= '1'; - R_STATE <= R_RESET_TIMESTAMP; + R_STATE <= R_START; elsif (rs_timeout_timer_done = '1') then -- Reset Timeout, retry RESET rs_timeout_timer_reset <= '1'; reset_timeout_flag <= '1'; - R_STATE <= R_RESET_TIMESTAMP; + R_STATE <= R_START; else case R_STATE is when R_IDLE => - if (reset_for_offline = '1' or - pll_adc_not_lock = '1' or - adc_reset_sync = '1' or + if (reset_for_offline = '1' or + (disable_adc_r = '0' and + (pll_adc_not_lock = '1' or + adc_reset_sync = '1')) or startup_reset = '1' ) then R_STATE <= R_RESET_TIMESTAMP; @@ -1383,26 +1451,61 @@ begin reset_handler_busy <= '0'; R_STATE <= R_IDLE; end if; + debug_state <= x"1"; + + when R_START => + -- First wait 1mue for NX_MAIN_CLK, have to put lock status here + -- to check in the future. + rs_wait_timer_start <= '1'; + R_STATE <= R_WAIT_0; + debug_state <= x"2"; + + when R_WAIT_0 => + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_0; + else + R_STATE <= R_WAIT_NX_ONLINE; + end if; + debug_state <= x"3"; + when R_WAIT_NX_ONLINE => + if (nx_online_i = '0') then + R_STATE <= R_WAIT_NX_ONLINE; + else + -- Just wait again + rs_wait_timer_start <= '1'; + R_STATE <= R_WAIT_1; + end if; + debug_state <= x"4"; + + when R_WAIT_1 => + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_1; + else + R_STATE <= R_RESET_TIMESTAMP; + end if; + debug_state <= x"5"; + when R_RESET_TIMESTAMP => -- must reset/resync Timestamp clock and data trnasmission clock -- of nxyter first, afterwards wait a bit to let settle down reset_handler_counter <= reset_handler_counter + 1; nx_timestamp_reset_o <= '1'; rs_wait_timer_start <= '1'; -- wait 1mue to settle - R_STATE <= R_WAIT_0; - debug_state <= x"1"; - - when R_WAIT_0 => + R_STATE <= R_WAIT_2; + debug_state <= x"6"; + + when R_WAIT_2 => if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_0; + R_STATE <= R_WAIT_2; else R_STATE <= R_SET_ALL_RESETS; end if; - debug_state <= x"2"; - + debug_state <= x"7"; + when R_SET_ALL_RESETS => - -- timer reset should be finished, can we check status,To be done? + -- timer reset should be finished, can we check status, + -- To be done? -- now set reset of all handlers frame_rates_reset <= '1'; pll_adc_sampling_clk_reset <= '1'; @@ -1413,23 +1516,23 @@ begin -- give resets 1mue to take effect rs_wait_timer_start <= '1'; - R_STATE <= R_WAIT_1; + R_STATE <= R_WAIT_3; debug_state <= x"3"; - when R_WAIT_1 => + when R_WAIT_3 => pll_adc_sampling_clk_reset <= '1'; adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_1; + R_STATE <= R_WAIT_3; else -- now start timeout timer and begin to release resets -- step by step rs_timeout_timer_start <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; - debug_state <= x"4"; + debug_state <= x"8"; when R_WAIT_NX_FRAME_RATE_OK => if (nx_frame_rate_offline = '0' and @@ -1438,7 +1541,11 @@ begin adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; - R_STATE <= R_PLL_WAIT_LOCK; + if (disable_adc_r = '0') then + R_STATE <= R_PLL_WAIT_LOCK; + else + R_STATE <= R_WAIT_DATA_HANDLER_OK; + end if; else pll_adc_sampling_clk_reset <= '1'; adc_reset_handler <= '1'; @@ -1446,7 +1553,7 @@ begin fifo_reset_handler <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; - debug_state <= x"5"; + debug_state <= x"9"; when R_PLL_WAIT_LOCK => if (pll_adc_not_lock = '0') then @@ -1473,7 +1580,7 @@ begin fifo_reset_handler <= '1'; R_STATE <= R_WAIT_ADC_OK; end if; - debug_state <= x"7"; + debug_state <= x"a"; when R_WAIT_DATA_HANDLER_OK => if (frame_rate_error = '0') then @@ -1484,7 +1591,7 @@ begin else R_STATE <= R_WAIT_DATA_HANDLER_OK; end if; - debug_state <= x"8"; + debug_state <= x"b"; end case; end if; end if; @@ -1559,7 +1666,8 @@ begin reset_handler_start_r <= '0'; adc_bit_shift <= x"0"; adc_debug_type <= (others => '0'); - debug_mode <= (others => '0'); + debug_mode <= (others => '0'); + disable_adc_r <= '0'; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -1595,7 +1703,8 @@ begin when x"0004" => slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate); - slv_data_out_o(31 downto 28) <= (others => '0'); + slv_data_out_o(30 downto 28) <= (others => '0'); + slv_data_out_o(31) <= disable_adc_r; slv_ack_o <= '1'; when x"0005" => @@ -1718,9 +1827,10 @@ begin reset_handler_start_r <= '1'; slv_ack_o <= '1'; - when x"0002" => + when x"0004" => + disable_adc_r <= SLV_DATA_IN(31); slv_ack_o <= '1'; - + when x"000a" => reset_resync_ctr <= '1'; slv_ack_o <= '1'; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index cf04fd7..63f20e1 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -647,12 +647,10 @@ begin slv_data_out_o(0) <= adc_tr_debug_mode; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - slv_ack_o <= '1'; when x"0010" => slv_data_out_o <= nx_trigger_ctr_t_nr; slv_ack_o <= '1'; - slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; diff --git a/nxyter/source/nx_fpga_timestamp.vhd b/nxyter/source/nx_fpga_timestamp.vhd index 5db6dbd..5726338 100644 --- a/nxyter/source/nx_fpga_timestamp.vhd +++ b/nxyter/source/nx_fpga_timestamp.vhd @@ -11,8 +11,7 @@ entity nx_fpga_timestamp is RESET_IN : in std_logic; NX_MAIN_CLK_IN : in std_logic; - TIMESTAMP_RESET_1_IN : in std_logic; - TIMESTAMP_RESET_2_IN : in std_logic; + TIMESTAMP_RESET_IN : in std_logic; TIMESTAMP_RESET_OUT : out std_logic; TRIGGER_IN : in std_logic; -- must be in NX_MAIN_CLK_DOMAIN TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); @@ -34,26 +33,32 @@ end entity; architecture Behavioral of nx_fpga_timestamp is - signal timestamp_reset_1_ff : std_logic; - signal timestamp_reset_1_f : std_logic; - signal timestamp_reset_1 : std_logic; - signal timestamp_reset_2_ff : std_logic; - signal timestamp_reset_2_f : std_logic; - signal timestamp_reset_2 : std_logic; + signal timestamp_reset_ff : std_logic; + signal timestamp_reset_f : std_logic; + signal timestamp_reset : std_logic; signal timestamp_ctr : unsigned(11 downto 0); signal timestamp_hold_o : std_logic_vector(11 downto 0); signal timestamp_trigger_o : std_logic; - signal timestamp_sync_o : std_logic; + signal timestamp_sync_o : std_logic; -- Reset - signal RESET_NX_MAIN_CLK_IN : std_logic; + signal reset_nx_main_clk_in_ff : std_logic; + signal reset_nx_main_clk_in_f : std_logic; + signal RESET_NX_MAIN_CLK_IN : std_logic; + + attribute syn_keep : boolean; + attribute syn_keep of reset_nx_main_clk_in_ff : signal is true; + attribute syn_keep of reset_nx_main_clk_in_f : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of reset_nx_main_clk_in_ff : signal is true; + attribute syn_preserve of reset_nx_main_clk_in_f : signal is true; begin - DEBUG_OUT(0) <= NX_MAIN_CLK_IN; - DEBUG_OUT(1) <= TIMESTAMP_RESET_1_IN; - DEBUG_OUT(2) <= TIMESTAMP_RESET_2_IN; + DEBUG_OUT(1) <= TIMESTAMP_RESET_IN; + DEBUG_OUT(2) <= timestamp_reset; DEBUG_OUT(3) <= TIMESTAMP_RESET_OUT; DEBUG_OUT(4) <= TRIGGER_IN; DEBUG_OUT(15 downto 5) <= timestamp_hold_o(10 downto 0); @@ -61,43 +66,36 @@ begin ----------------------------------------------------------------------------- -- Reset Domain Transfer ----------------------------------------------------------------------------- - signal_async_trans_RESET_IN: signal_async_trans - port map ( - CLK_IN => NX_MAIN_CLK_IN, - SIGNAL_A_IN => RESET_IN, - SIGNAL_OUT => RESET_NX_MAIN_CLK_IN - ); - + reset_nx_main_clk_in_ff <= RESET_IN when rising_edge(NX_MAIN_CLK_IN); + reset_nx_main_clk_in_f <= reset_nx_main_clk_in_ff + when rising_edge(NX_MAIN_CLK_IN); + RESET_NX_MAIN_CLK_IN <= reset_nx_main_clk_in_f + when rising_edge(NX_MAIN_CLK_IN); + ----------------------------------------------------------------------------- -- NX Clock Domain ----------------------------------------------------------------------------- -- Timestamp Process + Trigger + timestamp_reset_ff <= TIMESTAMP_RESET_IN + when rising_edge(NX_MAIN_CLK_IN); + timestamp_reset_f <= timestamp_reset_ff + when rising_edge(NX_MAIN_CLK_IN); + timestamp_reset <= timestamp_reset_f + when rising_edge(NX_MAIN_CLK_IN); + PROC_TIMESTAMP_CTR: process (NX_MAIN_CLK_IN) begin if (rising_edge(NX_MAIN_CLK_IN)) then - timestamp_reset_1_ff <= TIMESTAMP_RESET_1_IN; - timestamp_reset_2_ff <= TIMESTAMP_RESET_2_IN; - if (RESET_NX_MAIN_CLK_IN = '1') then - timestamp_reset_1_f <= '0'; - timestamp_reset_2_f <= '0'; - timestamp_reset_1 <= '0'; - timestamp_reset_2 <= '0'; - timestamp_ctr <= (others => '0'); timestamp_hold_o <= (others => '0'); timestamp_sync_o <= '0'; else - timestamp_reset_1_f <= timestamp_reset_1_ff; - timestamp_reset_1 <= timestamp_reset_1_f; - timestamp_reset_2_f <= timestamp_reset_2_ff; - timestamp_reset_2 <= timestamp_reset_2_f; timestamp_trigger_o <= '1'; timestamp_sync_o <= '0'; - if ((timestamp_reset_1 = '0' and timestamp_reset_1_f = '1') or - (timestamp_reset_2 = '0' and timestamp_reset_2_f = '1'))then + if ((timestamp_reset = '0' and timestamp_reset_f = '1')) then timestamp_ctr <= (others => '0'); timestamp_sync_o <= '1'; else diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd index 1760c4e..7ba74b0 100644 --- a/nxyter/source/nx_histograms.vhd +++ b/nxyter/source/nx_histograms.vhd @@ -312,7 +312,7 @@ begin adc_read_id <= (others => '0'); adc_read <= '0'; - adc_num_averages <= "001"; + adc_num_averages <= (others => '0'); adc_average_enable <= '1'; pileup_read_id <= (others => '0'); diff --git a/nxyter/source/nx_status.vhd b/nxyter/source/nx_status.vhd index 3ec8d8b..364bea7 100644 --- a/nxyter/source/nx_status.vhd +++ b/nxyter/source/nx_status.vhd @@ -19,7 +19,6 @@ entity nx_status is -- Signals I2C_SM_RESET_OUT : inout std_logic; I2C_REG_RESET_OUT : out std_logic; - NX_TS_RESET_OUT : out std_logic; NX_ONLINE_OUT : out std_logic; -- Error @@ -49,27 +48,22 @@ architecture Behavioral of nx_status is signal i2c_sm_online_ctr : unsigned(8 downto 0); signal offline_force : std_logic; - signal online_o : std_logic; - signal online_trigger : std_logic; - signal online_last : std_logic; + signal online_o : std_logic; + signal online_trigger : std_logic; + signal online_last : std_logic; -- Reset Handler signal i2c_sm_reset_start : std_logic; signal i2c_reg_reset_start : std_logic; - signal nx_ts_reset_start : std_logic; signal i2c_sm_reset_o : std_logic; signal i2c_reg_reset_o : std_logic; - signal nx_ts_reset_o : std_logic; - type STATES is (S_IDLE, S_I2C_SM_RESET, S_I2C_SM_RESET_WAIT, S_I2C_REG_RESET, - S_I2C_REG_RESET_WAIT, - S_NX_TS_RESET, - S_NX_TS_RESET_WAIT + S_I2C_REG_RESET_WAIT ); signal STATE : STATES; @@ -93,6 +87,7 @@ architecture Behavioral of nx_status is signal pll_adc_sclk_notlock_ctr : unsigned(15 downto 0); signal clear_notlock_counters : std_logic; + signal pll_reset_p : std_logic; signal pll_reset_o : std_logic; -- Nxyter Data Clock @@ -104,14 +99,13 @@ architecture Behavioral of nx_status is signal slv_no_more_data_o : std_logic; signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal nx_ts_reset_start_r : std_logic; begin DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= i2c_sm_reset_o; DEBUG_OUT(2) <= i2c_reg_reset_o; - DEBUG_OUT(3) <= nx_ts_reset_o; + DEBUG_OUT(3) <= '0'; DEBUG_OUT(4) <= PLL_NX_CLK_LOCK_IN; DEBUG_OUT(5) <= pll_nx_clk_lock; DEBUG_OUT(6) <= PLL_ADC_DCLK_LOCK_IN; @@ -185,10 +179,12 @@ begin online_o <= '1'; online_last <= '0'; else - if (i2c_sm_online = '0' or offline_force = '1') then - online_o <= '0'; - else + if (i2c_sm_online = '1' and + offline_force = '0' and + pll_nx_clk_lock = '1') then online_o <= '1'; + else + online_o <= '0'; end if; -- Offline State changes @@ -213,24 +209,18 @@ begin PROC_I2C_SM_RESET: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then - nx_ts_reset_start <= nx_ts_reset_start_r; if( RESET_IN = '1' ) then wait_timer_start <= '0'; i2c_sm_reset_o <= '0'; - i2c_reg_reset_o <= '0'; - nx_ts_reset_o <= '0'; STATE <= S_IDLE; else i2c_sm_reset_o <= '0'; i2c_reg_reset_o <= '0'; - nx_ts_reset_o <= '0'; wait_timer_start <= '0'; case STATE is when S_IDLE => - if (nx_ts_reset_start = '1') then - STATE <= S_NX_TS_RESET; - elsif (i2c_sm_reset_start = '1') then + if (i2c_sm_reset_start = '1') then STATE <= S_I2C_SM_RESET; elsif (i2c_reg_reset_start = '1') then STATE <= S_I2C_REG_RESET; @@ -266,20 +256,6 @@ begin STATE <= S_IDLE; end if; - when S_NX_TS_RESET => - nx_ts_reset_o <= '1'; - wait_timer_init <= x"01"; - wait_timer_start <= '1'; - STATE <= S_NX_TS_RESET_WAIT; - - when S_NX_TS_RESET_WAIT => - nx_ts_reset_o <= '1'; - if (wait_timer_done = '0') then - STATE <= S_NX_TS_RESET_WAIT; - else - STATE <= S_IDLE; - end if; - end case; end if; end if; @@ -378,21 +354,19 @@ begin slv_ack_o <= '0'; i2c_sm_reset_start <= '0'; i2c_reg_reset_start <= '0'; - nx_ts_reset_start_r <= '0'; offline_force <= '0'; nx_data_clk_dphase_o <= x"7"; nx_data_clk_finedelb_o <= x"0"; clear_notlock_counters <= '0'; - pll_reset_o <= '0'; + pll_reset_p <= '0'; else slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; slv_data_out_o <= (others => '0'); i2c_sm_reset_start <= '0'; i2c_reg_reset_start <= '0'; - nx_ts_reset_start_r <= '0'; clear_notlock_counters <= '0'; - pll_reset_o <= '0'; + pll_reset_p <= '0'; if (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is @@ -405,7 +379,6 @@ begin slv_ack_o <= '1'; when x"0002" => - nx_ts_reset_start_r <= '1'; slv_ack_o <= '1'; when x"0003" => @@ -413,7 +386,7 @@ begin slv_ack_o <= '1'; when x"0006" => - pll_reset_o <= '1'; + pll_reset_p <= '1'; slv_ack_o <= '1'; when x"000a" => @@ -494,6 +467,17 @@ begin end if; end process PROC_NX_REGISTERS; + ----------------------------------------------------------------------------- + pulse_to_level_1: pulse_to_level + generic map ( + NUM_CYCLES => 15) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + PULSE_IN => pll_reset_p, + LEVEL_OUT => pll_reset_o + ); + -- Output Signals i2c_sm_reset_i_x <= I2C_SM_RESET_OUT; @@ -505,7 +489,6 @@ begin PLL_RESET_OUT <= pll_reset_o; I2C_SM_RESET_OUT <= '0' when i2c_sm_reset_o = '1' else 'Z'; I2C_REG_RESET_OUT <= not i2c_reg_reset_o; - NX_TS_RESET_OUT <= nx_ts_reset_o; NX_ONLINE_OUT <= online_o; end Behavioral; diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 2461a6e..947675c 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -9,7 +9,6 @@ entity nx_trigger_generator is port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_MAIN_CLK_IN : in std_logic; TRIGGER_BUSY_IN : in std_logic; EXTERNAL_TRIGGER_OUT : out std_logic; @@ -82,13 +81,10 @@ architecture Behavioral of nx_trigger_generator is signal slv_ack_o : std_logic; signal pulser_trigger_period_r : unsigned(27 downto 0); - -- Reset - signal RESET_NX_MAIN_CLK_IN : std_logic; - begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= NX_MAIN_CLK_IN; + DEBUG_OUT(1) <= '0'; DEBUG_OUT(2) <= DATA_CLK_IN; DEBUG_OUT(3) <= TRIGGER_BUSY_IN; @@ -107,16 +103,6 @@ begin DEBUG_OUT(13) <= trigger; DEBUG_OUT(15 downto 14) <= (others => '0'); - ----------------------------------------------------------------------------- - -- Reset Domain Transfer - ----------------------------------------------------------------------------- - signal_async_trans_RESET_IN: signal_async_trans - port map ( - CLK_IN => NX_MAIN_CLK_IN, - SIGNAL_A_IN => RESET_IN, - SIGNAL_OUT => RESET_NX_MAIN_CLK_IN - ); - ----------------------------------------------------------------------------- -- Generate Pulser Trigger ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index 6c964e7..9b7d8a9 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -91,7 +91,12 @@ architecture Behavioral of nx_trigger_handler is signal invalid_timing_trigger : std_logic; signal invalid_timing_trigger_ctr : unsigned(15 downto 0); + signal trigger_busy_ff : std_logic; + signal trigger_busy_f : std_logic; signal trigger_busy : std_logic; + + signal fast_clear_ff : std_logic; + signal fast_clear_f : std_logic; signal fast_clear : std_logic; type TS_STATES is (TS_IDLE, @@ -180,10 +185,33 @@ architecture Behavioral of nx_trigger_handler is signal testpulse_rate : unsigned(27 downto 0); signal invalid_t_trigger_ctr_clear : std_logic; signal bypass_ctr_trigger : std_logic; + signal bypass_status_trigger : std_logic; -- Reset + signal reset_nx_main_clk_in_ff : std_logic; + signal reset_nx_main_clk_in_f : std_logic; signal RESET_NX_MAIN_CLK_IN : std_logic; + + attribute syn_keep : boolean; + attribute syn_keep of reset_nx_main_clk_in_ff : signal is true; + attribute syn_keep of reset_nx_main_clk_in_f : signal is true; + + attribute syn_keep of trigger_busy_ff : signal is true; + attribute syn_keep of trigger_busy_f : signal is true; + + attribute syn_keep of fast_clear_ff : signal is true; + attribute syn_keep of fast_clear_f : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of reset_nx_main_clk_in_ff : signal is true; + attribute syn_preserve of reset_nx_main_clk_in_f : signal is true; + + attribute syn_preserve of trigger_busy_ff : signal is true; + attribute syn_preserve of trigger_busy_f : signal is true; + + attribute syn_preserve of fast_clear_ff : signal is true; + attribute syn_preserve of fast_clear_f : signal is true; + begin -- Debug Line @@ -207,13 +235,13 @@ begin ----------------------------------------------------------------------------- -- Reset Domain Transfer ----------------------------------------------------------------------------- - signal_async_trans_RESET_IN: signal_async_trans - port map ( - CLK_IN => NX_MAIN_CLK_IN, - SIGNAL_A_IN => RESET_IN, - SIGNAL_OUT => RESET_NX_MAIN_CLK_IN - ); + reset_nx_main_clk_in_ff <= RESET_IN when rising_edge(NX_MAIN_CLK_IN); + reset_nx_main_clk_in_f <= reset_nx_main_clk_in_ff + when rising_edge(NX_MAIN_CLK_IN); + RESET_NX_MAIN_CLK_IN <= reset_nx_main_clk_in_f + when rising_edge(NX_MAIN_CLK_IN); + ----------------------------------------------------------------------------- -- Trigger Handler ----------------------------------------------------------------------------- @@ -266,11 +294,27 @@ begin TIMER_DONE_OUT => ts_wait_timer_done ); + + -- Signal Domain Transfers to NX Clock + trigger_busy_ff <= trigger_busy_o + when rising_edge(NX_MAIN_CLK_IN); + trigger_busy_f <= trigger_busy_ff + when rising_edge(NX_MAIN_CLK_IN); + trigger_busy <= trigger_busy_f + when rising_edge(NX_MAIN_CLK_IN); + + fast_clear_ff <= fast_clear_o + when rising_edge(NX_MAIN_CLK_IN); + fast_clear_f <= fast_clear_ff + when rising_edge(NX_MAIN_CLK_IN); + fast_clear <= fast_clear_f + when rising_edge(NX_MAIN_CLK_IN); + + testpulse_enable <= reg_testpulse_enable when rising_edge(NX_MAIN_CLK_IN); + PROC_TIMING_TRIGGER_HANDLER: process(NX_MAIN_CLK_IN) begin if( rising_edge(NX_MAIN_CLK_IN) ) then - testpulse_enable <= reg_testpulse_enable; - if (RESET_NX_MAIN_CLK_IN = '1') then invalid_timing_trigger_n <= '1'; ts_wait_timer_start <= '0'; @@ -355,29 +399,12 @@ begin end if; end process PROC_TIMING_TRIGGER_COUNTER; - signal_async_trans_TRIGGER_BUSY: signal_async_trans - port map ( - CLK_IN => NX_MAIN_CLK_IN, - SIGNAL_A_IN => trigger_busy_o, - SIGNAL_OUT => trigger_busy - ); - - signal_async_to_pulse_FAST_CLEAR: signal_async_to_pulse - generic map ( - NUM_FF => 2 - ) - port map ( - CLK_IN => NX_MAIN_CLK_IN, - RESET_IN => RESET_NX_MAIN_CLK_IN, - PULSE_A_IN => fast_clear_o, - PULSE_OUT => fast_clear - ); - -- Relax Timing - invalid_timing_trigger_ff <= - invalid_timing_trigger_n when rising_edge(NX_MAIN_CLK_IN); - invalid_timing_trigger_f <= - invalid_timing_trigger_ff when rising_edge(NX_MAIN_CLK_IN); + invalid_timing_trigger_ff <= invalid_timing_trigger_n + when rising_edge(NX_MAIN_CLK_IN); + invalid_timing_trigger_f <= invalid_timing_trigger_ff + when rising_edge(NX_MAIN_CLK_IN); + pulse_dtrans_INVALID_TIMING_TRIGGER: pulse_dtrans generic map ( CLK_RATIO => 4 @@ -427,7 +454,8 @@ begin when S_IDLE => if (LVL1_VALID_NOTIMING_TRG_IN = '1') then -- Calibration Trigger - if (LVL1_TRG_TYPE_IN = x"e") then + if (LVL1_TRG_TYPE_IN = x"e" and + bypass_status_trigger = '0') then -- Status Trigger TRIGGER_TYPE <= T_SETUP; status_trigger_o <= '1'; @@ -438,14 +466,15 @@ begin STATE <= S_WAIT_TRG_DATA_VALID; elsif (LVL1_VALID_TIMING_TRG_IN = '1') then - if (NXYTER_OFFLINE_IN = '1' or bypass_ctr_trigger = '1') then - -- Ignore Trigger for nxyter is or pretends to be offline - TRIGGER_TYPE <= T_IGNORE; - STATE <= S_WAIT_TRG_DATA_VALID; - else + if (NXYTER_OFFLINE_IN = '0' and + bypass_ctr_trigger = '0') then -- Normal Trigger TRIGGER_TYPE <= T_TIMING; STATE <= S_CTS_TRIGGER; + else + -- Ignore Trigger for nxyter is or pretends to be offline + TRIGGER_TYPE <= T_IGNORE; + STATE <= S_WAIT_TRG_DATA_VALID; end if; else trigger_busy_o <= '0'; @@ -540,13 +569,13 @@ begin TIMER_END_IN => wait_timer_end, TIMER_DONE_OUT => wait_timer_done ); - + + testpulse_delay <= reg_testpulse_delay when rising_edge(NX_MAIN_CLK_IN); + testpulse_length <= reg_testpulse_length when rising_edge(NX_MAIN_CLK_IN); + PROC_TESTPULSE_HANDLER: process (NX_MAIN_CLK_IN) begin if( rising_edge(NX_MAIN_CLK_IN) ) then - testpulse_delay <= reg_testpulse_delay; - testpulse_length <= reg_testpulse_length; - if (RESET_NX_MAIN_CLK_IN = '1') then wait_timer_start <= '0'; wait_timer_reset <= '1'; @@ -667,6 +696,7 @@ begin reg_testpulse_enable <= '0'; invalid_t_trigger_ctr_clear <= '1'; bypass_ctr_trigger <= '0'; + bypass_status_trigger <= '0'; else slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; @@ -696,6 +726,7 @@ begin when x"0006" => bypass_ctr_trigger <= SLV_DATA_IN(0); + bypass_status_trigger <= SLV_DATA_IN(1); slv_ack_o <= '1'; when others => @@ -743,7 +774,8 @@ begin when x"0006" => slv_data_out_o(0) <= bypass_ctr_trigger; - slv_data_out_o(31 downto 1) <= (others => '0'); + slv_data_out_o(1) <= bypass_status_trigger; + slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; when others => diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 8c1b311..82a273f 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -190,6 +190,10 @@ architecture Behavioral of nx_trigger_validate is signal readout_mode_r : std_logic_vector(3 downto 0); signal histogram_trigger_all_r : std_logic; signal out_of_window_error_ctr_clear : std_logic; + + signal histogram_limits : std_logic; + signal histogram_lower_limit : unsigned(13 downto 0); + signal histogram_upper_limit : unsigned(13 downto 0); -- Timestamp Trigger Window Settings signal nxyter_cv_time : unsigned(11 downto 0); @@ -415,13 +419,23 @@ begin -- Fill Histogram if (histogram_trigger_all = '0') then - histogram_fill_o <= '1'; - histogram_bin_o <= CHANNEL_IN; - histogram_adc_o <= ADC_DATA_IN; - histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); - histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); + if (histogram_limits = '1') then + if (deltaTStore >= histogram_lower_limit and + deltaTStore <= histogram_upper_limit) then + histogram_fill_o <= '1'; + histogram_bin_o <= CHANNEL_IN; + histogram_adc_o <= ADC_DATA_IN; + histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); + histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); + end if; + else + histogram_fill_o <= '1'; + histogram_bin_o <= CHANNEL_IN; + histogram_adc_o <= ADC_DATA_IN; + histogram_pileup_o <= TIMESTAMP_STATUS_IN(S_PILEUP); + histogram_ovfl_o <= TIMESTAMP_STATUS_IN(S_OVFL); + end if; end if; - end if; if (out_of_window_error_ctr_clear = '1') then @@ -585,7 +599,7 @@ begin -- Wait for Data and minimum Validation Time calculation min_validation_time := resize(ts_window_width * 4, 20); wait_for_data_time := - resize(nxyter_cv_time, 20) + data_fifo_delay_o * 32 + 320; + resize(nxyter_cv_time, 20) + data_fifo_delay_o * 32 + 280; --320; if (skip_wait_for_data = '1') then min_validation_time := @@ -1076,9 +1090,13 @@ begin slv_ack_o <= '1'; when x"001f" => - slv_data_out_o <= - std_logic_vector(data_rate_ctr_nr); - slv_data_out_o(31 downto 28) <= (others => '0'); + slv_data_out_o(13 downto 0) <= + std_logic_vector(histogram_lower_limit); + slv_data_out_o(15 downto 14) <= (others => '0'); + slv_data_out_o(29 downto 16) <= + std_logic_vector(histogram_upper_limit); + slv_data_out_o(30) <= '0'; + slv_data_out_o(31) <= histogram_limits; slv_ack_o <= '1'; when others => @@ -1137,6 +1155,12 @@ begin unsigned(SLV_DATA_IN(11 downto 0)); slv_ack_o <= '1'; + when x"001f" => + histogram_lower_limit <= SLV_DATA_IN(13 downto 0); + histogram_upper_limit <= SLV_DATA_IN(29 downto 16); + histogram_limits <= SLV_DATA_IN(31); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 5b02221..9b85b5d 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -346,7 +346,6 @@ component nx_status PLL_RESET_OUT : out std_logic; I2C_SM_RESET_OUT : inout std_logic; I2C_REG_RESET_OUT : out std_logic; - NX_TS_RESET_OUT : out std_logic; NX_ONLINE_OUT : out std_logic; ERROR_ALL_IN : in std_logic_vector(7 downto 0); SLV_READ_IN : in std_logic; @@ -449,6 +448,7 @@ component nx_data_receiver CLK_IN : in std_logic; RESET_IN : in std_logic; TRIGGER_IN : in std_logic; + NX_ONLINE_IN : in std_logic; NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_TIMESTAMP_RESET_OUT : out std_logic; @@ -849,8 +849,7 @@ component nx_fpga_timestamp CLK_IN : in std_logic; RESET_IN : in std_logic; NX_MAIN_CLK_IN : in std_logic; - TIMESTAMP_RESET_1_IN : in std_logic; - TIMESTAMP_RESET_2_IN : in std_logic; + TIMESTAMP_RESET_IN : in std_logic; TIMESTAMP_RESET_OUT : out std_logic; TRIGGER_IN : in std_logic; TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); @@ -918,7 +917,6 @@ component nx_trigger_generator port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_MAIN_CLK_IN : in std_logic; TRIGGER_BUSY_IN : in std_logic; EXTERNAL_TRIGGER_OUT : out std_logic; INTERNAL_TRIGGER_OUT : out std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 9522a02..1116413 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -115,8 +115,7 @@ architecture Behavioral of nXyter_FEE_board is signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); -- TRB Register - signal nx_timestamp_reset_status : std_logic; - signal nx_timestamp_reset_receiver : std_logic; + signal nx_timestamp_reset : std_logic; signal nx_timestamp_reset_o : std_logic; signal i2c_reg_reset_o : std_logic; signal nxyter_online : std_logic; @@ -321,7 +320,6 @@ begin I2C_SM_RESET_OUT => I2C_SM_RESET_OUT, I2C_REG_RESET_OUT => i2c_reg_reset_o, - NX_TS_RESET_OUT => nx_timestamp_reset_status, NX_ONLINE_OUT => nxyter_online, ERROR_ALL_IN => error_all, @@ -437,8 +435,7 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, - TIMESTAMP_RESET_1_IN => '0', --nx_timestamp_reset_status, - TIMESTAMP_RESET_2_IN => nx_timestamp_reset_receiver, + TIMESTAMP_RESET_IN => nx_timestamp_reset, TIMESTAMP_RESET_OUT => nx_timestamp_reset_o, TRIGGER_IN => timestamp_trigger, TIMESTAMP_HOLD_OUT => timestamp_hold, @@ -522,7 +519,6 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, TRIGGER_BUSY_IN => trigger_busy, EXTERNAL_TRIGGER_OUT => TRIGGER_OUT, @@ -555,10 +551,11 @@ begin CLK_IN => CLK_IN, RESET_IN => RESET_IN, TRIGGER_IN => trigger_timing, - + NX_ONLINE_IN => nxyter_online, + NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset_receiver, + NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset, ADC_CLK_DAT_IN => CLK_ADC_IN, ADC_FCLK_IN => ADC_FCLK_IN, diff --git a/nxyter/source/signal_async_to_pulse.vhd b/nxyter/source/signal_async_to_pulse.vhd index 9de1fae..f10d88c 100644 --- a/nxyter/source/signal_async_to_pulse.vhd +++ b/nxyter/source/signal_async_to_pulse.vhd @@ -24,6 +24,12 @@ architecture Behavioral of signal_async_to_pulse is signal pulse_ff : std_logic_vector(NUM_FF - 1 downto 0); signal pulse_o : std_logic; + attribute syn_keep : boolean; + attribute syn_keep of pulse_ff : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of pulse_ff : signal is true; + begin ----------------------------------------------------------------------------- diff --git a/nxyter/source/signal_async_trans.vhd b/nxyter/source/signal_async_trans.vhd index c5cf79b..ce8d143 100644 --- a/nxyter/source/signal_async_trans.vhd +++ b/nxyter/source/signal_async_trans.vhd @@ -19,6 +19,12 @@ architecture Behavioral of signal_async_trans is signal signal_ff : signal_ff_t; + attribute syn_keep : boolean; + attribute syn_keep of signal_ff : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of signal_ff : signal is true; + begin ----------------------------------------------------------------------------- diff --git a/nxyter/trb3_periph.p2t b/nxyter/trb3_periph.p2t deleted file mode 100644 index 2968146..0000000 --- a/nxyter/trb3_periph.p2t +++ /dev/null @@ -1,20 +0,0 @@ --w --i 15 --l 5 --n 1 --y --s 12 --t 69 --c 1 --e 2 --m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/nxyter/trb3_periph.p2t b/nxyter/trb3_periph.p2t new file mode 120000 index 0000000..c93d3a2 --- /dev/null +++ b/nxyter/trb3_periph.p2t @@ -0,0 +1 @@ +trb3_periph_multi.p2t \ No newline at end of file diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 3d02dd7..adbc78c 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -59,40 +59,38 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLI # Relax some of the timing constraints ################################################################# -#BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*"; - -MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns; - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_sync_o*" 10 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns; +################################################# +# Muelleimer: +# #LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ; +# +################################################# -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/signal_async_trans_RESET_IN/*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns; +#BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*"; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_RESET_IN/*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/signal_async_trans_TRIGGER_BUSY/*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_o" 30 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns; +MULTICYCLE to CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns; - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/signal_async_trans_RESET_IN/*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/output_handler_reset*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns; + +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*" 30 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*" 10 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_sync_o*" 10 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns; + +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/error_adc0_ff*" 30 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_r*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_rnx_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; @@ -107,6 +105,16 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_notlock_ctr_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_r*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_n*" 100 ns; + +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns; + +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns; @@ -119,7 +127,7 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; ################################################################# # look at .par and .twr.setup file for clocks -# and .mrp or errors +# IN .mrp you find the semantic errors #PROHIBIT PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; #PROHIBIT SECONDARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; @@ -132,15 +140,14 @@ PROHIBIT SECONDARY NET "NX1_DATA_CLK_*"; #PROHIBIT SECONDARY NET "NX2_DATA_CLK_*"; DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_DATA_CLK_IN"; +INPUT_SETUP GROUP "NX1_IN" 1.0 ns HOLD 1.0 ns CLKPORT="NX1_DATA_CLK_IN"; #DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*"; -#INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_DATA_CLK_IN"; +#INPUT_SETUP GROUP "NX2_IN" 2.0 ns HOLD 2.0 ns CLKPORT="NX2_DATA_CLK_IN"; UGROUP NXYTER1 BBOX 76 58 BLKNAME nXyter_FEE_board_0; - LOCATE UGROUP NXYTER1 SITE "R28C2D"; -#LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ; + LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R61C5" ; -- 2.43.0