From 5f0479c8fde57128131913d0b227c8ffd50a0dae Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 19 Sep 2014 16:45:34 +0200 Subject: [PATCH] changed SED checker to use new record based control bus interface --- 32PinAddOn/trb3_periph_32PinAddOn.vhd | 47 +++++--------- ADA_Addon/trb3_periph_ADA.vhd | 88 +++++---------------------- base/code/sedcheck.vhd | 39 ++++++------ cbmtof/cbmtof.vhd | 57 ++++++----------- gpin/trb3_periph_gpin.vhd | 49 +++++---------- hadesstart/trb3_periph_hadesstart.vhd | 39 +++++------- nxyter/trb3_periph_nx1.vhd | 44 +++++--------- wasa/trb3_periph_padiwa.vhd | 57 ++++++----------- 8 files changed, 130 insertions(+), 290 deletions(-) diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd index c1f55f4..db8ddd7 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -278,13 +278,8 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; --TDC signal hit_in_i : std_logic_vector(64 downto 1); @@ -629,16 +624,16 @@ begin BUS_NO_MORE_DATA_IN(7) => '0', BUS_UNKNOWN_ADDR_IN(7) => stat_nack, --SEU Detection - BUS_READ_ENABLE_OUT(8) => sed_read, - BUS_WRITE_ENABLE_OUT(8) => sed_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => sed_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => sed_addr, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => sed_dout, - BUS_DATAREADY_IN(8) => sed_ack, - BUS_WRITE_ACK_IN(8) => sed_ack, - BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => sed_nack, + BUS_READ_ENABLE_OUT(8) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(8) => bussed_rx.write, + BUS_DATA_OUT(8*32+31 downto 8*32) => bussed_rx.data, + BUS_ADDR_OUT(8*16+15 downto 8*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(8) => bussed_rx.timeout, + BUS_DATA_IN(8*32+31 downto 8*32) => bussed_tx.data, + BUS_DATAREADY_IN(8) => bussed_tx.ack, + BUS_WRITE_ACK_IN(8) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(8) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(8) => bussed_tx.unknown, --Channel Debug Registers BUS_READ_ENABLE_OUT(9) => cdb_read_en, BUS_WRITE_ENABLE_OUT(9) => cdb_write_en, @@ -849,24 +844,10 @@ begin port map( CLK => clk_100_i, ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr + BUS_RX => bussed_rx, + BUS_TX => bussed_tx ); --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); - --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- diff --git a/ADA_Addon/trb3_periph_ADA.vhd b/ADA_Addon/trb3_periph_ADA.vhd index ea69565..bbe970e 100644 --- a/ADA_Addon/trb3_periph_ADA.vhd +++ b/ADA_Addon/trb3_periph_ADA.vhd @@ -277,13 +277,8 @@ architecture trb3_periph_ADA_arch of trb3_periph_ADA is signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; --TDC signal hit_in_i : std_logic_vector(64 downto 1); @@ -665,16 +660,16 @@ begin BUS_NO_MORE_DATA_IN(6) => '0', BUS_UNKNOWN_ADDR_IN(6) => trig_nack, --SEU Detection - BUS_READ_ENABLE_OUT(7) => sed_read, - BUS_WRITE_ENABLE_OUT(7) => sed_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => sed_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => sed_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => sed_dout, - BUS_DATAREADY_IN(7) => sed_ack, - BUS_WRITE_ACK_IN(7) => sed_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => sed_nack, + BUS_READ_ENABLE_OUT(7) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(7) => bussed_rx.write, + BUS_DATA_OUT(7*32+31 downto 7*32) => bussed_rx.data, + BUS_ADDR_OUT(7*16+15 downto 7*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(7) => bussed_rx.timeout, + BUS_DATA_IN(7*32+31 downto 7*32) => bussed_tx.data, + BUS_DATAREADY_IN(7) => bussed_tx.ack, + BUS_WRITE_ACK_IN(7) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(7) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(7) => bussed_tx.unknown, --Channel Debug Registers BUS_READ_ENABLE_OUT(8) => cdb_read_en, BUS_WRITE_ENABLE_OUT(8) => cdb_write_en, @@ -709,53 +704,6 @@ begin -- SPI / Flash --------------------------------------------------------------------------- - --THE_SPI_MASTER : spi_master - -- port map( - -- CLK_IN => clk_100_i, - -- RESET_IN => reset_i, - -- -- Slave bus - -- BUS_READ_IN => spictrl_read_en, - -- BUS_WRITE_IN => spictrl_write_en, - -- BUS_BUSY_OUT => spictrl_busy, - -- BUS_ACK_OUT => spictrl_ack, - -- BUS_ADDR_IN(0) => spictrl_addr, - -- BUS_DATA_IN => spictrl_data_in, - -- BUS_DATA_OUT => spictrl_data_out, - -- -- SPI connections - -- SPI_CS_OUT => FLASH_CS, - -- SPI_SDI_IN => FLASH_DOUT, - -- SPI_SDO_OUT => FLASH_DIN, - -- SPI_SCK_OUT => FLASH_CLK, - -- -- BRAM for read/write data - -- BRAM_A_OUT => spi_bram_addr, - -- BRAM_WR_D_IN => spi_bram_wr_d, - -- BRAM_RD_D_OUT => spi_bram_rd_d, - -- BRAM_WE_OUT => spi_bram_we, - -- -- Status lines - -- STAT => open - -- ); - - ---- data memory for SPI accesses - --THE_SPI_MEMORY : spi_databus_memory - -- port map( - -- CLK_IN => clk_100_i, - -- RESET_IN => reset_i, - -- -- Slave bus - -- BUS_ADDR_IN => spimem_addr, - -- BUS_READ_IN => spimem_read_en, - -- BUS_WRITE_IN => spimem_write_en, - -- BUS_ACK_OUT => spimem_ack, - -- BUS_DATA_IN => spimem_data_in, - -- BUS_DATA_OUT => spimem_data_out, - -- -- state machine connections - -- BRAM_ADDR_IN => spi_bram_addr, - -- BRAM_WR_D_OUT => spi_bram_wr_d, - -- BRAM_RD_D_IN => spi_bram_rd_d, - -- BRAM_WE_IN => spi_bram_we, - -- -- Status lines - -- STAT => open - -- ); - THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload port map( CLK_IN => clk_100_i, @@ -871,16 +819,10 @@ begin port map( CLK => clk_100_i, ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr + BUS_RX => bussed_rx, + BUS_TX => bussed_tx ); - + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/base/code/sedcheck.vhd b/base/code/sedcheck.vhd index ce11075..419835e 100644 --- a/base/code/sedcheck.vhd +++ b/base/code/sedcheck.vhd @@ -2,19 +2,16 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library work; +use work.trb_net_std.all; entity sedcheck is port( CLK : in std_logic; ERROR_OUT : out std_logic; - DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_IN : in std_logic := '0'; - READ_IN : in std_logic := '0'; - ACK_OUT : out std_logic; - NACK_OUT : out std_logic; - ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0') + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX ); end entity; @@ -82,20 +79,22 @@ sed_error_q <= sed_error when rising_edge(CLK); --------------------------------------------------------------------------- proc_reg : process begin wait until rising_edge(CLK); - ACK_OUT <= '0'; - NACK_OUT <= '0'; - if WRITE_IN = '1' then - ACK_OUT <= '1'; - case ADDR_IN(1 downto 0) is - when "00" => control_i <= DATA_IN; - when others => ACK_OUT <= '0'; NACK_OUT <= '1'; + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => control_i <= BUS_RX.data; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; - elsif READ_IN = '1' then - ACK_OUT <= '1'; - case ADDR_IN(1 downto 0) is - when "00" => DATA_OUT <= control_i; - when "01" => DATA_OUT <= status_i; - when others => ACK_OUT <= '0'; NACK_OUT <= '1'; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => BUS_TX.data <= control_i; + when "01" => BUS_TX.data <= status_i; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; end if; end process; diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index ab623c8..cd3309e 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -281,13 +281,8 @@ architecture cbmtof_arch of cbmtof is signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; --FPGA Test signal time_counter : unsigned(31 downto 0); @@ -665,16 +660,16 @@ begin BUS_NO_MORE_DATA_IN(7) => '0', BUS_UNKNOWN_ADDR_IN(7) => stat_nack, --SEU Detection - BUS_READ_ENABLE_OUT(8) => sed_read, - BUS_WRITE_ENABLE_OUT(8) => sed_write, - BUS_DATA_OUT(8*32+31 downto 8*32) => sed_din, - BUS_ADDR_OUT(8*16+15 downto 8*16) => sed_addr, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATA_IN(8*32+31 downto 8*32) => sed_dout, - BUS_DATAREADY_IN(8) => sed_ack, - BUS_WRITE_ACK_IN(8) => sed_ack, - BUS_NO_MORE_DATA_IN(8) => '0', - BUS_UNKNOWN_ADDR_IN(8) => sed_nack, + BUS_READ_ENABLE_OUT(8) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(8) => bussed_rx.write, + BUS_DATA_OUT(8*32+31 downto 8*32) => bussed_rx.data, + BUS_ADDR_OUT(8*16+15 downto 8*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(8) => bussed_rx.timeout, + BUS_DATA_IN(8*32+31 downto 8*32) => bussed_tx.data, + BUS_DATAREADY_IN(8) => bussed_tx.ack, + BUS_WRITE_ACK_IN(8) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(8) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(8) => bussed_tx.unknown, STAT_DEBUG => open ); @@ -823,27 +818,13 @@ begin --------------------------------------------------------------------------- -- SED Detection --------------------------------------------------------------------------- -THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr - ); - --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => sed_error, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx + ); --------------------------------------------------------------------------- -- Reboot FPGA diff --git a/gpin/trb3_periph_gpin.vhd b/gpin/trb3_periph_gpin.vhd index 339fc20..9179c9d 100644 --- a/gpin/trb3_periph_gpin.vhd +++ b/gpin/trb3_periph_gpin.vhd @@ -276,15 +276,8 @@ architecture trb3_periph_gpin_arch of trb3_periph_gpin is signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); - - + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; --TDC signal hit_in_i : std_logic_vector(48 downto 1); @@ -616,16 +609,16 @@ begin BUS_NO_MORE_DATA_IN(6) => '0', BUS_UNKNOWN_ADDR_IN(6) => stat_nack, --SEU Detection - BUS_READ_ENABLE_OUT(7) => sed_read, - BUS_WRITE_ENABLE_OUT(7) => sed_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => sed_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => sed_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => sed_dout, - BUS_DATAREADY_IN(7) => sed_ack, - BUS_WRITE_ACK_IN(7) => sed_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => sed_nack, + BUS_READ_ENABLE_OUT(7) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(7) => bussed_rx.write, + BUS_DATA_OUT(7*32+31 downto 7*32) => bussed_rx.data, + BUS_ADDR_OUT(7*16+15 downto 7*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(7) => bussed_rx.timeout, + BUS_DATA_IN(7*32+31 downto 7*32) => bussed_tx.data, + BUS_DATAREADY_IN(7) => bussed_tx.ack, + BUS_WRITE_ACK_IN(7) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(7) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(7) => bussed_tx.unknown, --Channel Debug Registers BUS_READ_ENABLE_OUT(8) => cdb_read_en, BUS_WRITE_ENABLE_OUT(8) => cdb_write_en, @@ -802,24 +795,10 @@ begin port map( CLK => clk_100_i, ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr + BUS_RX => bussed_rx, + BUS_TX => bussed_tx ); --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); - --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd index a10a850..05ddfbf 100644 --- a/hadesstart/trb3_periph_hadesstart.vhd +++ b/hadesstart/trb3_periph_hadesstart.vhd @@ -268,13 +268,8 @@ architecture trb3_periph_hadesstart_arch of trb3_periph_hadesstart is signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; --TDC signal hit_in_i : std_logic_vector(64 downto 1); @@ -640,16 +635,16 @@ begin BUS_NO_MORE_DATA_IN(6) => '0', BUS_UNKNOWN_ADDR_IN(6) => trig_nack, --SEU Detection - BUS_READ_ENABLE_OUT(7) => sed_read, - BUS_WRITE_ENABLE_OUT(7) => sed_write, - BUS_DATA_OUT(7*32+31 downto 7*32) => sed_din, - BUS_ADDR_OUT(7*16+15 downto 7*16) => sed_addr, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATA_IN(7*32+31 downto 7*32) => sed_dout, - BUS_DATAREADY_IN(7) => sed_ack, - BUS_WRITE_ACK_IN(7) => sed_ack, - BUS_NO_MORE_DATA_IN(7) => '0', - BUS_UNKNOWN_ADDR_IN(7) => sed_nack, + BUS_READ_ENABLE_OUT(7) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(7) => bussed_rx.write, + BUS_DATA_OUT(7*32+31 downto 7*32) => bussed_rx.data, + BUS_ADDR_OUT(7*16+15 downto 7*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(7) => bussed_rx.timeout, + BUS_DATA_IN(7*32+31 downto 7*32) => bussed_tx.data, + BUS_DATAREADY_IN(7) => bussed_tx.ack, + BUS_WRITE_ACK_IN(7) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(7) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(7) => bussed_tx.unknown, --Channel Debug Registers BUS_READ_ENABLE_OUT(8) => cdb_read_en, BUS_WRITE_ENABLE_OUT(8) => cdb_write_en, @@ -800,14 +795,8 @@ begin port map( CLK => clk_100_i, ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr + BUS_RX => bussed_rx, + BUS_TX => bussed_tx ); --------------------------------------------------------------------------- diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nx1.vhd index 8b10ee8..fd150a6 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nx1.vhd @@ -257,13 +257,8 @@ architecture trb3_periph_arch of trb3_periph is -- SED Detection signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; @@ -566,16 +561,16 @@ begin BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out, BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out, - BUS_READ_ENABLE_OUT(3) => sed_read, - BUS_WRITE_ENABLE_OUT(3) => sed_write, - BUS_DATA_OUT(3*32+31 downto 3*32) => sed_din, - BUS_ADDR_OUT(3*16+15 downto 3*16) => sed_addr, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => sed_dout, - BUS_DATAREADY_IN(3) => sed_ack, - BUS_WRITE_ACK_IN(3) => sed_ack, - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => sed_nack, + BUS_READ_ENABLE_OUT(3) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(3) => bussed_rx.write, + BUS_DATA_OUT(3*32+31 downto 3*32) => bussed_rx.data, + BUS_ADDR_OUT(3*16+15 downto 3*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(3) => bussed_rx.timeout, + BUS_DATA_IN(3*32+31 downto 3*32) => bussed_tx.data, + BUS_DATAREADY_IN(3) => bussed_tx.ack, + BUS_WRITE_ACK_IN(3) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(3) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(3) => bussed_tx.unknown, STAT_DEBUG => open ); @@ -740,19 +735,12 @@ begin --------------------------------------------------------------------------- -- SED Detection --------------------------------------------------------------------------- - THE_SED : entity work.sedcheck port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr + CLK => clk_100_i, + ERROR_OUT => sed_error, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx ); ----------------------------------------------------------------------------- diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index b5b46cb..75db69e 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -299,13 +299,8 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; --TDC signal hit_in_i : std_logic_vector(64 downto 1); @@ -698,16 +693,16 @@ begin BUS_NO_MORE_DATA_IN(8) => '0', BUS_UNKNOWN_ADDR_IN(8) => stat_nack, --SEU Detection - BUS_READ_ENABLE_OUT(9) => sed_read, - BUS_WRITE_ENABLE_OUT(9) => sed_write, - BUS_DATA_OUT(9*32+31 downto 9*32) => sed_din, - BUS_ADDR_OUT(9*16+15 downto 9*16) => sed_addr, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATA_IN(9*32+31 downto 9*32) => sed_dout, - BUS_DATAREADY_IN(9) => sed_ack, - BUS_WRITE_ACK_IN(9) => sed_ack, - BUS_NO_MORE_DATA_IN(9) => '0', - BUS_UNKNOWN_ADDR_IN(9) => sed_nack, + BUS_READ_ENABLE_OUT(9) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(9) => bussed_rx.write, + BUS_DATA_OUT(9*32+31 downto 9*32) => bussed_rx.data, + BUS_ADDR_OUT(9*16+15 downto 9*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(9) => bussed_rx.timeout, + BUS_DATA_IN(9*32+31 downto 9*32) => bussed_tx.data, + BUS_DATAREADY_IN(9) => bussed_tx.ack, + BUS_WRITE_ACK_IN(9) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(9) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(9) => bussed_tx.unknown, --Channel Debug Registers BUS_READ_ENABLE_OUT(10) => cdb_read_en, BUS_WRITE_ENABLE_OUT(10) => cdb_write_en, @@ -869,27 +864,13 @@ end generate; --------------------------------------------------------------------------- -- SED Detection --------------------------------------------------------------------------- -THE_SED : entity work.sedcheck - port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr - ); - --- THE_SED : entity work.sedcheck --- port map( --- CLK => clk_100_i, --- ERROR_OUT => sed_error, --- i_rst_p => i_rst_p, --- STATUS_OUT => TEST_LINE(11 downto 0) --- ); + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => sed_error, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx + ); --------------------------------------------------------------------------- -- Reboot FPGA -- 2.43.0