From 5f1e88dec1a909f11c34d00011a17cadea6e5656 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 31 May 2016 14:37:55 +0200 Subject: [PATCH] round-robin readout for all channels. Each channel has a two-word (= 1 edges) buffer, one word is read every $CHANNEL clock cycles to main 1k fifo. --- code/ffarray.vhd | 50 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/code/ffarray.vhd b/code/ffarray.vhd index ea21aed..a121f5f 100644 --- a/code/ffarray.vhd +++ b/code/ffarray.vhd @@ -41,6 +41,13 @@ type ffarr_t is array(0 to 2) of vector_arr_8; signal ffarr : ffarr_t; signal finalval : vector_arr_5; + +signal buffer_read : std_logic_vector(CHANNELS-1 downto 0); +type buffer_t is array(0 to 1) of std_logic_vector(30 downto 0); +type buffers_t is array(CHANNELS-1 downto 0) of buffer_t; +signal buffer_data : buffers_t; +signal buffer_empty_0, buffer_empty_1 : std_logic_vector(CHANNELS-1 downto 0); + type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0); signal ram : ram_t; @@ -131,27 +138,48 @@ process begin end if; end process; +PROC_BUFFER : process begin + wait until rising_edge(CLK); + if fifo_write_val(c) = '1' then + if buffer_empty_0(c) = '1' then + buffer_data(c)(0)(3 downto 0) <= finalval(c)(3 downto 0); + buffer_data(c)(0)(4) <= finalval(c)(5); + buffer_data(c)(0)(25 downto 5) <= std_logic_vector(timer(20 downto 0)); + buffer_data(c)(0)(29 downto 26) <= (others => '0'); + buffer_data(c)(0)(30) <= finalval(c)(4); + buffer_empty_0(c) <= '0'; + end if; + end if; + if buffer_empty_0(c) = '0' and buffer_empty_1(c) = '1' then + buffer_data(c)(1) <= buffer_data(c)(0); + buffer_empty_0(c) <= '1'; + buffer_empty_1(c) <= '0'; + end if; + if buffer_read(c) = '1' then + buffer_empty_1(c) <= '1'; + end if; +end process; + + end generate; process variable chan : integer range 0 to 16 := 0; begin wait until rising_edge(CLK); - chan := to_integer(unsigned(SELECT_IN)); +-- chan := to_integer(unsigned(SELECT_IN)); fifo_real_write <= '0'; - if fifo_write_val(chan) = '1' then - fifo_data(3 downto 0) <= finalval(chan)(3 downto 0); - fifo_data(4) <= finalval(chan)(5); - fifo_data(25 downto 5) <= std_logic_vector(timer(20 downto 0)); --- fifo_data(27 downto 25) <= std_logic_vector(to_unsigned(chan,3)); - fifo_data(29 downto 26) <= SELECT_IN; - fifo_data(30) <= finalval(chan)(4); + buffer_read <= (others => '0'); + if buffer_empty_1(chan) = '0' then + fifo_data(30 downto 0) <= buffer_data(chan)(1); + fifo_data(29 downto 26)<= std_logic_vector(to_unsigned(chan,4)); fifo_real_write <= '1'; + buffer_read(chan) <= '1'; end if; --- chan := chan + 1; --- if chan = 9 then chan := 0; end if; + chan := chan + 1; + if chan = 9 then chan := 0; end if; end process; - + THE_FIFO : entity work.fifo_36x1k port map( -- 2.43.0