From 5f68f3b9641d04ea9abf8e1ea63034037c11cc67 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 22 Apr 2014 15:05:41 +0200 Subject: [PATCH] timing constraints for unimportant data lines is seperated from tdc placement constraints --- 32PinAddOn/compile_periph_gsi.pl | 14 +++--- 32PinAddOn/unimportant_lines_constraints.lpf | 52 ++++++++++++++++++++ ADA_Addon/compile_periph_gsi.pl | 13 ++--- ADA_Addon/unimportant_lines_constraints.lpf | 52 ++++++++++++++++++++ cbmtof/compile_cbmtof_gsi.pl | 1 + cbmtof/unimportant_lines_constraints.lpf | 52 ++++++++++++++++++++ hadesstart/unimportant_lines_constraints.lpf | 52 ++++++++++++++++++++ wasa/compile_periph_gsi.pl | 8 +-- wasa/unimportant_lines_constraints.lpf | 52 ++++++++++++++++++++ 9 files changed, 281 insertions(+), 15 deletions(-) create mode 100644 32PinAddOn/unimportant_lines_constraints.lpf create mode 100644 ADA_Addon/unimportant_lines_constraints.lpf create mode 100644 cbmtof/unimportant_lines_constraints.lpf create mode 100644 hadesstart/unimportant_lines_constraints.lpf create mode 100644 wasa/unimportant_lines_constraints.lpf diff --git a/32PinAddOn/compile_periph_gsi.pl b/32PinAddOn/compile_periph_gsi.pl index 0d1b968..7d9cd83 100755 --- a/32PinAddOn/compile_periph_gsi.pl +++ b/32PinAddOn/compile_periph_gsi.pl @@ -8,12 +8,12 @@ use Getopt::Long; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_32PinAddOn"; #Name of top-level entity -#my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; -#my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -#my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; -my $lattice_path = '/opt/lattice/diamond/2.01/'; -my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; +my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed +my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; +#my $lattice_path = '/opt/lattice/diamond/2.01/'; +#my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed +#my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### @@ -100,6 +100,8 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + #generate timestamp my $t=time; diff --git a/32PinAddOn/unimportant_lines_constraints.lpf b/32PinAddOn/unimportant_lines_constraints.lpf new file mode 100644 index 0000000..c6b7e10 --- /dev/null +++ b/32PinAddOn/unimportant_lines_constraints.lpf @@ -0,0 +1,52 @@ +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; + +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; + +MAXDELAY NET "THE_TDC/hit_in_i[*]" 0.600000 nS; #DATAPATH_ONLY ; + + +## Maybe effective + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; + + + + + + + +# BLOCK NET "THE_TDC/reset_tdc*" ; +# BLOCK NET "THE_TDC/reset_rdo*" ; +# #BLOCK NET "THE_TDC/hit_in_i_*" ; +# BLOCK NET "THE_TDC/hit_latch*" ; +# BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; + +# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; diff --git a/ADA_Addon/compile_periph_gsi.pl b/ADA_Addon/compile_periph_gsi.pl index 6099b1a..f543c45 100755 --- a/ADA_Addon/compile_periph_gsi.pl +++ b/ADA_Addon/compile_periph_gsi.pl @@ -8,12 +8,12 @@ use Getopt::Long; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_ADA"; #Name of top-level entity -#my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; -#my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -#my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; -my $lattice_path = '/opt/lattice/diamond/2.01/'; -my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; +my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed +my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; +#my $lattice_path = '/opt/lattice/diamond/2.01/'; +#my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed +#my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### @@ -100,6 +100,7 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); #generate timestamp my $t=time; diff --git a/ADA_Addon/unimportant_lines_constraints.lpf b/ADA_Addon/unimportant_lines_constraints.lpf new file mode 100644 index 0000000..c6b7e10 --- /dev/null +++ b/ADA_Addon/unimportant_lines_constraints.lpf @@ -0,0 +1,52 @@ +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; + +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; + +MAXDELAY NET "THE_TDC/hit_in_i[*]" 0.600000 nS; #DATAPATH_ONLY ; + + +## Maybe effective + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; + + + + + + + +# BLOCK NET "THE_TDC/reset_tdc*" ; +# BLOCK NET "THE_TDC/reset_rdo*" ; +# #BLOCK NET "THE_TDC/hit_in_i_*" ; +# BLOCK NET "THE_TDC/hit_latch*" ; +# BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; + +# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; diff --git a/cbmtof/compile_cbmtof_gsi.pl b/cbmtof/compile_cbmtof_gsi.pl index 4917432..1b97940 100755 --- a/cbmtof/compile_cbmtof_gsi.pl +++ b/cbmtof/compile_cbmtof_gsi.pl @@ -100,6 +100,7 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); #generate timestamp my $t=time; diff --git a/cbmtof/unimportant_lines_constraints.lpf b/cbmtof/unimportant_lines_constraints.lpf new file mode 100644 index 0000000..c6b7e10 --- /dev/null +++ b/cbmtof/unimportant_lines_constraints.lpf @@ -0,0 +1,52 @@ +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; + +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; + +MAXDELAY NET "THE_TDC/hit_in_i[*]" 0.600000 nS; #DATAPATH_ONLY ; + + +## Maybe effective + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; + + + + + + + +# BLOCK NET "THE_TDC/reset_tdc*" ; +# BLOCK NET "THE_TDC/reset_rdo*" ; +# #BLOCK NET "THE_TDC/hit_in_i_*" ; +# BLOCK NET "THE_TDC/hit_latch*" ; +# BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; + +# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; diff --git a/hadesstart/unimportant_lines_constraints.lpf b/hadesstart/unimportant_lines_constraints.lpf new file mode 100644 index 0000000..c6b7e10 --- /dev/null +++ b/hadesstart/unimportant_lines_constraints.lpf @@ -0,0 +1,52 @@ +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; + +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; + +MAXDELAY NET "THE_TDC/hit_in_i[*]" 0.600000 nS; #DATAPATH_ONLY ; + + +## Maybe effective + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; + + + + + + + +# BLOCK NET "THE_TDC/reset_tdc*" ; +# BLOCK NET "THE_TDC/reset_rdo*" ; +# #BLOCK NET "THE_TDC/hit_in_i_*" ; +# BLOCK NET "THE_TDC/hit_latch*" ; +# BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; + +# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; diff --git a/wasa/compile_periph_gsi.pl b/wasa/compile_periph_gsi.pl index d3d40b1..f84a4bd 100755 --- a/wasa/compile_periph_gsi.pl +++ b/wasa/compile_periph_gsi.pl @@ -100,6 +100,7 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); #generate timestamp my $t=time; @@ -183,7 +184,7 @@ if($map==1 || $all==1){ print "# !!!Possible Placement Errors!!! #\n"; print "#################################################\n\n"; - my $c="egrep 'WARNING.*hitBuf_|Channels/hit_buf_RNO|WARNING.*FC_|Channels/Channel200/SimAdderNo_FC|WARNING.*ff_en_|Channels/Channel200/ff_array_en_i_1_i' trb3_periph_padiwa_mrp.html"; + my $c="egrep 'WARNING.*hitBuf_|Channels/hit_buf_RNO|WARNING.*FC_|Channels/Channel200/SimAdderNo_FC|WARNING.*ff_en_|Channels/Channel200/ff_array_en_i_1_i'"." $TOPNAME"."_mrp.html"; system($c); last; } @@ -232,7 +233,8 @@ if($par==1 || $all==1){ } else { - $c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + $c=qq|par -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; execute($c); my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; system($c); @@ -269,7 +271,7 @@ if($bitgen==1 || $all==1){ execute($c); } -$c=qq|htmlrpt -mrp $TOPNAME.mrp -ptwr $TOPNAME.twr.setup $TOPNAME|; +$c=qq|htmlrpt -mrp $TOPNAME.mrp -mtwr $TOPNAME.twr.hold -ptwr $TOPNAME.twr.setup $TOPNAME|; execute($c); $c=qq|firefox $TOPNAME.html|; diff --git a/wasa/unimportant_lines_constraints.lpf b/wasa/unimportant_lines_constraints.lpf new file mode 100644 index 0000000..c6b7e10 --- /dev/null +++ b/wasa/unimportant_lines_constraints.lpf @@ -0,0 +1,52 @@ +############################################################################# +## Unimportant Data Lines ## +############################################################################# +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" 4x; +MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; +MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; + +MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; +MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/fifo_almost_full_sync*" 2x; + +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 5 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 5 X; + +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; +MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; + +MAXDELAY NET "THE_TDC/hit_in_i[*]" 0.600000 nS; #DATAPATH_ONLY ; + + +## Maybe effective + +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/gen_DEBUG_risingEdgeDetect_1/PULSE_OUT" 5 x; + + + + + + + +# BLOCK NET "THE_TDC/reset_tdc*" ; +# BLOCK NET "THE_TDC/reset_rdo*" ; +# #BLOCK NET "THE_TDC/hit_in_i_*" ; +# BLOCK NET "THE_TDC/hit_latch*" ; +# BLOCK NET "THE_TDC/reset_counters_i*" ; + + + +# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; +# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; + +# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset_1" 50 ns; +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; -- 2.43.0