From 5fb98260eec00a04d71f19c92207d4578a590430 Mon Sep 17 00:00:00 2001 From: hadaq Date: Wed, 4 Jul 2012 09:01:50 +0000 Subject: [PATCH] *** empty log message *** --- base/trb3_periph_mainz.lpf | 12 +++--- tdc_releases/tdc_v0.3/TDC.vhd | 36 ++++++++-------- tdc_test/trb3_periph.vhd | 79 +++++++++++++++++------------------ 3 files changed, 63 insertions(+), 64 deletions(-) diff --git a/base/trb3_periph_mainz.lpf b/base/trb3_periph_mainz.lpf index 014afe2..07fb2ec 100644 --- a/base/trb3_periph_mainz.lpf +++ b/base/trb3_periph_mainz.lpf @@ -7,18 +7,18 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; ################################################################# # Clock I/O ################################################################# -#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; -#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; -#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; -#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; +LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; +LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; diff --git a/tdc_releases/tdc_v0.3/TDC.vhd b/tdc_releases/tdc_v0.3/TDC.vhd index 1727334..cb3c6e8 100644 --- a/tdc_releases/tdc_v0.3/TDC.vhd +++ b/tdc_releases/tdc_v0.3/TDC.vhd @@ -528,20 +528,20 @@ begin fifo_nr_next <= CHANNEL_NUMBER; elsif fifo_nr_hex(0)(3) /= '1' then fifo_nr_next <= conv_integer("00000" & fifo_nr_hex(0)(2 downto 0)); - elsif fifo_nr_hex(1)(3) /= '1' then - fifo_nr_next <= conv_integer("00001" & fifo_nr_hex(1)(2 downto 0)); - elsif fifo_nr_hex(2)(3) /= '1' then - fifo_nr_next <= conv_integer("00010" & fifo_nr_hex(2)(2 downto 0)); - elsif fifo_nr_hex(3)(3) /= '1' then - fifo_nr_next <= conv_integer("00011" & fifo_nr_hex(3)(2 downto 0)); - --elsif fifo_nr_hex(4)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0)); - --elsif fifo_nr_hex(5)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0)); - --elsif fifo_nr_hex(6)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0)); - --elsif fifo_nr_hex(7)(3) /= '1' then - -- fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0)); + --elsif fifo_nr_hex(1)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00001" & fifo_nr_hex(1)(2 downto 0)); + --elsif fifo_nr_hex(2)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00010" & fifo_nr_hex(2)(2 downto 0)); + --elsif fifo_nr_hex(3)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00011" & fifo_nr_hex(3)(2 downto 0)); + --elsif fifo_nr_hex(4)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0)); + --elsif fifo_nr_hex(5)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0)); + --elsif fifo_nr_hex(6)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0)); + --elsif fifo_nr_hex(7)(3) /= '1' then + -- fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0)); else fifo_nr_next <= CHANNEL_NUMBER; end if; @@ -1136,12 +1136,12 @@ begin -- TDC_DEBUG(31 downto 28) <= -- Register 0x81 - TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 0); + --TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 0); -- Register 0x82 - Empty_Channels : if CHANNEL_NUMBER >= 33 generate - TDC_DEBUG(2*32+CHANNEL_NUMBER-33 downto 2*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 32); - end generate Empty_Channels; + --Empty_Channels : if CHANNEL_NUMBER >= 33 generate + -- TDC_DEBUG(2*32+CHANNEL_NUMBER-33 downto 2*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 32); + --end generate Empty_Channels; -- Register 0x83 TDC_DEBUG(3*32+31 downto 3*32+0) <= "00000" & TRG_WIN_POST & "00000" & TRG_WIN_PRE; diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd index 3e0d82e..f9f15e4 100644 --- a/tdc_test/trb3_periph.vhd +++ b/tdc_test/trb3_periph.vhd @@ -614,45 +614,45 @@ begin -- TDC ------------------------------------------------------------------------------- --- THE_TDC : TDC --- generic map ( --- CHANNEL_NUMBER => 40, -- Number of TDC channels --- STATUS_REG_NR => REGIO_NUM_STAT_REGS, --- CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) --- port map ( --- RESET => reset_i, --- CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement --- CLK_READOUT => clk_100_i, -- Clock for the readout --- REFERENCE_TIME => timing_trg_received_i, -- Reference time input --- HIT_IN => hit_in_i(39 downto 1), -- Channel start signals --- TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width --- TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width - --- -- Trigger signals from handler --- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet --- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet --- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet --- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet --- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet --- SPIKE_DETECTED_IN => trg_spike_detected_i, --- MULTI_TMG_TRG_IN => trg_multiple_trg_i, --- SPURIOUS_TRG_IN => trg_spurious_trg_i, - --- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package --- TRG_CODE_IN => trg_code_i, -- --- TRG_INFORMATION_IN => trg_information_i, -- --- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package - --- --Response to handler --- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal --- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc --- DATA_OUT => fee_data_i, -- tdc data --- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal --- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal --- -- --- TDC_DEBUG => stat_reg, --- LOGIC_ANALYSER_OUT => open, --TEST_LINE, --- CONTROL_REG_IN => ctrl_reg); + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 8, -- Number of TDC channels + STATUS_REG_NR => REGIO_NUM_STAT_REGS, + CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(7 downto 1), -- Channel start signals + TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width + + -- Trigger signals from handler + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + SPURIOUS_TRG_IN => trg_spurious_trg_i, + + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + + --Response to handler + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + TDC_DEBUG => stat_reg, + LOGIC_ANALYSER_OUT => open, --TEST_LINE, + CONTROL_REG_IN => ctrl_reg); -- -- For single edge measurements @@ -660,7 +660,6 @@ begin -- -- For ToT Measurements -- hit_in_i(1) <= not timing_trg_received_i; - -- Gen_Hit_In_Signals : for i in 1 to 19 generate -- hit_in_i(i*2) <= INP(i-1); -- hit_in_i(i*2+1) <= not INP(i-1); -- 2.43.0