From 5fbe7bc63d5846442e287244043cf9cb5eb39cc8 Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Thu, 19 Jun 2014 16:11:57 +0200 Subject: [PATCH] Finally! SODA across a soda-hub. Reset-problem solved (stuck quad reset on hub downlink) trbnet not working at all right now --- code/med_ecp3_sfp_4_sync_down.vhd | 53 +++--- code/med_ecp3_sfp_sync_down.vhd | 10 +- code/med_ecp3_sfp_sync_up.vhd | 21 +-- code/soda_components.vhd | 5 +- code/trb3_periph_sodahub.vhd | 35 ++-- code/trb3_periph_sodasource.vhd | 2 +- soda_client.ldf | 2 +- soda_client.lpf | 1 + soda_client_probe.rvl | 9 +- soda_hub_probe.rvl | 258 +++++++++++++++++++++++++----- soda_source.lpf | 1 + soda_source_probe.rvl | 57 ++++++- trb3_soda_client.xcf | 8 +- trb3_soda_dual_client.xcf | 6 +- trb3_soda_hub.xcf | 8 +- trb3_soda_source.xcf | 9 +- 16 files changed, 360 insertions(+), 125 deletions(-) diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index 120aabb..02eb39e 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -15,7 +15,7 @@ entity med_ecp3_sfp_4_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); -- hub downlink is NO slave port( - OSCCLK : in std_logic; -- 200 MHz reference clock + OSC_CLK : in std_logic; -- 200 MHz reference clock TX_DATACLK : in std_logic; -- 200 MHz data clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock RESET : in std_logic; -- synchronous reset @@ -85,7 +85,8 @@ architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is signal clk_200_osc : std_logic; -signal clk_200_tx_data : std_logic; +signal clk_200_txdata : std_logic; +signal clk_200_rxdn : std_logic_vector(3 downto 0); signal clk_200_i : std_logic_vector(3 downto 0); signal clk_rx_full : std_logic_vector(3 downto 0); signal clk_rx_half : std_logic_vector(3 downto 0); @@ -101,7 +102,7 @@ signal rx_error : t_HUB_BIT; --std_logic_vector(3 downto 0); signal rst_n : t_HUB_BIT; signal rst : t_HUB_BIT; -- PL! signal rx_serdes_rst : t_HUB_BIT; -signal tx_serdes_rst : t_HUB_BIT; +signal tx_serdes_rst : std_logic; signal tx_pcs_rst : t_HUB_BIT; signal rx_pcs_rst : t_HUB_BIT; signal rst_qd : t_HUB_BIT; @@ -165,8 +166,8 @@ begin --SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -clk_200_osc <= OSCCLK; -- This external clock is oscillator/pll generated !!! -clk_200_tx_data <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!! +clk_200_osc <= OSC_CLK; -- This external clock is oscillator/pll generated !!! +clk_200_txdata <= TX_DATACLK; -- This external clock is the rx_full of the uplink !!! gen_clocks : for i in 0 to 3 generate @@ -176,13 +177,14 @@ gen_clocks : for i in 0 to 3 generate CLK_RX_FULL_OUT(i) <= clk_rx_full(i); - gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_200_i(i) <= clk_rx_full(i); - end generate; +-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master +-- clk_200_i(i) <= clk_rx_full(i); +-- end generate; - gen_master_clock : if IS_SYNC_SLAVE = c_NO generate - clk_200_i(i) <= clk_200_tx_data; - end generate; +-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate + clk_200_i(i) <= clk_200_txdata; + clk_200_rxdn(i) <= clk_rx_full(i); -- These clocks are the rx_full of the DOWNLINKs !!! +-- end generate; end generate; ------------------------------------------------- @@ -195,9 +197,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch0 => SD_RXD_N_IN(0), hdoutp_ch0 => SD_TXD_P_OUT(0), hdoutn_ch0 => SD_TXD_N_OUT(0), - rxiclk_ch0 => clk_200_i(0), + rxiclk_ch0 => clk_200_i(0), --clk_200_txdata, sci_sel_ch0 => sci_ch_i(0), - txiclk_ch0 => clk_200_tx_data, + txiclk_ch0 => clk_200_txdata, rx_full_clk_ch0 => clk_rx_full(0), rx_half_clk_ch0 => clk_rx_half(0), tx_full_clk_ch0 => clk_tx_full(0), @@ -228,9 +230,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch1 => SD_RXD_N_IN(1), hdoutp_ch1 => SD_TXD_P_OUT(1), hdoutn_ch1 => SD_TXD_N_OUT(1), - rxiclk_ch1 => clk_200_i(1), + rxiclk_ch1 => clk_200_i(1), --clk_200_txdata, sci_sel_ch1 => sci_ch_i(1), - txiclk_ch1 => clk_200_tx_data, + txiclk_ch1 => clk_200_txdata, rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), tx_full_clk_ch1 => clk_tx_full(1), @@ -261,9 +263,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch2 => SD_RXD_N_IN(2), hdoutp_ch2 => SD_TXD_P_OUT(2), hdoutn_ch2 => SD_TXD_N_OUT(2), - rxiclk_ch2 => clk_200_i(2), + rxiclk_ch2 => clk_200_i(2), --clk_200_txdata, sci_sel_ch2 => sci_ch_i(2), - txiclk_ch2 => clk_200_tx_data, + txiclk_ch2 => clk_200_txdata, rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), tx_full_clk_ch2 => clk_tx_full(2), @@ -294,9 +296,9 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch3 => SD_RXD_N_IN(3), hdoutp_ch3 => SD_TXD_P_OUT(3), hdoutn_ch3 => SD_TXD_N_OUT(3), - rxiclk_ch3 => clk_200_i(3), + rxiclk_ch3 => clk_200_i(3), --clk_200_txdata, sci_sel_ch3 => sci_ch_i(3), - txiclk_ch3 => clk_200_tx_data, + txiclk_ch3 => clk_200_txdata, rx_full_clk_ch3 => clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), tx_full_clk_ch3 => clk_tx_full(3), @@ -331,17 +333,18 @@ THE_SERDES : entity work.serdes_4_sync_downstream sci_wrn => sci_write_i, fpga_txrefclk => clk_200_osc, --clk_200_i(0), - tx_serdes_rst_c => tx_serdes_rst(0), + tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 tx_pll_lol_qd_s => tx_pll_lol_quad, tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols - rst_qd_c => rst_down_quad, + rst_qd_c => rst_down_quad, -- jemig wat is Oscar toch gasfjkl[glk serdes_rst_qd_c => serdes_rst_down_quad ); ------------------------- -- combined quad reset -- ------------------------- -rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0'; +--rst_down_quad <= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0'; +rst_down_quad <= RESET; serdes_rst_down_quad <= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0'; generated_logic : for i in 0 to 3 generate @@ -383,7 +386,7 @@ generated_logic : for i in 0 to 3 generate PROC_ALLOW : process(clk_200_i(i)) begin - if rising_edge(clk_200_i(i)) then -- clk_200_tx_data ?? + if rising_edge(clk_200_i(i)) then -- clk_200_txdata ?? if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then rx_allow(i) <= '1'; tx_allow(i) <= '1'; @@ -398,7 +401,7 @@ generated_logic : for i in 0 to 3 generate tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); - PROC_START_TIMER : process(clk_200_i(i)) --clk_200_tx_data?? + PROC_START_TIMER : process(clk_200_i(i)) --clk_200_txdata?? begin if rising_edge(clk_200_i(i)) then if got_link_ready_i(i) = '1' then @@ -427,7 +430,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => clk_200_i(i), --clk_200_tx_data?? + CLK_200 => clk_200_i(i), --clk_200_txdata?? CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index dabf48f..6f17719 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -186,13 +186,13 @@ SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches rst_n <= not(CLEAR or internal_make_link_reset_out); rst <= (CLEAR or internal_make_link_reset_out); -gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_200_i <= clk_rx_full; -end generate; +--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate +-- clk_200_i <= clk_rx_full; +--end generate; -gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate clk_200_i <= clk_200_internal; -end generate; +--end generate; ------------------------------------------------- diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index 3f0c78b..bced937 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -16,8 +16,8 @@ entity med_ecp3_sfp_sync_up is -- MASTER_CLOCK_SWITCH : integer := c_NO; --just for debugging, should be NO IS_SYNC_SLAVE : integer := c_YES); --select slave mode port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock - SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + CLK : in std_logic; -- 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset --Internal Connection TX @@ -40,6 +40,7 @@ entity med_ecp3_sfp_sync_up is TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! LINK_PHASE_OUT : out std_logic := '0'; --PL! + LINK_READY_OUT : out std_logic := '0'; --PL! --SFP Connection SD_RXD_P_IN : in std_logic; @@ -202,21 +203,23 @@ CLK_RX_FULL_OUT <= clk_rx_full; --SD_TXDIS_OUT <= not (rx_allow_q or not IS_SYNC_SLAVE); --slave only switches on when RX is ready -SD_TXDIS_OUT <= '0'; --not (rx_allow_q); --slave only switches on when RX is ready +SD_TXDIS_OUT <= '0'; --not (rx_allow_q); --slave only switches on when RX is ready +LINK_READY_OUT <= got_link_ready_i; + --rst_n <= not CLEAR; PL! rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger); rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger); -gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate +--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate clk_200_i <= clk_rx_full; -end generate; +--end generate; -gen_master_clock : if IS_SYNC_SLAVE = c_NO generate - clk_200_i <= clk_200_internal; -end generate; +--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +-- clk_200_i <= clk_200_internal; +--end generate; ------------------------------------------------- @@ -291,7 +294,7 @@ THE_RX_FSM : rx_reset_fsm THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n, - TX_REFCLK => clk_200_i, --nternal, -- allways running PL! + TX_REFCLK => clk_200_internal, -- allways running PL! 18-06 was clk_200_i TX_PLL_LOL_QD_S => tx_pll_lol, RST_QD_C => rst_qd, TX_PCS_RST_CH_C => tx_pcs_rst, diff --git a/code/soda_components.vhd b/code/soda_components.vhd index 4fc1ea4..a987eee 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -366,7 +366,7 @@ component med_ecp3_sfp_4_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode port( - OSCCLK : in std_logic; -- 200 MHz reference clock + OSC_CLK : in std_logic; -- 200 MHz reference clock TX_DATACLK : in std_logic; -- 200 MHz data clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to OSC clock RESET : in std_logic; -- synchronous reset @@ -430,7 +430,7 @@ component med_ecp3_sfp_sync_up is IS_SYNC_SLAVE : integer := c_YES --select slave mode ); port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock + CLK : in std_logic; -- 200 MHz reference clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset @@ -454,6 +454,7 @@ component med_ecp3_sfp_sync_up is TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! LINK_PHASE_OUT : out std_logic := '0'; --PL! + LINK_READY_OUT : out std_logic := '0'; --PL! --SFP Connection SD_RXD_P_IN : in std_logic; diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index a8ae655..ae61142 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -88,6 +88,8 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; signal reset_i : std_logic; + signal downlink_clear : std_logic; + signal downlink_reset : std_logic; signal GSR_N : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -185,6 +187,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal rxup_dlm_word : std_logic_vector(7 downto 0); signal txup_dlm_preview_S : std_logic; --PL! signal uplink_phase_S : std_logic; --PL! + signal uplink_ready_S : std_logic; --PL! signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); --SODA downlink @@ -292,7 +295,7 @@ begin --------------------------------------------------------------------------- -- Clock Handling --------------------------------------------------------------------------- -gen_200_PLL : if USE_125_MHZ = c_NO generate +--gen_200_PLL : if USE_125_MHZ = c_NO generate THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, @@ -300,20 +303,20 @@ gen_200_PLL : if USE_125_MHZ = c_NO generate CLKOK => clk_raw_internal, LOCK => pll_lock ); -end generate; +--end generate; -gen_125 : if USE_125_MHZ = c_YES generate - clk_sys_internal <= CLK_GPLL_LEFT; - clk_raw_internal <= CLK_GPLL_LEFT; -end generate; +--gen_125 : if USE_125_MHZ = c_YES generate +-- clk_sys_internal <= CLK_GPLL_LEFT; +-- clk_raw_internal <= CLK_GPLL_LEFT; +--end generate; -gen_sync_clocks : if SYNC_MODE = c_YES generate +--gen_sync_clocks : if SYNC_MODE = c_YES generate clk_soda_i <= soda_rxup_clock_full; -end generate; +--end generate; -gen_local_clocks : if SYNC_MODE = c_NO generate - clk_soda_i <= clk_raw_internal; -end generate; +--gen_local_clocks : if SYNC_MODE = c_NO generate +-- clk_soda_i <= clk_raw_internal; +--end generate; --------------------------------------------------------------------------- @@ -463,6 +466,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up TX_DLM_WORD => txup_dlm_word, TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL! LINK_PHASE_OUT => uplink_phase_S, --PL! + LINK_READY_OUT => uplink_ready_S, --PL! --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting SD_RXD_P_IN => SERDES_ADDON_RX(4), SD_RXD_N_IN => SERDES_ADDON_RX(5), @@ -529,7 +533,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up ); - + downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0'; + downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0'; THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down @@ -538,11 +543,11 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up IS_SYNC_SLAVE => c_NO ) port map( - OSCCLK => clk_raw_internal, + OSC_CLK => clk_raw_internal, TX_DATACLK => clk_soda_i, --clk_raw_internal, --clk_200_i, SYSCLK => clk_sys_internal, --clk_sys_i, - RESET => reset_i, - CLEAR => clear_i, + RESET => downlink_reset, + CLEAR => downlink_clear, --------------------------------------------------------------------------------------------------------------------------------------------------------- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. --------------------------------------------------------------------------------------------------------------------------------------------------------- diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd index 6499977..6691f84 100644 --- a/code/trb3_periph_sodasource.vhd +++ b/code/trb3_periph_sodasource.vhd @@ -308,7 +308,7 @@ end generate; --gen_local_clocks : if SYNC_MODE = c_NO generate -- clk_sys_i <= clk_sys_internal; --- clk_200_i <= clk_raw_internal; +-- clk_200_ip <= clk_raw_internal; --end generate; diff --git a/soda_client.ldf b/soda_client.ldf index ab0653e..5b10566 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -4,7 +4,7 @@