From 5fe65743dc223b900c48851e0b578151171e3fff Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 8 Aug 2007 12:36:19 +0000 Subject: [PATCH] changed confusing port names of base api, Jan --- trb_net_active_api.vhd | 52 +++++++------- trb_net_base_api.vhd | 145 +++++++++++++++++++++------------------- trb_net_passive_api.vhd | 52 +++++++------- 3 files changed, 127 insertions(+), 122 deletions(-) diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd index 93568f8..ef6c0b0 100644 --- a/trb_net_active_api.vhd +++ b/trb_net_active_api.vhd @@ -120,23 +120,23 @@ architecture trb_net_active_api_arch of trb_net_active_api is -- Internal direction port -- the ports with active or passive in their name are to be mapped by the active api -- to the init respectivly the reply path and vice versa in the passive api. - INT_ACTIVE_DATAREADY_OUT: out STD_LOGIC; - INT_ACTIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_ACTIVE_READ_IN: in STD_LOGIC; + INT_MASTER_DATAREADY_OUT: out STD_LOGIC; + INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_MASTER_READ_IN: in STD_LOGIC; - INT_ACTIVE_DATAREADY_IN: in STD_LOGIC; - INT_ACTIVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_ACTIVE_READ_OUT: out STD_LOGIC; + INT_MASTER_DATAREADY_IN: in STD_LOGIC; + INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_MASTER_READ_OUT: out STD_LOGIC; - INT_PASSIVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last -- header (only for the reply path) - INT_PASSIVE_DATAREADY_OUT: out STD_LOGIC; - INT_PASSIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_PASSIVE_READ_IN: in STD_LOGIC; + INT_SLAVE_DATAREADY_OUT: out STD_LOGIC; + INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_SLAVE_READ_IN: in STD_LOGIC; - INT_PASSIVE_DATAREADY_IN: in STD_LOGIC; - INT_PASSIVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_PASSIVE_READ_OUT: out STD_LOGIC; + INT_SLAVE_DATAREADY_IN: in STD_LOGIC; + INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_SLAVE_READ_OUT: out STD_LOGIC; -- Status and control port STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) @@ -177,23 +177,23 @@ begin APL_SEQNR_OUT => APL_SEQNR_OUT, -- Internal direction port - INT_ACTIVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_ACTIVE_DATA_OUT => INT_INIT_DATA_OUT, - INT_ACTIVE_READ_IN => INT_INIT_READ_IN, + INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, + INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT, + INT_MASTER_READ_IN => INT_INIT_READ_IN, - INT_ACTIVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_ACTIVE_DATA_IN => INT_INIT_DATA_IN, - INT_ACTIVE_READ_OUT => INT_INIT_READ_OUT, + INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN, + INT_MASTER_DATA_IN => INT_INIT_DATA_IN, + INT_MASTER_READ_OUT => INT_INIT_READ_OUT, - INT_PASSIVE_HEADER_IN => INT_REPLY_HEADER_IN, + INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - INT_PASSIVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_PASSIVE_DATA_OUT => INT_REPLY_DATA_OUT, - INT_PASSIVE_READ_IN => INT_REPLY_READ_IN, + INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, + INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT, + INT_SLAVE_READ_IN => INT_REPLY_READ_IN, - INT_PASSIVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_PASSIVE_DATA_IN => INT_REPLY_DATA_IN, - INT_PASSIVE_READ_OUT => INT_REPLY_READ_OUT, + INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, + INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN, + INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT, -- Status and control port STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, STAT_FIFO_TO_APL => STAT_FIFO_TO_APL diff --git a/trb_net_base_api.vhd b/trb_net_base_api.vhd index 4a51d9c..8102cfe 100644 --- a/trb_net_base_api.vhd +++ b/trb_net_base_api.vhd @@ -47,27 +47,27 @@ entity trb_net_base_api is APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0); -- Internal direction port - -- the ports with active or passive in their name are to be mapped by the active api + -- the ports with master or slave in their name are to be mapped by the active api -- to the init respectivly the reply path and vice versa in the passive api. - -- lets say: the "active" path is the path that I send data on. - INT_ACTIVE_DATAREADY_OUT: out STD_LOGIC; - INT_ACTIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_ACTIVE_READ_IN: in STD_LOGIC; + -- lets define: the "master" path is the path that I send data on. + INT_MASTER_DATAREADY_OUT: out STD_LOGIC; + INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_MASTER_READ_IN: in STD_LOGIC; - INT_ACTIVE_DATAREADY_IN: in STD_LOGIC; - INT_ACTIVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_ACTIVE_READ_OUT: out STD_LOGIC; + INT_MASTER_DATAREADY_IN: in STD_LOGIC; + INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_MASTER_READ_OUT: out STD_LOGIC; - INT_PASSIVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last -- header (only for the reply path) - INT_PASSIVE_DATAREADY_OUT: out STD_LOGIC; - INT_PASSIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_PASSIVE_READ_IN: in STD_LOGIC; + INT_SLAVE_DATAREADY_OUT: out STD_LOGIC; + INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_SLAVE_READ_IN: in STD_LOGIC; - INT_PASSIVE_DATAREADY_IN: in STD_LOGIC; - INT_PASSIVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_PASSIVE_READ_OUT: out STD_LOGIC; + INT_SLAVE_DATAREADY_IN: in STD_LOGIC; + INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_SLAVE_READ_OUT: out STD_LOGIC; -- Status and control port STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); @@ -200,7 +200,7 @@ architecture trb_net_base_api_arch of trb_net_base_api is type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); signal current_state, next_state : API_STATE; signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; - signal passive_running, next_passive_running : std_logic; + signal slave_running, next_slave_running : std_logic; signal combined_header: std_logic_vector(47 downto 0); --stored in sbuf -- , registered_header, next_registered_header: std_logic_vector(47 downto 0); @@ -211,10 +211,10 @@ architecture trb_net_base_api_arch of trb_net_base_api is signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0); signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); - signal next_INT_ACTIVE_DATA_OUT: std_logic_vector(50 downto 0); - signal next_INT_ACTIVE_DATAREADY_OUT: std_logic; + signal next_INT_MASTER_DATA_OUT: std_logic_vector(50 downto 0); + signal next_INT_MASTER_DATAREADY_OUT: std_logic; signal sbuf_free, sbuf_next_READ: std_logic; - signal next_INT_PASSIVE_READ_OUT, reg_INT_PASSIVE_READ_OUT: std_logic; + signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic; signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0); signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); @@ -235,12 +235,12 @@ begin CLK => CLK, RESET => RESET, CLK_EN => CLK_EN, - INT_DATAREADY_OUT => INT_PASSIVE_DATAREADY_OUT, - INT_DATA_OUT => INT_PASSIVE_DATA_OUT, - INT_READ_IN => INT_PASSIVE_READ_IN, - INT_DATAREADY_IN => INT_ACTIVE_DATAREADY_IN, - INT_DATA_IN => INT_ACTIVE_DATA_IN, - INT_READ_OUT => INT_ACTIVE_READ_OUT, + INT_DATAREADY_OUT => INT_SLAVE_DATAREADY_OUT, + INT_DATA_OUT => INT_SLAVE_DATA_OUT, + INT_READ_IN => INT_SLAVE_READ_IN, + INT_DATAREADY_IN => INT_MASTER_DATAREADY_IN, + INT_DATA_IN => INT_MASTER_DATA_IN, + INT_READ_OUT => INT_MASTER_READ_OUT, APL_HOLD_TRM => '0', APL_DTYPE_IN => (others => '0'), APL_ERROR_PATTERN_IN => (others => '0'), @@ -248,6 +248,11 @@ begin ); end generate; +-- gen_noterm: if API_TYPE = 0 generate +-- INT_SLAVE_READ_OUT <= '0'; +-- +-- end generate; + --------------------------------------- -- fifo to internal --------------------------------------- @@ -359,13 +364,13 @@ begin CLK => CLK, RESET => RESET, CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_INT_ACTIVE_DATAREADY_OUT, + COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT, COMB_next_READ_OUT => sbuf_next_READ, COMB_READ_IN => '1', - COMB_DATA_IN => next_INT_ACTIVE_DATA_OUT, - SYN_DATAREADY_OUT => INT_ACTIVE_DATAREADY_OUT, - SYN_DATA_OUT => INT_ACTIVE_DATA_OUT, - SYN_READ_IN => INT_ACTIVE_READ_IN + COMB_DATA_IN => next_INT_MASTER_DATA_OUT, + SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT, + SYN_DATA_OUT => INT_MASTER_DATA_OUT, + SYN_READ_IN => INT_MASTER_READ_IN ); @@ -385,45 +390,45 @@ begin fifo_to_int_data_out, combined_trailer) begin if out_select = HDR then - next_INT_ACTIVE_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; - next_INT_ACTIVE_DATA_OUT(DWORD_POSITION) <= combined_header; + next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; + next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= combined_header; elsif out_select = TRM then - next_INT_ACTIVE_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_ACTIVE_DATA_OUT(DWORD_POSITION) <= registered_trailer; + next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; + next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= registered_trailer; elsif out_select = TRM_COMB then - next_INT_ACTIVE_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_ACTIVE_DATA_OUT(DWORD_POSITION) <= combined_trailer; + next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; + next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= combined_trailer; else - next_INT_ACTIVE_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_ACTIVE_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + next_INT_MASTER_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; + next_INT_MASTER_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; end if; end process; --------------------------------------- --- the state machine for the active part +-- the state machine --------------------------------------- -- gen_active_fsm : if API_TYPE = 1 generate STATE_COMB : process(current_state, APL_SEND_IN, combined_header, - INT_ACTIVE_READ_IN, APL_WRITE_IN, fifo_to_int_empty, - fifo_to_int_data_out, combined_trailer, + INT_MASTER_READ_IN, APL_WRITE_IN, fifo_to_int_empty, + fifo_to_int_data_out, combined_trailer, slave_running, next_registered_trailer, fifo_to_int_data_out, - fifo_to_apl_empty, INT_PASSIVE_DATAREADY_IN, - reg_INT_PASSIVE_READ_OUT,fifo_to_apl_read, + fifo_to_apl_empty, INT_SLAVE_DATAREADY_IN, + reg_INT_SLAVE_READ_OUT,fifo_to_apl_read, reg_APL_DATAREADY_OUT, fifo_to_apl_data_out, reg_APL_DATAREADY_OUT, APL_READ_IN, sbuf_free, reg_APL_TYP_OUT, APL_SHORT_TRANSFER_IN, fifo_to_apl_full) begin -- process next_state <= MY_ERROR; - next_INT_ACTIVE_DATAREADY_OUT <= '0'; + next_INT_MASTER_DATAREADY_OUT <= '0'; out_select <= DAT; update_registered_trailer <= '0'; fifo_to_int_read <= '0'; - next_INT_PASSIVE_READ_OUT <= '0'; + next_INT_SLAVE_READ_OUT <= '0'; fifo_to_apl_write <= '0'; next_APL_DATAREADY_OUT <= '0'; fifo_to_apl_read <= '0'; - next_passive_running <= passive_running; + next_slave_running <= slave_running; ------------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------------- @@ -431,11 +436,11 @@ begin if APL_SEND_IN = '1' then if APL_SHORT_TRANSFER_IN = '1' and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' then next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN - next_INT_ACTIVE_DATAREADY_OUT <= '0'; + next_INT_MASTER_DATAREADY_OUT <= '0'; else -- normal transfer, prepare the header next_state <= SEND_HEADER; out_select <= HDR; - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; end if; -- next word will be a header else next_state <= IDLE; @@ -447,7 +452,7 @@ begin next_state <= SEND_SHORT; if APL_SEND_IN = '0' then -- terminate the transfer next_state <= SEND_TRAILER; - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= TRM; else update_registered_trailer <= '1'; @@ -459,9 +464,9 @@ begin if sbuf_free = '1' then -- kill current header next_state <= RUNNING; if fifo_to_int_empty = '1' then - next_INT_ACTIVE_DATAREADY_OUT <= '0'; + next_INT_MASTER_DATAREADY_OUT <= '0'; else - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= DAT; fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty @@ -476,14 +481,14 @@ begin if fifo_to_int_empty = '1' then -- immediate stop next_state <= SEND_TRAILER; update_registered_trailer <= '1'; - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= TRM_COMB; else next_state <= SHUTDOWN; update_registered_trailer <= '1'; if sbuf_free = '1' then -- data words have to be prepared - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= DAT; fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty = '0' @@ -492,7 +497,7 @@ begin next_state <= RUNNING; if fifo_to_int_empty = '0' and sbuf_free = '1' then -- data words have to be prepared - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= DAT; fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty = '0' @@ -504,13 +509,13 @@ begin next_state <= SHUTDOWN; if fifo_to_int_empty = '0' and sbuf_free = '1' then -- data words have to be prepared - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= DAT; fifo_to_int_read <= '1'; elsif sbuf_free = '1' then -- we are done next_state <= SEND_TRAILER; - next_INT_ACTIVE_DATAREADY_OUT <= '1'; + next_INT_MASTER_DATAREADY_OUT <= '1'; out_select <= TRM; end if; ------------------------------------------------------------------------------- @@ -520,8 +525,8 @@ begin if sbuf_free = '1' then -- kill current trailer next_state <= WAITING; out_select <= TRM; - next_INT_ACTIVE_DATAREADY_OUT <= '0'; - next_passive_running <= '0'; + next_INT_MASTER_DATAREADY_OUT <= '0'; + next_slave_running <= '0'; else next_state <= SEND_TRAILER; end if; @@ -533,9 +538,9 @@ begin -- here we have to supply the receiver port -- part 1: connection to network if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then - next_INT_PASSIVE_READ_OUT <= '1'; + next_INT_SLAVE_READ_OUT <= '1'; end if; - if reg_INT_PASSIVE_READ_OUT = '1' and INT_PASSIVE_DATAREADY_IN = '1' then + if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then fifo_to_apl_write <= '1'; -- use fifo as the pipe end if; @@ -548,7 +553,7 @@ begin -- valid read fifo_to_apl_read <= '1'; if reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR then - next_passive_running <= '1'; + next_slave_running <= '1'; end if; if reg_APL_TYP_OUT = TYPE_TRM and (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then next_state <= IDLE; @@ -591,11 +596,11 @@ begin APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing - INT_PASSIVE_READ_OUT <= reg_INT_PASSIVE_READ_OUT; + INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; -- connect receiver - fifo_to_apl_data_in <= INT_PASSIVE_DATA_IN; + fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; reg_APL_DATA_OUT <= next_APL_DATA_OUT; reg_APL_TYP_OUT <= next_APL_TYP_OUT; @@ -604,7 +609,7 @@ begin APL_TYP_OUT <= reg_APL_TYP_OUT; -- APL_RUN_OUT <= '0' when ((current_state = IDLE )) APL_RUN_OUT <= '0' when ((current_state = IDLE and API_TYPE = 1) - or (passive_running = '0' and API_TYPE = 0)) + or (slave_running = '0' and API_TYPE = 0)) else '1'; APL_SEQNR_OUT <= sequence_counter; @@ -626,29 +631,29 @@ begin if rising_edge(CLK) then if RESET = '1' then sequence_counter <= (others => '0'); - reg_INT_PASSIVE_READ_OUT <= '0'; + reg_INT_SLAVE_READ_OUT <= '0'; if API_TYPE = 1 then current_state <= IDLE; else current_state <= WAITING; end if; - passive_running <= '0'; + slave_running <= '0'; tb_current_state <= IDLE; tb_registered_trailer <= (others => '0'); tb_registered_target <= ILLEGAL_ADRESS; elsif CLK_EN = '1' then sequence_counter <= next_sequence_counter; - reg_INT_PASSIVE_READ_OUT <= next_INT_PASSIVE_READ_OUT; + reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT; current_state <= next_state; - passive_running <= next_passive_running; + slave_running <= next_slave_running; tb_current_state <= tb_next_state; tb_registered_trailer <= tb_next_registered_trailer; tb_registered_target <= tb_next_registered_target; else sequence_counter <= sequence_counter; - reg_INT_PASSIVE_READ_OUT <= reg_INT_PASSIVE_READ_OUT; + reg_INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; current_state <= current_state; - passive_running <= passive_running; + slave_running <= slave_running; tb_current_state <= tb_current_state; tb_registered_trailer <= tb_registered_trailer; tb_registered_target <= tb_registered_target; diff --git a/trb_net_passive_api.vhd b/trb_net_passive_api.vhd index 048f23f..da5a119 100644 --- a/trb_net_passive_api.vhd +++ b/trb_net_passive_api.vhd @@ -120,23 +120,23 @@ architecture trb_net_passive_api_arch of trb_net_passive_api is -- Internal direction port -- the ports with active or passive in their name are to be mapped by the active api -- to the init respectivly the reply path and vice versa in the passive api. - INT_ACTIVE_DATAREADY_OUT: out STD_LOGIC; - INT_ACTIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_ACTIVE_READ_IN: in STD_LOGIC; + INT_MASTER_DATAREADY_OUT: out STD_LOGIC; + INT_MASTER_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_MASTER_READ_IN: in STD_LOGIC; - INT_ACTIVE_DATAREADY_IN: in STD_LOGIC; - INT_ACTIVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_ACTIVE_READ_OUT: out STD_LOGIC; + INT_MASTER_DATAREADY_IN: in STD_LOGIC; + INT_MASTER_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_MASTER_READ_OUT: out STD_LOGIC; - INT_PASSIVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last + INT_SLAVE_HEADER_IN: in STD_LOGIC; -- Concentrator kindly asks to resend the last -- header (only for the reply path) - INT_PASSIVE_DATAREADY_OUT: out STD_LOGIC; - INT_PASSIVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_PASSIVE_READ_IN: in STD_LOGIC; + INT_SLAVE_DATAREADY_OUT: out STD_LOGIC; + INT_SLAVE_DATA_OUT: out STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_SLAVE_READ_IN: in STD_LOGIC; - INT_PASSIVE_DATAREADY_IN: in STD_LOGIC; - INT_PASSIVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word - INT_PASSIVE_READ_OUT: out STD_LOGIC; + INT_SLAVE_DATAREADY_IN: in STD_LOGIC; + INT_SLAVE_DATA_IN: in STD_LOGIC_VECTOR (50 downto 0); -- Data word + INT_SLAVE_READ_OUT: out STD_LOGIC; -- Status and control port STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) @@ -177,23 +177,23 @@ begin APL_SEQNR_OUT => APL_SEQNR_OUT, -- Internal direction port - INT_ACTIVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, - INT_ACTIVE_DATA_OUT => INT_REPLY_DATA_OUT, - INT_ACTIVE_READ_IN => INT_REPLY_READ_IN, + INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, + INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT, + INT_MASTER_READ_IN => INT_REPLY_READ_IN, - INT_ACTIVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN, - INT_ACTIVE_DATA_IN => INT_REPLY_DATA_IN, - INT_ACTIVE_READ_OUT => INT_REPLY_READ_OUT, + INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN, + INT_MASTER_DATA_IN => INT_REPLY_DATA_IN, + INT_MASTER_READ_OUT => INT_REPLY_READ_OUT, - INT_PASSIVE_HEADER_IN => INT_REPLY_HEADER_IN, + INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN, - INT_PASSIVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, - INT_PASSIVE_DATA_OUT => INT_INIT_DATA_OUT, - INT_PASSIVE_READ_IN => INT_INIT_READ_IN, + INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, + INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT, + INT_SLAVE_READ_IN => INT_INIT_READ_IN, - INT_PASSIVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, - INT_PASSIVE_DATA_IN => INT_INIT_DATA_IN, - INT_PASSIVE_READ_OUT => INT_INIT_READ_OUT, + INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN, + INT_SLAVE_DATA_IN => INT_INIT_DATA_IN, + INT_SLAVE_READ_OUT => INT_INIT_READ_OUT, -- Status and control port STAT_FIFO_TO_INT => STAT_FIFO_TO_INT, STAT_FIFO_TO_APL => STAT_FIFO_TO_APL -- 2.43.0