From 601cbca0ad00568d58fbcbd52063bf19cf94954b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 9 Dec 2008 10:40:23 +0000 Subject: [PATCH] included fixes for synplify/win --- etrax_interface.vhd | 10 +++--- lattice/ecp2m/trb_net16_fifo_arch.vhd | 1 - special/trb_net_bridge_etrax_apl.vhd | 12 ++++--- special/trb_net_bridge_etrax_endpoint.vhd | 6 ++-- trb_net16_addresses.vhd | 6 ++-- trb_net16_api_base.vhd | 12 ++++--- trb_net16_endpoint_0_trg_1_api.vhd | 1 + trb_net16_hub_base.vhd | 2 -- trb_net16_ibuf.vhd | 11 ++++-- trb_net16_io_multiplexer.vhd | 7 ++-- trb_net16_med_ecp_sfp.vhd | 42 ++++++++++++----------- trb_net16_med_tlk.vhd | 8 ++--- trb_net16_obuf.vhd | 18 +++++----- trb_net16_regIO.vhd | 11 +++--- trb_net16_term.vhd | 2 +- 15 files changed, 78 insertions(+), 71 deletions(-) diff --git a/etrax_interface.vhd b/etrax_interface.vhd index a0f398f..3ace9bc 100644 --- a/etrax_interface.vhd +++ b/etrax_interface.vhd @@ -267,8 +267,8 @@ begin if rising_edge(CLK) then stat_num := conv_integer(saved_address(3 downto 0)); ctrl_num := conv_integer(saved_address(3 downto 0)); - case saved_rw_mode(14 downto 0) is - when "000000000000000" => +-- case saved_rw_mode(14 downto 0) is +-- when "000000000000000" => if saved_rw_mode(15) = '1' then if saved_address(15 downto 8) = 0 then if saved_address(7 downto 4) = 0 then --status regs @@ -284,9 +284,9 @@ begin elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data; end if; - when others => - saved_data_fpga <= x"deadface"; - end case; +-- when others => +-- saved_data_fpga <= x"deadface"; +-- end case; end if; end process DATA_SOURCE_SELECT; end architecture; diff --git a/lattice/ecp2m/trb_net16_fifo_arch.vhd b/lattice/ecp2m/trb_net16_fifo_arch.vhd index e5a720c..f4dc140 100644 --- a/lattice/ecp2m/trb_net16_fifo_arch.vhd +++ b/lattice/ecp2m/trb_net16_fifo_arch.vhd @@ -83,7 +83,6 @@ end component; signal din, dout : std_logic_vector(c_DATA_WIDTH +1 downto 0); - signal depth16 : std_logic_vector(7 downto 0); begin din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd index 07571e8..4c0e1bd 100644 --- a/special/trb_net_bridge_etrax_apl.vhd +++ b/special/trb_net_bridge_etrax_apl.vhd @@ -55,7 +55,7 @@ end entity; --2c4 r number of received 32bit words receiver_counter 10bit used ---3c0 (7..0) seq_num api_status +--3c0 (7..0) seq_num apis_tatus @@ -168,7 +168,7 @@ begin when x"30" => next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32); when others => - next_CPU_DATA_OUT <= "1000000000000000000" & CTRL(31 downto 19); + next_CPU_DATA_OUT <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19); end case; -- end if; end process; @@ -206,10 +206,12 @@ begin gen_api_connect : for i in 0 to 2**(c_MUX_WIDTH)-1 generate APL_DTYPE_OUT(i*4+3 downto i*4) <= sender_control(i*32+3 downto i*32); api_status(i*32+7 downto i*32) <= APL_SEQNR_IN(i*8+7 downto i*8); + api_status(i*32+31 downto i*32+8) <= (others => '0'); -- APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) -- <= fifo_pci_to_net_dout((c_DATA_WIDTH+c_NUM_WIDTH)*i+c_DATA_WIDTH-1 downto (c_DATA_WIDTH+c_NUM_WIDTH)*i); -- APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= fifo_pci_to_net_dout; sender_status(i*32) <= APL_RUN_IN(i); + sender_status(i*32+31 downto i*32+1) <= (others => '0'); --api_status(i*32+10 downto i*32+8) <= APL_TYP_IN; next_APL_SEND_OUT(i) <= '1' when reg_CPU_ADDRESS(11 downto 8) = "0001" and reg_CPU_ADDRESS(7 downto 4) = i @@ -239,7 +241,7 @@ begin fifo_net_to_pci_dout(i*32+31 downto i*32+25) <= (others => '0'); fifo_net_to_pci_dout(i*32+23 downto i*32+18) <= (others => '0'); fifo_net_to_pci_dout(i*32+24) <= fifo_net_to_pci_valid_read(i); - fifo_net_to_pci_din(32*i+c_DATA_WIDTH+c_NUM_WIDTH-1 downto 32*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); + fifo_net_to_pci_din(32*i+c_DATA_WIDTH+1 downto 32*i) <= APL_PACKET_NUM_IN(c_NUM_WIDTH*i+2) & APL_PACKET_NUM_IN(c_NUM_WIDTH*i) & APL_DATA_IN(c_DATA_WIDTH*(i+1)-1 downto c_DATA_WIDTH*i); APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH-1 downto i*32); APL_PACKET_NUM_OUT((i)*3+1 downto i*3) <= fifo_pci_to_net_dout(i*32+c_DATA_WIDTH+1 downto i*32+c_DATA_WIDTH); APL_PACKET_NUM_OUT(i*3+2) <= '0'; @@ -315,11 +317,11 @@ process(CLK) end if; end process; - process(CPU_ADDRESS, buf_CPU_DATA_OUT, fifo_net_to_pci_dout,reg_CPU_ADDRESS) + process(CPU_ADDRESS, buf_CPU_DATA_OUT, fifo_net_to_pci_dout,reg_CPU_ADDRESS, last_fifo_read, buf_CPU_DATAREADY_OUT) begin last_CPU_ADDRESS <= CPU_ADDRESS; if reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) = x"23" then - CPU_DATA_OUT <= fifo_net_to_pci_dout((conv_integer(reg_CPU_ADDRESS(6 downto 4))+1)*32-1 downto conv_integer(reg_CPU_ADDRESS(6 downto 4))*32); + CPU_DATA_OUT <= fifo_net_to_pci_dout((conv_integer(reg_CPU_ADDRESS(6 downto 4)))*32+31 downto conv_integer(reg_CPU_ADDRESS(6 downto 4))*32); b_CPU_DATAREADY_OUT <= last_fifo_read; else CPU_DATA_OUT <= buf_CPU_DATA_OUT; diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd index 7983b0c..ea33983 100644 --- a/special/trb_net_bridge_etrax_endpoint.vhd +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -340,8 +340,8 @@ begin MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - - MPLEX: trb_net16_io_multiplexer + MPLEX_CTRL <= (others => '0'); + THE_MPLEX: trb_net16_io_multiplexer port map ( CLK => CLK, RESET => RESET_i, @@ -365,6 +365,7 @@ begin CTRL => MPLEX_CTRL ); + STAT_CTRL_INIT_BUFFER <= (others => '0'); gen_iobufs : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate IOBUF: trb_net16_iobuf port map ( @@ -575,6 +576,7 @@ STAT_ENDP(11 downto 8) <= APL_DATA_IN(3 downto 0); STAT_ENDP(13 downto 12) <= APL_PACKET_NUM_IN(4 downto 3); STAT_ENDP(14) <= APL_DATAREADY_IN(1); STAT_ENDP(15) <= buf_to_apl_REPLY_DATAREADY(0); +STAT_ENDP(31 downto 16) <= (others => '0'); STAT_API1 <= buf_api_stat_fifo_to_int((2)*32-1 downto (1)*32); end architecture; \ No newline at end of file diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd index 96f7ae2..bc23950 100644 --- a/trb_net16_addresses.vhd +++ b/trb_net16_addresses.vhd @@ -89,7 +89,7 @@ begin ram_read_addr <= ram_read_addr1 or ram_read_addr2; - read_id : process(CLK) + proc_read_id : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then @@ -148,7 +148,7 @@ begin end if; end process; - send_ack : process(state, API_READ_IN, ram_read_dout, last_ram_read_addr2, sending_state) + proc_send_ack : process(state, API_READ_IN, ram_read_dout, last_ram_read_addr2, sending_state) begin next_state <= state; API_DATA_OUT <= ram_read_dout; @@ -239,7 +239,7 @@ begin end if; end process; - STAT_RAM : ram_16x16_dp + THE_STAT_RAM : ram_16x16_dp generic map( INIT0 => INIT_UNIQUE_ID(15 downto 0), INIT1 => INIT_UNIQUE_ID(31 downto 16), diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 17715d3..a0aa48e 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -875,11 +875,13 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; --------------------------------------- process(CLK) begin - if rising_edge(CLK) and CLK_EN = '1' then - if slave_start = '1' then - endpoint_reached <= '1'; - elsif master_end = '1' or RESET = '1' then - endpoint_reached <= '0'; + if rising_edge(CLK) then + if CLK_EN = '1' then + if slave_start = '1' then + endpoint_reached <= '1'; + elsif master_end = '1' or RESET = '1' then + endpoint_reached <= '0'; + end if; end if; end if; end process; diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 2ee1391..3711e3b 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -348,6 +348,7 @@ begin reset_internal <= MED_STAT_OP_IN(13) or RESET; MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15); MED_CTRL_OP_OUT(14 downto 0) <= (others => '0'); + STAT_REPLY_BUFFER <= (others => '0'); --Connections for data channel genmuxcon : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 8f58a86..ad856a7 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -463,7 +463,6 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is API_DTYPE_OUT : out std_logic_vector (3 downto 0); API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); API_SEND_OUT : out std_logic; - API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); -- Receiver port API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); @@ -1173,7 +1172,6 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); API_DTYPE_OUT => HC_DTYPE_IN, API_ERROR_PATTERN_OUT => HC_ERROR_PATTERN_IN, API_SEND_OUT => HC_SEND_IN, - API_TARGET_ADDRESS_OUT => open, -- Receiver port API_DATA_IN => HC_DATA_OUT, API_PACKET_NUM_IN => HC_PACKET_NUM_OUT, diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index db9baa8..bb87f20 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -142,7 +142,11 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal throw_away : std_logic; signal fifo_read_before : std_logic; signal stat_sbufs : std_logic_vector(1 downto 0); + signal counter_match : std_logic; begin + +counter_match <= '1'; + ------------------------ --the input fifo ------------------------ @@ -229,7 +233,7 @@ begin if current_fifo_packet_type = TYPE_TRM or (current_fifo_packet_type = TYPE_EOB) then CRC_enable <= '0'; end if; - if current_fifo_packet_type = TYPE_EOB and fifo_long_packet_num_out = c_F3 then + if (current_fifo_packet_type = TYPE_EOB or current_fifo_packet_type = TYPE_TRM) and fifo_long_packet_num_out = c_F0 then CRC_enable <= '1'; end if; end process; @@ -243,7 +247,7 @@ begin ------------------------ --control incoming data ------------------------ - FILTER_DATA_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN, MED_PACKET_NUM_IN, + FILTER_DATA_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_PACKET_NUM_IN, fifo_full, current_rec_buffer_size_out, current_error_state, reg_read_out, current_packet_type) begin -- process @@ -372,7 +376,7 @@ begin process(fifo_data_out, fifo_long_packet_num_out, sbuf_init_free, RESET, fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type, - fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN, CRC_match) + fifo_read_before, CRC_match) begin tmp_INT_DATA_OUT <= fifo_data_out; @@ -386,6 +390,7 @@ begin if USE_CHECKSUM = 1 then if current_fifo_packet_type = TYPE_TRM and fifo_long_packet_num_out = c_F2 then tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match; + tmp_INT_DATA_OUT(4) <= fifo_data_out(4) or not counter_match; CRC_RESET <= '1'; end if; end if; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index ec193c7..5ae8ef5 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -89,7 +89,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is ); end component; - signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH-1)-1 downto 0); + signal current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH-1)-1 downto 0); signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC; signal final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); @@ -143,8 +143,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- demux_next_READ <= (others => '1'); MED_READ_OUT <= current_MED_READ_OUT; - comb_demux : process (next_demux_dr_tmp, INT_READ_IN, - MED_DATAREADY_IN, current_MED_READ_OUT, + comb_demux : process (next_demux_dr_tmp, MED_DATAREADY_IN, current_MED_READ_OUT, MED_PACKET_NUM_IN, demux_dr_tmp) begin next_demux_dr <= demux_dr_tmp; --(others => '0'); @@ -226,7 +225,7 @@ ARBITER: trb_net_priority_arbiter arbiter_CLK_EN <= CLK_EN and not next_endpoint_locked; -- we have to care to read four packets from every endpoint - process(current_mux_buffer, mux_read, endpoint_locked, current_mux_packet_number) + process(mux_read, endpoint_locked, current_mux_packet_number) begin next_endpoint_locked <= endpoint_locked; if current_mux_packet_number = "011" and mux_read = '1' then diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd index a7771ef..700516a 100644 --- a/trb_net16_med_ecp_sfp.vhd +++ b/trb_net16_med_ecp_sfp.vhd @@ -193,16 +193,16 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is type STATES is ( SLEEP, QRST, WPAR, WLOS, ALIGN, WRXA, WTXA, LINK ); signal CURRENT_STATE, NEXT_STATE: STATES; signal state_bits : std_logic_vector(3 downto 0); - signal clock : std_logic; + signal clock : std_logic; - signal med_error_x : std_logic_vector(2 downto 0); - signal med_error : std_logic_vector(2 downto 0); + signal med_error_x : std_logic_vector(2 downto 0); + signal med_error : std_logic_vector(2 downto 0); signal timing_ctr : std_logic_vector(28 downto 0); signal ce_ctr_x : std_logic; - signal ce_ctr : std_logic; - signal rst_ctr_x : std_logic; - signal rst_ctr : std_logic; + signal ce_ctr : std_logic; + signal rst_ctr_x : std_logic; + signal rst_ctr : std_logic; signal quad_rst_x : std_logic; signal quad_rst : std_logic; signal lane_rst_x : std_logic; @@ -214,11 +214,11 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is signal align_me_x : std_logic; signal align_me : std_logic; signal resync_x : std_logic; - signal resync : std_logic; + signal resync : std_logic; signal reset_me_x : std_logic; signal reset_me : std_logic; - signal rx_k_q : std_logic_vector(1 downto 0); + signal rx_k_q : std_logic_vector(1 downto 0); signal info_led : std_logic; @@ -227,18 +227,19 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is signal swap_bytes : std_logic; -- status inputs from SFP - signal sfp_prsnt_n : std_logic; -- synchronized input signals - signal sfp_los : std_logic; -- synchronized input signals + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals - signal buf_STAT_OP : std_logic_vector(15 downto 15); + signal buf_STAT_OP : std_logic_vector(15 downto 15); signal buf_RESET_TRBNET_OUT : std_logic; - signal resync_counter : std_logic_vector(2 downto 0); - signal internal_reset : std_logic; - signal send_resync_counter : std_logic_vector(11 downto 0); - signal next_send_resync, send_resync : std_logic; + signal resync_counter : std_logic_vector(2 downto 0); + signal internal_reset : std_logic; + signal send_resync_counter : std_logic_vector(11 downto 0); + signal next_send_resync : std_logic; + signal send_resync : std_logic; - signal led_counter : std_logic_vector(17 downto 0); - signal rx_led, tx_led : std_logic; + signal led_counter : std_logic_vector(17 downto 0); + signal rx_led, tx_led : std_logic; begin @@ -335,7 +336,8 @@ begin end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, sfp_prsnt_n, sfp_los, timing_ctr, link_error, rst_ctr, link_ok, rx_k_q ) +PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_prsnt_n, sfp_los, timing_ctr, link_error, rst_ctr, + link_ok, rx_k_q, send_resync ) begin NEXT_STATE <= SLEEP; -- avoid latches ce_ctr_x <= '0'; @@ -667,13 +669,13 @@ end process; buf_RESET_TRBNET_OUT <= '0'; end if; if buf_MED_DATAREADY_OUT = '1' then - if fifo_rx_dout(7 downto 0) = x"7F" then + if fifo_rx_dout(15 downto 0) = x"7F7F" then resync_counter <= resync_counter + 1; else resync_counter <= "000"; end if; end if; - if resync_counter(2) = '1' or sfp_los = '1' then + if resync_counter(2) = '1' or sfp_los = '1' or link_error(7 downto 6) /= "00" then resync_counter <= resync_counter + 1; buf_STAT_OP(15) <= '1'; buf_RESET_TRBNET_OUT <= '1'; diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 1724809..6e829e8 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -126,7 +126,6 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal counter_reset : std_logic; signal resync_counter : std_logic_vector(2 downto 0); - signal buf_STAT_OP : std_logic_vector(15 downto 0); signal send_resync : std_logic_vector(0 downto 0); signal send_resync_counter : std_logic_vector(11 downto 0); signal next_send_resync : std_logic_vector(0 downto 0); @@ -301,14 +300,13 @@ begin process(CLK) begin if rising_edge(CLK) then - buf_STAT_OP(15) <= '0'; buf_RESET_TRBNET_OUT <= '0'; if RESET = '1' or internal_reset = '1' then buf_RESET_TRBNET_OUT <= '1'; resync_counter <= "000"; end if; if buf_MED_DATAREADY_OUT = '1' then - if fifo_dout_a(15 downto 0) = x"007F" then + if fifo_dout_a(15 downto 0) = x"7F7F" then resync_counter <= resync_counter + 1; else resync_counter <= "000"; @@ -316,11 +314,9 @@ begin end if; if resync_counter(2) = '1' or SFP_LOS = '1' then resync_counter <= resync_counter + 1; - buf_STAT_OP(15) <= '1'; buf_RESET_TRBNET_OUT <= '1'; end if; if resync_counter = "111" then - buf_STAT_OP(15) <= '0'; buf_RESET_TRBNET_OUT <= '0'; end if; end if; @@ -429,7 +425,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); if send_resync(0) = '0' then reg_TXD <= fifo_dout_m(15 downto 0); else - reg_TXD <= x"007F"; + reg_TXD <= x"7F7F"; end if; reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or send_resync(0); --last_fifo_rd_en_m; end if; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index b0c86cb..eb2168e 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -193,22 +193,22 @@ begin end generate; GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN, - CURRENT_DATA_COUNT, CRC) + CURRENT_DATA_COUNT, CRC, saved_packet_type) begin current_NOP_word <= (others => '0'); current_ACK_word <= (others => '0'); current_EOB_word <= (others => '0'); current_DATA_word <= INT_DATA_IN; - if transfer_counter = c_F1 then + if transfer_counter = c_F0 then + current_EOB_word <= CRC; + if saved_packet_type = TYPE_TRM then + current_DATA_word <= CRC; + end if; + elsif transfer_counter = c_F1 then current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN; - end if; - if transfer_counter = c_F2 then + elsif transfer_counter = c_F2 then current_EOB_word(DATA_COUNT_WIDTH-1 downto 0) <= CURRENT_DATA_COUNT; - end if; - if transfer_counter = c_F3 then - current_EOB_word <= CRC; - end if; - if transfer_counter = c_H0 then + elsif transfer_counter = c_H0 then current_NOP_word(2 downto 0) <= TYPE_ILLEGAL; current_ACK_word(2 downto 0) <= TYPE_ACK; current_EOB_word(2 downto 0) <= TYPE_EOB; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 58a4967..e29257e 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -11,13 +11,13 @@ use work.trb_net_std.all; entity trb_net16_regIO is generic ( - NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers - NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers + NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); --set to 0 for unused ctrl registers to save resources - USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00001111"; --set to 0 for each unused bit in a register USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); @@ -62,8 +62,8 @@ entity trb_net16_regIO is MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); --Custom Register in / out REGISTERS_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); REGISTERS_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); @@ -505,6 +505,7 @@ begin end case; if API_TYP_IN = TYPE_TRM then next_state <= DAT_START_READ; + DAT_READ_ENABLE_OUT <= '1'; end if; end if; diff --git a/trb_net16_term.vhd b/trb_net16_term.vhd index 856d87b..81c1476 100644 --- a/trb_net16_term.vhd +++ b/trb_net16_term.vhd @@ -87,9 +87,9 @@ begin transfer_counter, INT_READ_IN, saved_packet_type, buf_APL_ERROR_PATTERN_IN, buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT) begin + next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; if USE_APL_PORT = 1 then next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; next_APL_GOT_TRM <= reg_APL_GOT_TRM; if saved_packet_type = TYPE_TRM then if INT_PACKET_NUM_IN = c_F3 then -- 2.43.0