From 616994daa1449977ad5c5a560566e3cd4391b079 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Thu, 6 Nov 2014 09:10:48 +0100 Subject: [PATCH] CBMNet: Reboot DLM availabe (send 3 DLMS: 0xd, 0x1, 0xe). Optional GBE disable --- cbmnet/code/cbmnet_bridge.vhd | 54 ++++++++++++++++++++++++++++ cbmnet/code/cbmnet_interface_pkg.vhd | 2 ++ cbmnet/code/cbmnet_readout.vhd | 30 ++++++++++++---- 3 files changed, 79 insertions(+), 7 deletions(-) diff --git a/cbmnet/code/cbmnet_bridge.vhd b/cbmnet/code/cbmnet_bridge.vhd index be87594..7150235 100644 --- a/cbmnet/code/cbmnet_bridge.vhd +++ b/cbmnet/code/cbmnet_bridge.vhd @@ -22,6 +22,8 @@ entity cbmnet_bridge is CBM_CLK_OUT : out std_logic; CBM_RESET_OUT: out std_logic; + REBOOT_FPGA_OUT : out std_logic; + -- Media Interface SD_RXD_P_IN : in std_logic := '0'; SD_RXD_N_IN : in std_logic := '0'; @@ -178,6 +180,9 @@ architecture cbmnet_bridge_arch of cbmnet_bridge is signal cbm_data2send_buf_i : std_logic_vector(15 downto 0); signal cbm_phy_ctrl_i : std_logic_vector(31 downto 0); + + signal cbm_reboot_fpga_i : std_logic; + -- regio signal regio_rx, rdo_regio_rx, phy_regio_rx, sync_regio_rx : CTRLBUS_RX; @@ -194,6 +199,9 @@ architecture cbmnet_bridge_arch of cbmnet_bridge is signal trb_data_override_i : std_logic_vector(16 downto 0); signal cbm_data_override_i : std_logic_vector(16 downto 0); +-- reboot fsm + type RB_FSM_STATES is (WAIT_FOR_D, WAIT_FOR_1, WAIT_FOR_E, REBOOT); + signal rb_fsm_i : RB_FSM_STATES; begin THE_CBM_PHY: cbmnet_phy_ecp3 generic map ( @@ -624,4 +632,50 @@ begin REGIO_WRITE_ACK_OUT <= regio_tx.ack; REGIO_NO_MORE_DATA_OUT <= regio_tx.nack; REGIO_UNKNOWN_ADDR_OUT <= regio_tx.unknown; + + +-- REBOOT via DLM + THE_DLM_REBOOT: process + begin + cbm_reboot_fpga_i <= '0'; + if cbm_link_active_i='0' then + rb_fsm_i <= WAIT_FOR_D; + else + case (rb_fsm_i) is + when WAIT_FOR_D => + if cbm_dlm_rec_va_i='1' and cbm_dlm_rec_type_i=x"d" then + rb_fsm_i <= WAIT_FOR_1; + end if; + + when WAIT_FOR_1 => + if cbm_dlm_rec_va_i='1' then + if cbm_dlm_rec_type_i=x"1" then + rb_fsm_i <= WAIT_FOR_E; + else + rb_fsm_i <= WAIT_FOR_D; + end if; + end if; + + when WAIT_FOR_E => + if cbm_dlm_rec_va_i='1' then + if cbm_dlm_rec_type_i=x"E" then + rb_fsm_i <= REBOOT; + else + rb_fsm_i <= WAIT_FOR_D; + end if; + end if; + + when REBOOT => + cbm_reboot_fpga_i <= '1'; + end case; + end if; + end process; + + THE_REBOOT_SYNC: pos_edge_strech_sync + port map ( + IN_CLK_IN => cbm_clk_i, + DATA_IN => cbm_reboot_fpga_i, + OUT_CLK_IN => TRB_CLK_IN, + DATA_OUT => REBOOT_FPGA_OUT + ); end architecture; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index b7fb336..e7ae02e 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -19,6 +19,8 @@ package cbmnet_interface_pkg is CBM_CLK_OUT : out std_logic; CBM_RESET_OUT: out std_logic; + REBOOT_FPGA_OUT: out std_logic; + -- Media Interface SD_RXD_P_IN : in std_logic := '0'; SD_RXD_N_IN : in std_logic := '0'; diff --git a/cbmnet/code/cbmnet_readout.vhd b/cbmnet/code/cbmnet_readout.vhd index fa97033..f05b791 100644 --- a/cbmnet/code/cbmnet_readout.vhd +++ b/cbmnet/code/cbmnet_readout.vhd @@ -137,22 +137,25 @@ architecture cbmnet_readout_arch of CBMNET_READOUT is signal regio_data_ready_i : std_logic; signal regio_unkown_address_i : std_logic; - signal cfg_enabled_i : std_logic; + signal cfg_enabled_i : std_logic; + signal cfg_include_gbe_i : std_logic := '1'; signal cfg_source_i : std_logic_vector(15 downto 0); signal cfg_source_override_i : std_logic; + + signal gbe_include_i : std_logic := '1'; begin GBE_CTS_NUMBER_OUT <= HUB_CTS_NUMBER_IN; GBE_CTS_CODE_OUT <= HUB_CTS_CODE_IN; GBE_CTS_INFORMATION_OUT <= HUB_CTS_INFORMATION_IN; GBE_CTS_READOUT_TYPE_OUT <= HUB_CTS_READOUT_TYPE_IN; - GBE_CTS_START_READOUT_OUT <= HUB_CTS_START_READOUT_IN; + GBE_CTS_START_READOUT_OUT <= HUB_CTS_START_READOUT_IN and gbe_include_i; GBE_FEE_DATA_OUT <= HUB_FEE_DATA_IN; - GBE_FEE_DATAREADY_OUT <= HUB_FEE_DATAREADY_IN; + GBE_FEE_DATAREADY_OUT <= HUB_FEE_DATAREADY_IN and gbe_include_i; GBE_FEE_STATUS_BITS_OUT <= HUB_FEE_STATUS_BITS_IN; - GBE_FEE_BUSY_OUT <= HUB_FEE_BUSY_IN; + GBE_FEE_BUSY_OUT <= HUB_FEE_BUSY_IN and gbe_include_i; - HUB_FEE_READ_OUT <= GBE_FEE_READ_IN; - HUB_CTS_READOUT_FINISHED_OUT <= GBE_CTS_READOUT_FINISHED_IN; + HUB_FEE_READ_OUT <= GBE_FEE_READ_IN or not gbe_include_i; + HUB_CTS_READOUT_FINISHED_OUT <= GBE_CTS_READOUT_FINISHED_IN or not gbe_include_i; HUB_CTS_STATUS_BITS_OUT <= GBE_CTS_STATUS_BITS_IN; proc_reset: process is @@ -453,7 +456,9 @@ begin -- read case addr is - when 16#00# => regio_data_status_i(0) <= cfg_enabled_i; + when 16#00# => + regio_data_status_i(0) <= cfg_enabled_i; + regio_data_status_i(1) <= cfg_include_gbe_i; when 16#01# => regio_data_status_i(16 downto 0) <= cfg_source_override_i & cfg_source_i; when 16#02# => regio_data_status_i <= std_logic_vector(stat_connections_i); regio_data_ready_i <= trb_from_cbm_sync_ack_i; @@ -486,6 +491,7 @@ begin case addr is when 16#0# => cfg_enabled_i <= REGIO_IN.data(0); + cfg_include_gbe_i <= REGIO_IN.data(1); when 16#1# => cfg_source_i <= REGIO_IN.data(15 downto 0); @@ -495,6 +501,16 @@ begin regio_unkown_address_i <= '1'; end case; end if; + + if RESET_IN = '1' then + cfg_enabled_i <= '0'; + cfg_include_gbe_i <= '1'; + end if; + + -- make sure, we enable/disable gbe not during an ongoing rdo + if HUB_CTS_START_READOUT_IN='0' and HUB_FEE_BUSY_IN='0' then + gbe_include_i <= cfg_include_gbe_i; + end if; end process; -- 2.43.0