From 617d7f8f745269d220e443d74ca0fcdd678c0d41 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Wed, 21 May 2014 15:15:37 +0200 Subject: [PATCH] Adjusted check list necessary to create a new project --- trb3/VhdlProjectSetup.tex | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/trb3/VhdlProjectSetup.tex b/trb3/VhdlProjectSetup.tex index 7694ca0..f64bcaf 100644 --- a/trb3/VhdlProjectSetup.tex +++ b/trb3/VhdlProjectSetup.tex @@ -4,13 +4,10 @@ A not complete list of steps how to create a new TRB3 VHDL project. \item Create a new subdirectory inside \cmdname{./trb3/}. Choose a short, descriptive name for the project. Change to this directory. \item Create subdirectories \begin{description*} -\item[\files{workdir}] where all generated files during synthesis, map and par are stored \item[\files{code}] for your own vhd codes for this project \item[\files{cores}] for generated ipcores \item[\files{sim}] for the simulation project -\item[\files{project}] if you want to create a Lattice Diamond Project \end{description*} -\item Go to workdir and execute \cmdname{../../base/linkdesignfiles.sh}. This has to be repeated in \files{project/\$projectname}. \item Copy necessary files from another project. Choose one using the same FPGA you want to create your project and if possible one that uses the same pinout. \begin{description*} \item[\files{compile*.pl}] The main script that runs synthesis, map, par... @@ -19,11 +16,20 @@ A not complete list of steps how to create a new TRB3 VHDL project. \item[\files{*.p2t}] Settings for the place and route tool \item[\files{*.vhd}] The top-level vhd file as basis for the new design \end{description*} +\item Edit \files{compile\_constraints.pl} +This script takes one optional parameter pointing to the workdir \emph{relative to the script itself} (if omitted, \files{./workdir/} is assumed). +The program is invoked by the other \files{compile*.pl} scripts and the \files{/base/create\_project.pl} tool and has the following tasks: +\begin{itemize*} +\item Create the workdir if not existing +\item Execute \files{base/linkdesignfiles.sh} with the correct parameters to account for a varing number of \files{../} of the relative links generate +and depending on the position of the workdir relative to the repositories root directory. +\item Combine global and design specific \files{*.lpf}-files into a single file \files{\{workdir\}/\{topname\}.lpf}. +\item Optional: Generate design specific script that are invoked in the build process. +\end{itemize*} \item Edit \files{compile*.pl} \begin{itemize*} \item Set the \cmdname{\$projectname} \item Check that all configuration options (the marked block in the beginning of the file) match your local environment. -\item Check the 2 to 4 lines generating the constraint file if it accesses the correct files. One file from the base directory gives the pin-out, a local file gives the project-dependent constraints. For TDCs, another file is included. \end{itemize*} \item Edit \files{\$projectname.prj} \begin{itemize*} @@ -31,4 +37,9 @@ A not complete list of steps how to create a new TRB3 VHDL project. \item Add / Remove source files as necessary \end{itemize*} \item Try to run the compile script. +\item Optional: run \cmdname{base/create\_project.pl} which will generate a diamond project from your \files{*.prj} file. Further, it +executes the \files{compile\_constraints.pl} tool to obtain the constraint and configuration files. You can rerun this program at any time -- +in this the project file are rewritten which may undo manual changes. Observe, that the script only extracts lpf/vhd/v files and outputs +a warning if non-supported files are found in your \files{*.prj} file. + \end{itemize*} -- 2.43.0