From 61968c968f1860325d8da1b1048f3cdd78bd23cb Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Wed, 5 Aug 2020 17:34:35 +0200 Subject: [PATCH] Adapt to media interface changes in trbnet --- endpoint_test/.gitignore | 1 + endpoint_test/constrs/constr.xdc | 21 - endpoint_test/constrs/debug.xdc | 234 - endpoint_test/constrs/endpoint_test.xdc | 19 + endpoint_test/constrs/test.xdc | 4 - endpoint_test/endpoint_test.xpr | 115 +- endpoint_test/ip/clk_wiz_0/clk_wiz_0.xci | 714 + endpoint_test/ip/clk_wiz_0/clk_wiz_0.xml | 4587 ++ endpoint_test/src/endpoint_test.vhd | 321 +- hub_test/.gitignore | 1 + hub_test/bd/design_1/design_1.bd | 1373 + .../design_1_axi_gpio_0_0.xci | 150 + .../design_1_axi_gpio_0_0.xml | 1748 + .../design_1_axi_gpio_0_1.xci | 148 + .../design_1_axi_gpio_0_1.xml | 1746 + .../design_1_axi_iic_0_0.xci | 142 + .../design_1_axi_iic_0_0.xml | 2385 + .../design_1_axi_timer_0_0.xci | 130 + .../design_1_axi_timer_0_0.xml | 1683 + .../design_1_dlmb_bram_if_cntlr_0.xci | 179 + .../design_1_dlmb_bram_if_cntlr_0.xml | 4012 + .../design_1_dlmb_v10_0.xci | 142 + .../design_1_dlmb_v10_0.xml | 3527 + .../design_1_ilmb_bram_if_cntlr_0.xci | 179 + .../design_1_ilmb_bram_if_cntlr_0.xml | 4012 + .../design_1_ilmb_v10_0.xci | 142 + .../design_1_ilmb_v10_0.xml | 3527 + .../design_1_lmb_bram_0.xci | 291 + .../design_1_lmb_bram_0.xml | 4153 + .../ip/design_1_mdm_1_0/design_1_mdm_1_0.xci | 1187 + .../ip/design_1_mdm_1_0/design_1_mdm_1_0.xml | 64308 ++++++++++++++++ .../design_1_microblaze_0_0.xci | 1033 + .../design_1_microblaze_0_0.xml | 27482 +++++++ .../design_1_microblaze_0_axi_intc_0.xci | 199 + .../design_1_microblaze_0_axi_intc_0.xml | 4292 ++ .../design_1_microblaze_0_axi_periph_0.xci | 360 + .../design_1_microblaze_0_axi_periph_0.xml | 1644 + .../design_1_microblaze_0_xlconcat_0.xci | 145 + .../design_1_microblaze_0_xlconcat_0.xml | 1257 + .../design_1_rst_Clk_100M_0.xci | 87 + .../design_1_rst_Clk_100M_0.xml | 690 + .../ip/design_1_xbar_0/design_1_xbar_0.xci | 3608 + .../ip/design_1_xbar_0/design_1_xbar_0.xml | 47272 ++++++++++++ hub_test/constrs/hub_test.xdc | 113 +- hub_test/hub_test.xpr | 107 +- hub_test/ip/clk_wiz_0/clk_wiz_0.xci | 714 + hub_test/ip/clk_wiz_0/clk_wiz_0.xml | 4587 ++ hub_test/ip/vio_0/vio_0.xci | 11 +- hub_test/ip/vio_0/vio_0.xml | 32 +- hub_test/scripts/compile.sh | 2 + hub_test/scripts/create_hardware_platform.tcl | 7 + hub_test/scripts/generate_software.tcl | 6 + hub_test/src/hub_test.vhd | 574 +- hub_test/sw/init.c | 174 + 54 files changed, 194614 insertions(+), 963 deletions(-) delete mode 100644 endpoint_test/constrs/constr.xdc delete mode 100644 endpoint_test/constrs/debug.xdc create mode 100644 endpoint_test/constrs/endpoint_test.xdc delete mode 100644 endpoint_test/constrs/test.xdc create mode 100644 endpoint_test/ip/clk_wiz_0/clk_wiz_0.xci create mode 100644 endpoint_test/ip/clk_wiz_0/clk_wiz_0.xml create mode 100644 hub_test/bd/design_1/design_1.bd create mode 100644 hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci create mode 100644 hub_test/bd/design_1/ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xml create mode 100644 hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_axi_iic_0_0/design_1_axi_iic_0_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_axi_timer_0_0/design_1_axi_timer_0_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/design_1_microblaze_0_axi_intc_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_axi_periph_0/design_1_microblaze_0_axi_periph_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_microblaze_0_xlconcat_0/design_1_microblaze_0_xlconcat_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_rst_Clk_100M_0/design_1_rst_Clk_100M_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_rst_Clk_100M_0/design_1_rst_Clk_100M_0.xml create mode 100644 hub_test/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xci create mode 100644 hub_test/bd/design_1/ip/design_1_xbar_0/design_1_xbar_0.xml create mode 100644 hub_test/ip/clk_wiz_0/clk_wiz_0.xci create mode 100644 hub_test/ip/clk_wiz_0/clk_wiz_0.xml create mode 100644 hub_test/scripts/create_hardware_platform.tcl create mode 100644 hub_test/scripts/generate_software.tcl create mode 100644 hub_test/sw/init.c diff --git a/endpoint_test/.gitignore b/endpoint_test/.gitignore index 72e44b5..b83df8a 100644 --- a/endpoint_test/.gitignore +++ b/endpoint_test/.gitignore @@ -2,3 +2,4 @@ /endpoint_test.hw/ /endpoint_test.ip_user_files/ /endpoint_test.runs/ +/endpoint_test.srcs/ diff --git a/endpoint_test/constrs/constr.xdc b/endpoint_test/constrs/constr.xdc deleted file mode 100644 index f08c162..0000000 --- a/endpoint_test/constrs/constr.xdc +++ /dev/null @@ -1,21 +0,0 @@ -set_property PACKAGE_PIN AT18 [get_ports clk_in1_p] -set_property IOSTANDARD LVDS [get_ports clk_in1_p] -create_clock -period 5.000 -name clk_clk_in1_p [get_ports clk_in1_p] - -set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub] -set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] -set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets clk_100] -#set_property PACKAGE_PIN AK38 [get_ports mgtrefclk0_x0y3_n] -#set_property PACKAGE_PIN AK37 [get_ports mgtrefclk0_x0y3_p] -set_property PACKAGE_PIN K10 [get_ports {MPOD_RESET_N[3]}] -set_property PACKAGE_PIN K11 [get_ports {MPOD_RESET_N[2]}] -set_property PACKAGE_PIN G14 [get_ports {MPOD_RESET_N[1]}] -set_property PACKAGE_PIN H14 [get_ports {MPOD_RESET_N[0]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[3]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[2]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[1]}] -set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[0]}] - -set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets THE_ENDPOINT/THE_ENDPOINT/THE_LVL1_HANDLER/tmg_reg0] -set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets THE_ENDPOINT/THE_ENDPOINT/THE_LVL1_HANDLER/tmg_stretch] \ No newline at end of file diff --git a/endpoint_test/constrs/debug.xdc b/endpoint_test/constrs/debug.xdc deleted file mode 100644 index 78878c2..0000000 --- a/endpoint_test/constrs/debug.xdc +++ /dev/null @@ -1,234 +0,0 @@ -create_debug_core u_ila_1 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU_CNT 3 [get_debug_cores u_ila_1] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] -set_property port_width 1 [get_debug_ports u_ila_1/clk] -connect_debug_port u_ila_1/clk [get_nets [list THE_SYSCLK/clk_out1]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] -set_property port_width 1 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {med2int[0][stat_op][13]}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] -set_property port_width 1 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list reset_all]] -create_debug_core u_ila_2 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] -set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_2] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] -set_property port_width 1 [get_debug_ports u_ila_2/clk] -connect_debug_port u_ila_2/clk [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/CLK_SYS]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] -set_property port_width 16 [get_debug_ports u_ila_2/probe0] -connect_debug_port u_ila_2/probe0 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][7]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][9]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][10]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][11]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][12]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][13]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][14]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[data][15]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] -set_property port_width 3 [get_debug_ports u_ila_2/probe1] -connect_debug_port u_ila_2/probe1 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[packet_num][0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[packet_num][1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[packet_num][2]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] -set_property port_width 1 [get_debug_ports u_ila_2/probe2] -connect_debug_port u_ila_2/probe2 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/media_med2int_i[dataready]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] -set_property port_width 16 [get_debug_ports u_ila_2/probe3] -connect_debug_port u_ila_2/probe3 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][7]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][9]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][10]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][11]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][12]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][13]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][14]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[data][15]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4] -set_property port_width 3 [get_debug_ports u_ila_2/probe4] -connect_debug_port u_ila_2/probe4 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[packet_num][0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[packet_num][1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[packet_num][2]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5] -set_property port_width 1 [get_debug_ports u_ila_2/probe5] -connect_debug_port u_ila_2/probe5 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/MEDIA_INT2MED[dataready]}]] -create_debug_port u_ila_2 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6] -set_property port_width 8 [get_debug_ports u_ila_2/probe6] -connect_debug_port u_ila_2/probe6 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/RX_DATA[7]}]] -create_debug_core u_ila_3 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3] -set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_3] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_3] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_3] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_3] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_3] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3] -set_property port_width 1 [get_debug_ports u_ila_3/clk] -connect_debug_port u_ila_3/clk [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/CLK_200]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe0] -set_property port_width 1 [get_debug_ports u_ila_3/probe0] -connect_debug_port u_ila_3/probe0 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/ct_fifo_write]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe1] -set_property port_width 18 [get_debug_ports u_ila_3/probe1] -connect_debug_port u_ila_3/probe1 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[7]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[9]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[10]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[11]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[12]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[13]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[14]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[15]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[16]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_data[17]}]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe2] -set_property port_width 4 [get_debug_ports u_ila_3/probe2] -connect_debug_port u_ila_3/probe2 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_state_bits[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_state_bits[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_state_bits[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_state_bits[3]}]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe3] -set_property port_width 8 [get_debug_ports u_ila_3/probe3] -connect_debug_port u_ila_3/probe3 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_data_in[7]}]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe4] -set_property port_width 1 [get_debug_ports u_ila_3/probe4] -connect_debug_port u_ila_3/probe4 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reg_rx_k_in]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe5] -set_property port_width 1 [get_debug_ports u_ila_3/probe5] -connect_debug_port u_ila_3/probe5 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/reset_i]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe6] -set_property port_width 3 [get_debug_ports u_ila_3/probe6] -connect_debug_port u_ila_3/probe6 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_packet_num[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_packet_num[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/rx_packet_num[2]}]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe7] -set_property port_width 1 [get_debug_ports u_ila_3/probe7] -connect_debug_port u_ila_3/probe7 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/trbnetReset]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe8] -set_property port_width 1 [get_debug_ports u_ila_3/probe8] -connect_debug_port u_ila_3/probe8 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/make_reset_trbnet_i]] -create_debug_port u_ila_3 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe9] -set_property port_width 10 [get_debug_ports u_ila_3/probe9] -connect_debug_port u_ila_3/probe9 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[7]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_CONTROL/tn_reset_wrd_cnt[9]}]] -create_debug_core u_ila_4 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_4] -set_property ALL_PROBE_SAME_MU_CNT 3 [get_debug_cores u_ila_4] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_4] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_4] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_4] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_4] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_4] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_4] -set_property port_width 1 [get_debug_ports u_ila_4/clk] -connect_debug_port u_ila_4/clk [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/CLK_100]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_4/probe0] -set_property port_width 16 [get_debug_ports u_ila_4/probe0] -connect_debug_port u_ila_4/probe0 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[7]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[9]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[10]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[11]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[12]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[13]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[14]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_IN[15]}]] -create_debug_port u_ila_4 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_4/probe1] -set_property port_width 3 [get_debug_ports u_ila_4/probe1] -connect_debug_port u_ila_4/probe1 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_PACKET_NUMBER_IN[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_PACKET_NUMBER_IN[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_PACKET_NUMBER_IN[2]}]] -create_debug_port u_ila_4 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_4/probe2] -set_property port_width 1 [get_debug_ports u_ila_4/probe2] -connect_debug_port u_ila_4/probe2 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_WRITE_IN]] -create_debug_port u_ila_4 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_4/probe3] -set_property port_width 32 [get_debug_ports u_ila_4/probe3] -connect_debug_port u_ila_4/probe3 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[7]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[9]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[10]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[11]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[12]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[13]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[14]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[15]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[16]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[17]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[18]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[19]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[20]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[21]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[22]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[23]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[24]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[25]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[26]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[27]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[28]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[29]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[30]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT[31]}]] -create_debug_core u_ila_5 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_5] -set_property ALL_PROBE_SAME_MU_CNT 3 [get_debug_cores u_ila_5] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_5] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_5] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_5] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_5] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_5] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_5] -set_property port_width 1 [get_debug_ports u_ila_5/clk] -connect_debug_port u_ila_5/clk [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/CLK_200]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_5/probe0] -set_property port_width 8 [get_debug_ports u_ila_5/probe0] -connect_debug_port u_ila_5/probe0 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[6]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_DATA_OUT[7]}]] -create_debug_port u_ila_5 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_5/probe1] -set_property port_width 1 [get_debug_ports u_ila_5/probe1] -connect_debug_port u_ila_5/probe1 [get_nets [list THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_K_OUT]] -create_debug_port u_ila_5 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_5/probe2] -set_property port_width 4 [get_debug_ports u_ila_5/probe2] -connect_debug_port u_ila_5/probe2 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/state_bits[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/state_bits[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/state_bits[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/state_bits[3]}]] -create_debug_port u_ila_5 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_5/probe3] -set_property port_width 32 [get_debug_ports u_ila_5/probe3] -connect_debug_port u_ila_5/probe3 [get_nets [list {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[0]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[1]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[2]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[3]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[4]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[5]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[6]} THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/TX_WRITE_IN {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[8]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[9]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[10]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[11]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[12]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[13]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[14]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[15]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[16]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[17]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[18]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[19]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[20]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[21]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[22]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[23]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[24]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[25]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[26]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[27]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[28]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[29]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[30]} {THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/DEBUG_OUT[31]}]] -create_debug_core u_ila_6 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_6] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_6] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_6] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_6] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_6] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_6] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_6] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_6] -set_property port_width 1 [get_debug_ports u_ila_6/clk] -connect_debug_port u_ila_6/clk [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/clk_200]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe0] -set_property port_width 8 [get_debug_ports u_ila_6/probe0] -connect_debug_port u_ila_6/probe0 [get_nets [list {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[0]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[1]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[2]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[3]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[4]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[5]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[6]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_data[7]}]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe1] -set_property port_width 1 [get_debug_ports u_ila_6/probe1] -connect_debug_port u_ila_6/probe1 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_k]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe2] -set_property port_width 1 [get_debug_ports u_ila_6/probe2] -connect_debug_port u_ila_6/probe2 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_full_i]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe3] -set_property port_width 1 [get_debug_ports u_ila_6/probe3] -connect_debug_port u_ila_6/probe3 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_almfull_i]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe4] -set_property port_width 10 [get_debug_ports u_ila_6/probe4] -connect_debug_port u_ila_6/probe4 [get_nets [list {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[0]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[1]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[2]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[3]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[4]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[5]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[6]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[7]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[8]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_wr_cnt[9]}]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe5] -set_property port_width 1 [get_debug_ports u_ila_6/probe5] -connect_debug_port u_ila_6/probe5 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userclk_tx_usrclk2_i]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe6] -set_property port_width 1 [get_debug_ports u_ila_6/probe6] -connect_debug_port u_ila_6/probe6 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/reset_all]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe7] -set_property port_width 1 [get_debug_ports u_ila_6/probe7] -connect_debug_port u_ila_6/probe7 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userclk_tx_active_i]] -create_debug_port u_ila_6 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_6/probe8] -set_property port_width 1 [get_debug_ports u_ila_6/probe8] -connect_debug_port u_ila_6/probe8 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/reset_tx_done_i]] -create_debug_core u_ila_7 ila -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_7] -set_property ALL_PROBE_SAME_MU_CNT 3 [get_debug_cores u_ila_7] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_7] -set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_7] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_7] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_7] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_7] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_7] -set_property port_width 1 [get_debug_ports u_ila_7/clk] -connect_debug_port u_ila_7/clk [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userclk_tx_usrclk2_i]] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_7/probe0] -set_property port_width 16 [get_debug_ports u_ila_7/probe0] -connect_debug_port u_ila_7/probe0 [get_nets [list {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[0]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[1]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[2]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[3]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[4]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[5]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[6]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[7]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[8]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[9]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[10]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[11]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[12]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[13]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[14]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/userdata_tx_i[15]}]] -create_debug_port u_ila_7 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_7/probe1] -set_property port_width 8 [get_debug_ports u_ila_7/probe1] -connect_debug_port u_ila_7/probe1 [get_nets [list {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[0]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[1]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[2]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[3]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[4]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[5]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[6]} {THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/txctrl2_i[7]}]] -create_debug_port u_ila_7 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_7/probe2] -set_property port_width 1 [get_debug_ports u_ila_7/probe2] -connect_debug_port u_ila_7/probe2 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_empty_i]] -create_debug_port u_ila_7 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_7/probe3] -set_property port_width 1 [get_debug_ports u_ila_7/probe3] -connect_debug_port u_ila_7/probe3 [get_nets [list THE_MEDIA_INTERFACE/gen_pcs0.THE_GTH_8b10b/tx_fifo_valid_i]] -set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub] -set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] -set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets clk_100] diff --git a/endpoint_test/constrs/endpoint_test.xdc b/endpoint_test/constrs/endpoint_test.xdc new file mode 100644 index 0000000..1a4d183 --- /dev/null +++ b/endpoint_test/constrs/endpoint_test.xdc @@ -0,0 +1,19 @@ +set_property PACKAGE_PIN AK38 [get_ports MGTREFCLK_N] +set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK_P] + +create_clock -period 8.000 -name MGTREFCLK_P [get_ports MGTREFCLK_P] + +set_property PACKAGE_PIN AT18 [get_ports CLK_200_P] +set_property IOSTANDARD LVDS [get_ports CLK_200_P] +create_clock -period 5.000 -name CLK_200_P [get_ports CLK_200_P] + +set_property PACKAGE_PIN K10 [get_ports {MPOD_RESET_N[3]}] +set_property PACKAGE_PIN K11 [get_ports {MPOD_RESET_N[2]}] +set_property PACKAGE_PIN G14 [get_ports {MPOD_RESET_N[1]}] +set_property PACKAGE_PIN H14 [get_ports {MPOD_RESET_N[0]}] +set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[3]}] +set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[2]}] +set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[1]}] +set_property IOSTANDARD LVTTL [get_ports {MPOD_RESET_N[0]}] + +set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets THE_ENDPOINT/THE_ENDPOINT/THE_LVL1_HANDLER/tmg_stretch] \ No newline at end of file diff --git a/endpoint_test/constrs/test.xdc b/endpoint_test/constrs/test.xdc deleted file mode 100644 index 7ab87e5..0000000 --- a/endpoint_test/constrs/test.xdc +++ /dev/null @@ -1,4 +0,0 @@ -set_property PACKAGE_PIN AK38 [get_ports mgtrefclk0_x0y3_n] -set_property PACKAGE_PIN AK37 [get_ports mgtrefclk0_x0y3_p] - -create_clock -period 8.000 -name clk_mgtrefclk0_x0y3_p [get_ports mgtrefclk0_x0y3_p] diff --git a/endpoint_test/endpoint_test.xpr b/endpoint_test/endpoint_test.xpr index 2d7c336..aa2f028 100644 --- a/endpoint_test/endpoint_test.xpr +++ b/endpoint_test/endpoint_test.xpr @@ -122,20 +122,6 @@ - - - - - - - - - - - - - - @@ -143,14 +129,7 @@ - - - - - - - - + @@ -164,19 +143,6 @@ - - - - - - - - - - - - - @@ -184,20 +150,6 @@ - - - - - - - - - - - - - - @@ -223,7 +175,7 @@ - + @@ -241,25 +193,13 @@ - - - - - - - - - - - - - + @@ -283,12 +223,6 @@ - - - - - - @@ -355,6 +289,12 @@ + + + + + + @@ -385,7 +325,7 @@ - + @@ -397,6 +337,12 @@ + + + + + + @@ -577,7 +523,13 @@ - + + + + + + + @@ -596,26 +548,13 @@ - - - - - - - - - - - - - + - @@ -632,12 +571,6 @@ - - - - - -