From 619f02b9f558dd42bfe1059a882b0b8474f8a935 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Thu, 22 May 2014 09:22:57 +0200 Subject: [PATCH] Commenting duplicate declaration of FIFO_DC_36x32_OutReg/FIFO_DC_36x16_OutReg --- base/trb3_components.vhd | 64 ++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 5631286..f77ea69 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -521,8 +521,8 @@ package trb3_components is Empty : out std_logic; Full : out std_logic; AlmostFull : out std_logic); - end component FIFO_DC_36x32_OutReg; - + end component; + component FIFO_DC_36x16_OutReg is port ( Data : in std_logic_vector(35 downto 0); @@ -536,7 +536,7 @@ package trb3_components is Empty : out std_logic; Full : out std_logic; AlmostFull : out std_logic); - end component FIFO_DC_36x16_OutReg; + end component; component FIFO_36x128_OutReg_Counter is port ( @@ -553,35 +553,35 @@ package trb3_components is Full : out std_logic); end component FIFO_36x128_OutReg_Counter; - component FIFO_DC_36x32_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; - - component FIFO_DC_36x16_OutReg is - port ( - Data : in std_logic_vector(35 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(35 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; +-- component FIFO_DC_36x32_OutReg is +-- port ( +-- Data : in std_logic_vector(35 downto 0); +-- WrClock : in std_logic; +-- RdClock : in std_logic; +-- WrEn : in std_logic; +-- RdEn : in std_logic; +-- Reset : in std_logic; +-- RPReset : in std_logic; +-- Q : out std_logic_vector(35 downto 0); +-- Empty : out std_logic; +-- Full : out std_logic; +-- AlmostFull : out std_logic); +-- end component; +-- +-- component FIFO_DC_36x16_OutReg is +-- port ( +-- Data : in std_logic_vector(35 downto 0); +-- WrClock : in std_logic; +-- RdClock : in std_logic; +-- WrEn : in std_logic; +-- RdEn : in std_logic; +-- Reset : in std_logic; +-- RPReset : in std_logic; +-- Q : out std_logic_vector(35 downto 0); +-- Empty : out std_logic; +-- Full : out std_logic; +-- AlmostFull : out std_logic); +-- end component; --component FIFO_24x2_OutReg -- port ( -- 2.43.0