From 61aaecbadb76496018a21c21452724f2dca454dc Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 2 Feb 2007 17:30:14 +0000 Subject: [PATCH] test status, Ingo --- compile2a.pl | 8 +-- dsp_interface.vhd | 74 +++++++++++++++++------- etrax_interface.vhd | 14 +++-- impact_batch_a.txt | 4 +- trb_v2a_fpga.ucf | 130 +++++++++++++++++++++---------------------- trb_v2a_fpga.vhd | 75 +++++++++++++++---------- trb_v2a_fpga_syn.prj | 20 +++---- 7 files changed, 188 insertions(+), 137 deletions(-) diff --git a/compile2a.pl b/compile2a.pl index 18e9dbc..43edfe0 100755 --- a/compile2a.pl +++ b/compile2a.pl @@ -16,7 +16,7 @@ $ENV{LM_LICENSE_FILE}="1709@depc140"; $PLD_DEVICE="xc4vlx40-10-ff1148"; -$TOPNAME="rpc_trb_v2_fpga"; +$TOPNAME="trb_v2a_fpga"; @@ -28,7 +28,7 @@ $r=execute($c, "do_not_exit" ); chdir "workdir"; -my $fh = new FileHandle("; $fh -> close; @@ -40,7 +40,7 @@ $fh -> close; foreach (@a) { - if(/Parse errors/) + if(/\@E:/) { $c="cat $TOPNAME.srr"; system($c); @@ -88,7 +88,7 @@ execute($c); # Command line for generate .stapl file # -$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch.txt"; +$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch_a.txt"; execute($c); diff --git a/dsp_interface.vhd b/dsp_interface.vhd index a8c04e5..78fc6bf 100644 --- a/dsp_interface.vhd +++ b/dsp_interface.vhd @@ -12,10 +12,11 @@ entity dsp_interface is HBR_OUT : out std_logic; -- Host Bus Request to DSP HBG_IN : in std_logic; -- Host Bus Grant from DSP RD_OUT : out std_logic; -- read/write enable of DSP - DSP_DATA : inout std_logic_vector(31 downto 0); + DSP_DATA_OUT : out std_logic_vector(31 downto 0); + DSP_DATA_IN : in std_logic_vector(31 downto 0); ADDRESS_DSP : out std_logic_vector(31 downto 0); - WRL : inout std_logic; --when dsp slave is output - WRH : inout std_logic; --when dsp slave is output + WRL : out std_logic; --when dsp slave is output + WRH : out std_logic; --when dsp slave is output BM_IN : in std_logic; --Bus Master. For debug DSP_RESET : out std_logic; BRST : inout std_logic; @@ -25,7 +26,8 @@ entity dsp_interface is RESET : in std_logic; R_W_ENABLE : in std_logic; TRIGGER : in std_logic; - INTERNAL_DATA : inout std_logic_vector(31 downto 0); --63 downto 0 + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); --63 downto 0 + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); --63 downto 0 INTERNAL_ADDRESS : in std_logic_vector(31 downto 0); VALID_DATA_SENT : out std_logic; ACKNOWLEDGE : in std_logic; @@ -38,8 +40,10 @@ architecture dsp_interface of dsp_interface is --signal delaration type state_type is (IDLE, WRITE_DSP_MEMORY, READ_DSP_MEMORY, READ_DSP_MEMORY_NEXT, + READ_DSP_DUMMY, WRITE_DSP_DATA, READ_DSP_WAIT1, READ_DSP_WAIT2, READ_DSP_WAIT3, + READ_DSP_WAIT4, READ_DSP_DATA, READ_DSP_WAIT_FOR_HBR, WRITE_DSP_WAIT_FOR_HBR, WRITE_DSP_DUMMY, SENT_DATA_TO_INTERNAL_ENTITY, @@ -81,8 +85,8 @@ begin -- behavioural --another state, they are default for all the machine --INOUT - DSP_DATA <= (others => 'Z'); - INTERNAL_DATA <= (others => 'Z'); + DSP_DATA_OUT <= (others => 'Z'); + -- INTERNAL_DATA <= (others => 'Z'); WRH <= 'Z'; WRL <= 'Z'; --in for virtex to read dsp(it's out =0 if I --write into dsp) @@ -92,7 +96,8 @@ begin -- behavioural VALID_DATA_SENT <= '0'; RD_OUT <= 'Z'; debug_register <= "000"; - BRST <= '1'; --write in main entity TLD !!!! + BRST <= 'Z'; +-- BRST <= '1'; --write in main entity TLD !!!! next_read_dsp_data <= reg_read_dsp_data; next_address_dsp <= reg_address_dsp; @@ -110,7 +115,7 @@ begin -- behavioural elsif TRIGGER = '1' and R_W_ENABLE = '0'then --write into the dsp bus next_state <= WRITE_DSP_WAIT_FOR_HBR; next_address_dsp <= INTERNAL_ADDRESS; - next_write_dsp_data <= INTERNAL_DATA; + next_write_dsp_data <= INTERNAL_DATA_IN; else next_state <= IDLE; end if; @@ -127,11 +132,24 @@ begin -- behavioural when READ_DSP_MEMORY_NEXT => debug_register <= "010"; ADDRESS_DSP <= reg_address_dsp; - DSP_DATA <= (others => 'Z'); + DSP_DATA_OUT <= (others => x"a5a5a5a5"); RD_OUT <= '0'; - --WRL <= '1'; WRL <= '1'; + WRH <= '1'; HBR_OUT <= '0'; + BRST <= '1'; + -- next_state <= READ_DSP_WAIT1; + next_state <= READ_DSP_DUMMY; + + when READ_DSP_DUMMY => + debug_register <= "010"; + ADDRESS_DSP <= reg_address_dsp; + DSP_DATA_OUT <= (others => 'Z'); + RD_OUT <= '0'; + WRL <= '1'; + WRH <= '1'; + HBR_OUT <= '0'; + BRST <= '1'; next_state <= READ_DSP_WAIT1; when READ_DSP_WAIT1 => @@ -139,44 +157,56 @@ begin -- behavioural next_state <= READ_DSP_WAIT2; RD_OUT <= '1'; WRL <= '1'; - WRL <= '1'; + WRH <= '1'; HBR_OUT <= '0'; + BRST <= '1'; when READ_DSP_WAIT2 => debug_register <= "100"; - next_state <= READ_DSP_WAIT3; + next_state <= READ_DSP_WAIT3; RD_OUT <= '1'; WRL <= '1'; - WRL <= '1'; + WRH <= '1'; HBR_OUT <= '0'; - + BRST <= '1'; when READ_DSP_WAIT3 => debug_register <= "101"; - next_state <= READ_DSP_MEMORY; + next_state <= READ_DSP_WAIT4; RD_OUT <= '1'; WRL <= '1'; - WRL <= '1'; + WRH <= '1'; HBR_OUT <= '0'; + BRST <= '1'; + when READ_DSP_WAIT4 => + debug_register <= "101"; + next_state <= READ_DSP_MEMORY; + RD_OUT <= '1'; + WRL <= '1'; + WRH <= '1'; + HBR_OUT <= '0'; + BRST <= '1'; + when READ_DSP_MEMORY => debug_register <= "110"; RD_OUT <= '1'; WRL <= '1'; - WRL <= '1'; + WRH <= '1'; HBR_OUT <= '0'; + BRST <= '1'; if ACK = '0' then next_state <= READ_DSP_MEMORY; else next_state <= SENT_DATA_TO_INTERNAL_ENTITY; - next_read_dsp_data <= DSP_DATA; + next_read_dsp_data <= DSP_DATA_IN; end if; when SENT_DATA_TO_INTERNAL_ENTITY => debug_register <= "111"; VALID_DATA_SENT <= '1'; - INTERNAL_DATA <= reg_read_dsp_data; + INTERNAL_DATA_OUT <= reg_read_dsp_data; next_state <= IDLE; ----------------------------------------------------------------------- @@ -198,24 +228,28 @@ begin -- behavioural WRL <= '1'; WRH <= '1'; RD_OUT <= '1'; + BRST <= '1'; next_state <= WRITE_DSP_MEMORY_NEXT; when WRITE_DSP_MEMORY_NEXT => debug_register <= "010"; + DSP_DATA_OUT <= x"5a5a5a5a"; ADDRESS_DSP <= reg_address_dsp; WRL <= '0'; WRH <= '1'; HBR_OUT <= '0'; RD_OUT <= '1'; + BRST <= '1'; next_state <= WRITE_DSP_MEMORY; when WRITE_DSP_MEMORY => debug_register <= "011"; - DSP_DATA <= reg_write_dsp_data; + DSP_DATA_OUT <= reg_write_dsp_data; WRL <= '1'; WRH <= '1'; HBR_OUT <= '0'; RD_OUT <= '1'; + BRST <= '1'; if ACK = '1' then next_state <= WAIT_ACKNOWLEDGMENT; diff --git a/etrax_interface.vhd b/etrax_interface.vhd index 0be7dfe..0a1b35f 100755 --- a/etrax_interface.vhd +++ b/etrax_interface.vhd @@ -29,7 +29,8 @@ entity etrax_interface is TDC_TDO : in std_logic; TDC_RESET : out std_logic; EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA : inout std_logic_vector(31 downto 0); + EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); EXTERNAL_ACK : out std_logic; EXTERNAL_VALID : in std_logic; EXTERNAL_MODE : out std_logic_vector(15 downto 0); @@ -345,7 +346,7 @@ begin elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0); elsif ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA and rw_operation_finished_pulse = '1' then - saved_external_data <= EXTERNAL_DATA; + saved_external_data <= EXTERNAL_DATA_IN; elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0); elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then @@ -359,16 +360,17 @@ begin end process REGISTER_ETRAX_BUS; EXTERNAL_ADDRESS <= saved_address; EXTERNAL_MODE <= saved_rw_mode(15 downto 0); + EXTERNAL_DATA_OUT <= saved_data; EXTERNAL_DATA_LOGIC: process (CLK, RESET) begin if rising_edge(CLK) then if RESET = '1' then - EXTERNAL_DATA <= (others => 'Z'); +-- EXTERNAL_DATA <= (others => 'Z'); elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '1' then - EXTERNAL_DATA <= (others => 'Z'); +-- EXTERNAL_DATA <= (others => 'Z'); EXTERNAL_ACK <= '1'; elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '0' then - EXTERNAL_DATA <= saved_data; +-- EXTERNAL_DATA <= saved_data; EXTERNAL_ACK <= '1'; -- elsif ETRAX_RW_STATE_currentstate = SAVING_EXTERNAL_DATA then --or -- (ETRAX_RW_STATE_currentstate = SEND_VALID and etrax_trigger_pulse ='1')then @@ -376,7 +378,7 @@ begin -- EXTERNAL_DATA <= (others => 'Z'); else EXTERNAL_ACK <= '0'; - EXTERNAL_DATA <= (others => 'Z'); +-- EXTERNAL_DATA <= (others => 'Z'); end if; end if; end process EXTERNAL_DATA_LOGIC; diff --git a/impact_batch_a.txt b/impact_batch_a.txt index 36d9261..030ff79 100644 --- a/impact_batch_a.txt +++ b/impact_batch_a.txt @@ -1,6 +1,6 @@ setMode -bs setMode -bs -setCable -port stapl -file "/home/marek/rpc_trb_v2_fpga/trbv2_fpga.stapl" -addDevice -p 1 -file "/home/marek/rpc_trb_v2_fpga/workdir/rpc_trb_v2_fpga.bit" +setCable -port stapl -file "../trb_v2a_fpga.stapl" +addDevice -p 1 -file "trb_v2a_fpga.bit" Program -p 1 -defaultVersion 0 quit \ No newline at end of file diff --git a/trb_v2a_fpga.ucf b/trb_v2a_fpga.ucf index fcf73f6..2236289 100644 --- a/trb_v2a_fpga.ucf +++ b/trb_v2a_fpga.ucf @@ -170,74 +170,74 @@ NET DBAD LOC = "M28" | IOSTANDARD = "LVTTL"; NET DGOOD LOC = "H34" | IOSTANDARD = "LVTTL"; NET DINT LOC = "L31" | IOSTANDARD = "LVTTL"; -# NET DSPADDR<0> LOC = "AA23"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<1> LOC = "AA24"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<2> LOC = "AJ34"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<3> LOC = "AH34"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<4> LOC = "AD27"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<5> LOC = "AC27"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<6> LOC = "AB25"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<7> LOC = "AB26"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<8> LOC = "AG30"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<9> LOC = "AG31"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<10> LOC = "AH32"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<11> LOC = "AH33"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<12> LOC = "AC25"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<13> LOC = "AD26"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<14> LOC = "AF29"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<15> LOC = "AF30"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<16> LOC = "AA28"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<17> LOC = "AA29"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<18> LOC = "W24"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<19> LOC = "Y24"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<20> LOC = "AB30"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<21> LOC = "AA30"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<22> LOC = "W25"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<23> LOC = "Y26"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<24> LOC = "AE33"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<25> LOC = "AE34"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<26> LOC = "AC32"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<27> LOC = "AC33"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<28> LOC = "AC29"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<29> LOC = "AC30"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<30> LOC = "AD34"| IOSTANDARD = "LVTTL"; -# NET DSPADDR<31> LOC = "AC34"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<0> LOC = "AA25"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<1> LOC = "AA26"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<2> LOC = "AE32"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<3> LOC = "AD32"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<4> LOC = "AC28"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<5> LOC = "AB28"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<6> LOC = "AD30"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<7> LOC = "AD31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<8> LOC = "AG32"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<9> LOC = "AG33"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<10> LOC = "AF33"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<11> LOC = "AF34"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<12> LOC = "AE29"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<13> LOC = "AD29"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<14> LOC = "AF31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<15> LOC = "AE31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<16> LOC = "AK31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<17> LOC = "AK32"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<18> LOC = "AK33"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<19> LOC = "AK34"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<20> LOC = "AM32"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<21> LOC = "AM33"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<22> LOC = "AJ31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<23> LOC = "AJ32"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<24> LOC = "AB22"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<25> LOC = "AB23"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<26> LOC = "AL33"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<27> LOC = "AL34"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<28> LOC = "AM31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<29> LOC = "AL31"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<30> LOC = "AJ30"| IOSTANDARD = "LVTTL"; -# NET DSPDAT<31> LOC = "AH30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<0> LOC = "AA23"| IOSTANDARD = "LVTTL"; + NET DSPADDR<1> LOC = "AA24"| IOSTANDARD = "LVTTL"; + NET DSPADDR<2> LOC = "AJ34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<3> LOC = "AH34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<4> LOC = "AD27"| IOSTANDARD = "LVTTL"; + NET DSPADDR<5> LOC = "AC27"| IOSTANDARD = "LVTTL"; + NET DSPADDR<6> LOC = "AB25"| IOSTANDARD = "LVTTL"; + NET DSPADDR<7> LOC = "AB26"| IOSTANDARD = "LVTTL"; + NET DSPADDR<8> LOC = "AG30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<9> LOC = "AG31"| IOSTANDARD = "LVTTL"; + NET DSPADDR<10> LOC = "AH32"| IOSTANDARD = "LVTTL"; + NET DSPADDR<11> LOC = "AH33"| IOSTANDARD = "LVTTL"; + NET DSPADDR<12> LOC = "AC25"| IOSTANDARD = "LVTTL"; + NET DSPADDR<13> LOC = "AD26"| IOSTANDARD = "LVTTL"; + NET DSPADDR<14> LOC = "AF29"| IOSTANDARD = "LVTTL"; + NET DSPADDR<15> LOC = "AF30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<16> LOC = "AA28"| IOSTANDARD = "LVTTL"; + NET DSPADDR<17> LOC = "AA29"| IOSTANDARD = "LVTTL"; + NET DSPADDR<18> LOC = "W24"| IOSTANDARD = "LVTTL"; + NET DSPADDR<19> LOC = "Y24"| IOSTANDARD = "LVTTL"; + NET DSPADDR<20> LOC = "AB30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<21> LOC = "AA30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<22> LOC = "W25"| IOSTANDARD = "LVTTL"; + NET DSPADDR<23> LOC = "Y26"| IOSTANDARD = "LVTTL"; + NET DSPADDR<24> LOC = "AE33"| IOSTANDARD = "LVTTL"; + NET DSPADDR<25> LOC = "AE34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<26> LOC = "AC32"| IOSTANDARD = "LVTTL"; + NET DSPADDR<27> LOC = "AC33"| IOSTANDARD = "LVTTL"; + NET DSPADDR<28> LOC = "AC29"| IOSTANDARD = "LVTTL"; + NET DSPADDR<29> LOC = "AC30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<30> LOC = "AD34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<31> LOC = "AC34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<0> LOC = "AA25"| IOSTANDARD = "LVTTL"; + NET DSPDAT<1> LOC = "AA26"| IOSTANDARD = "LVTTL"; + NET DSPDAT<2> LOC = "AE32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<3> LOC = "AD32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<4> LOC = "AC28"| IOSTANDARD = "LVTTL"; + NET DSPDAT<5> LOC = "AB28"| IOSTANDARD = "LVTTL"; + NET DSPDAT<6> LOC = "AD30"| IOSTANDARD = "LVTTL"; + NET DSPDAT<7> LOC = "AD31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<8> LOC = "AG32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<9> LOC = "AG33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<10> LOC = "AF33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<11> LOC = "AF34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<12> LOC = "AE29"| IOSTANDARD = "LVTTL"; + NET DSPDAT<13> LOC = "AD29"| IOSTANDARD = "LVTTL"; + NET DSPDAT<14> LOC = "AF31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<15> LOC = "AE31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<16> LOC = "AK31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<17> LOC = "AK32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<18> LOC = "AK33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<19> LOC = "AK34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<20> LOC = "AM32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<21> LOC = "AM33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<22> LOC = "AJ31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<23> LOC = "AJ32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<24> LOC = "AB22"| IOSTANDARD = "LVTTL"; + NET DSPDAT<25> LOC = "AB23"| IOSTANDARD = "LVTTL"; + NET DSPDAT<26> LOC = "AL33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<27> LOC = "AL34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<28> LOC = "AM31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<29> LOC = "AL31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<30> LOC = "AJ30"| IOSTANDARD = "LVTTL"; + NET DSPDAT<31> LOC = "AH30"| IOSTANDARD = "LVTTL"; NET DSP_ACK LOC = "AB15" | IOSTANDARD = "LVTTL"; NET DSP_BM LOC = "AL16" | IOSTANDARD = "LVTTL"; # NET DSP_BMS LOC = AF15; - # NET DSP_BOFF LOC = AK14; + NET DSP_BOFF LOC = "AK14" | IOSTANDARD = "LVTTL"; NET DSP_BRST LOC = "AN20" | IOSTANDARD = "LVTTL"; # NET DSP_BUSLOCK LOC = AC19; # NET DSP_DMAR<0> LOC = AD17; diff --git a/trb_v2a_fpga.vhd b/trb_v2a_fpga.vhd index d7b6571..c22ade6 100644 --- a/trb_v2a_fpga.vhd +++ b/trb_v2a_fpga.vhd @@ -13,7 +13,7 @@ use IEEE.NUMERIC_STD.all; -- library UNISIM; -- use UNISIM.VComponents.all; -entity rpc_trb_v2_fpga is +entity trb_v2a_fpga is port ( ------------------------------------------------------------------------- -- GENERAL @@ -138,7 +138,7 @@ entity rpc_trb_v2_fpga is DSP_ACK : in std_logic; DSP_BM : in std_logic; -- DSP_BMS LOC = AF15; - -- DSP_BOFF LOC = AK14; + DSP_BOFF : out std_logic; -- LOC = AK14; DSP_BRST : inout std_logic; -- DSP_BUSLOCK LOC = AC19; -- DSP_DMAR : std_logic_vector (3 downto 0); @@ -174,12 +174,12 @@ entity rpc_trb_v2_fpga is -- DSP_L1DATON : std_logic_vector (3 downto 0); -- DSP_L0CLKOUTP LOC = AL24; -- DSP_MSH LOC = AL14; - DSP_RD : inout std_logic; + DSP_RD : out std_logic; DSP_RESET : out std_logic; -- DSP_RESET_OUT LOC = AH22; -- DSP_TMROE LOC = AP20; - DSP_WRH :inout std_logic; - DSP_WRL :inout std_logic; + DSP_WRH : out std_logic; + DSP_WRL : out std_logic; ------------------------------------------------------------------------- -- SDRAM ------------------------------------------------------------------------- @@ -235,8 +235,8 @@ entity rpc_trb_v2_fpga is VIRT_TMS : out std_logic; VIRT_TRST : out std_logic ); - end rpc_trb_v2_fpga; -architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is + end trb_v2a_fpga; +architecture trb_v2a_fpga of trb_v2a_fpga is component tdc_interface port ( CLK : in std_logic; @@ -331,7 +331,8 @@ architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is TDC_TDO : in std_logic; TDC_RESET : out std_logic; EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); - EXTERNAL_DATA : inout std_logic_vector(31 downto 0); + EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); EXTERNAL_ACK : out std_logic; EXTERNAL_VALID : in std_logic; EXTERNAL_MODE : out std_logic_vector(15 downto 0); @@ -395,10 +396,11 @@ architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is HBR_OUT : out std_logic; -- Host Bus Request to DSP HBG_IN : in std_logic; -- Host Bus Grant from DSP RD_OUT : out std_logic; -- read/write enable of DSP - DSP_DATA : inout std_logic_vector(31 downto 0); + DSP_DATA_OUT : out std_logic_vector(31 downto 0); + DSP_DATA_IN : in std_logic_vector(31 downto 0); ADDRESS_DSP : out std_logic_vector(31 downto 0); - WRL : inout std_logic; --when dsp slave is output - WRH : inout std_logic; --when dsp slave is output + WRL : out std_logic; --when dsp slave is output + WRH : out std_logic; --when dsp slave is output BM_IN : in std_logic; --Bus Master. For debug DSP_RESET : out std_logic; BRST : inout std_logic; @@ -408,7 +410,8 @@ architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is RESET : in std_logic; R_W_ENABLE : in std_logic; TRIGGER : in std_logic; - INTERNAL_DATA : inout std_logic_vector(31 downto 0); --63 downto 0 + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); --63 downto 0 + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); --63 downto 0 INTERNAL_ADDRESS : in std_logic_vector(31 downto 0); VALID_DATA_SENT : out std_logic; ACKNOWLEDGE : in std_logic; @@ -465,7 +468,8 @@ architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is signal fpga_register_18_i : std_logic_vector(31 downto 0); signal dsp_register_00_i : std_logic_vector(31 downto 0); signal external_address_i : std_logic_vector(31 downto 0); - signal external_data_i : std_logic_vector(31 downto 0); + signal external_data_in_i : std_logic_vector(31 downto 0); + signal external_data_out_i : std_logic_vector(31 downto 0); signal external_ack_i : std_logic; signal external_valid_i : std_logic; signal external_mode_i : std_logic_vector(15 downto 0); @@ -478,11 +482,15 @@ architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is signal dsp_hbr_i : std_logic; signal external_reset_i : std_logic; - signal dspdat_i : std_logic_vector(31 downto 0); + signal dspdat_out_i : std_logic_vector(31 downto 0); + signal dspdat_in_i : std_logic_vector(31 downto 0); signal dspaddr_i : std_logic_vector(31 downto 0); signal internal_clock : std_logic; signal internal_clock_not : std_logic; signal external_debug_i : std_logic; + signal DSP_WRL_i: std_logic; + signal DSP_RD_i: std_logic; + begin ----------------------------------------------------------------------------- -- LVDS signals @@ -491,15 +499,15 @@ begin generic map ( IOSTANDARD => "LVDS_25_DCI") port map ( - O => internal_clock,--CLK, + O => CLK,--CLK, I => VIRT_CLK, IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port) ); - BUFG_CLK : BUFG - port map( - I => internal_clock, - O => CLK - ); +-- BUFG_CLK : BUFG +-- port map( +-- I => internal_clock, +-- O => CLK +-- ); -- CLK <= tlk_clk_r; @@ -655,7 +663,8 @@ begin TDC_TDO => VIRT_TDO, TDC_RESET => TDC_RESET, EXTERNAL_ADDRESS => external_address_i, - EXTERNAL_DATA => external_data_i, + EXTERNAL_DATA_OUT => external_data_out_i, + EXTERNAL_DATA_IN => external_data_in_i, EXTERNAL_ACK => external_ack_i, EXTERNAL_VALID => external_valid_i, EXTERNAL_MODE => external_mode_i, @@ -735,10 +744,11 @@ begin port map ( HBR_OUT => dsp_hbr_i, HBG_IN => DSP_HBG, - RD_OUT => DSP_RD, - DSP_DATA => dspdat_i,--DSPDAT, + RD_OUT => DSP_RD_i, + DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP, + DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA, ADDRESS_DSP => dspaddr_i,--DSPADDR, - WRL => DSP_WRL, + WRL => DSP_WRL_i, WRH => DSP_WRH, BM_IN => DSP_BM, DSP_RESET => open, @@ -748,7 +758,8 @@ begin RESET => external_reset_i, R_W_ENABLE => external_mode_i(15), TRIGGER => dsp_strobe_i, - INTERNAL_DATA => external_data_i, + INTERNAL_DATA_IN => external_data_out_i, + INTERNAL_DATA_OUT => external_data_in_i, INTERNAL_ADDRESS => external_address_i, VALID_DATA_SENT => dsp_external_valid_i, ACKNOWLEDGE => dsp_strobe_i, @@ -763,13 +774,17 @@ begin DSP_RESET <= fpga_register_19_i(1); DSP_HBR <= dsp_hbr_i; - DSPDAT <= dspdat_i; + DSPDAT <= dspdat_out_i; + dspdat_in_i <= DSPDAT; + DSP_WRL <= DSP_WRL_i; + DSP_RD <= DSP_RD_i; -- DSP_HBR <= '1'; fpga_register_07_i <= x"000000" &"0"& DSP_ACK & dsp_register_00_i(2 downto 0)& DSP_HBG & dsp_hbr_i&dsp_strobe_i; - --ADO_TTL <= dspdat_i(15 downto 0) & DSPADDR(15 downto 0) & --CLK & fpga_register_07_i(6 downto 0); DSPADDR <= dspaddr_i; - ADO_TTL <= "000" & x"0000000" & external_debug_i& dspdat_i(2 downto 0) & dspaddr_i(3 downto 0) - & CLK & fpga_register_07_i(6 downto 0); -end rpc_trb_v2_fpga; + DSP_BOFF <= '1'; + ADO_TTL <= "000" & x"0000000" & DSP_WRL_i & DSP_RD_i & "0" & + dspdat_in_i(4 downto 0) & dspdat_out_i(4 downto 0) + & CLK & fpga_register_07_i(2 downto 1); +end trb_v2a_fpga; diff --git a/trb_v2a_fpga_syn.prj b/trb_v2a_fpga_syn.prj index ed66729..767011e 100644 --- a/trb_v2a_fpga_syn.prj +++ b/trb_v2a_fpga_syn.prj @@ -4,7 +4,7 @@ #add_file options add_file -vhdl -lib work "etrax_interface.vhd" -add_file -vhdl -lib work "lvl1_fifo.vhd" +#add_file -vhdl -lib work "lvl1_fifo.vhd" add_file -vhdl -lib work "trigger_logic.vhd" add_file -vhdl -lib work "up_down_counter.vhd" add_file -vhdl -lib work "f_divider.vhd" @@ -12,12 +12,12 @@ add_file -vhdl -lib work "up_counter_17bit.vhd" add_file -vhdl -lib work "lvl1_and_lvl2_busy.vhd" add_file -vhdl -lib work "tdc_interface.vhd" #add_file -vhdl -lib work "up_down_counter_16_bit.vhd" -add_file -vhdl -lib work "rpc_trb_v2_fpga.vhd" -add_file -vhdl -lib work "tlk_interface.vhd" -add_file -vhdl -lib work "link_converter.vhd" -add_file -vhdl -lib work "optical_link_test.vhd" -add_file -vhdl -lib work "from_64_bit_to_optical_link.vhd" -add_file -vhdl -lib work "optical_link_to_64_bit.vhd" +add_file -vhdl -lib work "trb_v2a_fpga.vhd" +add_file -vhdl -lib work "trbnet/tlk_interface.vhd" +add_file -vhdl -lib work "trbnet/link_converter.vhd" +add_file -vhdl -lib work "trbnet/optical_link_test.vhd" +add_file -vhdl -lib work "trbnet/from_64_bit_to_optical_link.vhd" +add_file -vhdl -lib work "trbnet/optical_link_to_64_bit.vhd" add_file -vhdl -lib work "up_down_counter_10bit.vhd" add_file -vhdl -lib work "simpleupcounter_10bit.vhd" add_file -vhdl -lib work "simpleupcounter_16bit.vhd" @@ -30,7 +30,7 @@ add_file -vhdl -lib work "dsp_interface.vhd" #add_file -vhdl -lib work "" #add_file -vhdl -lib work "" #add_file -vhdl -lib work "" -add_file -constraint "rpc_trb_v2_fpga_syn.sdc" +add_file -constraint "trb_v2a_fpga_syn.sdc" #implementation: "workdir" @@ -47,7 +47,7 @@ set_option -default_enum_encoding default set_option -symbolic_fsm_compiler 0 set_option -resource_sharing 1 set_option -use_fsm_explorer 0 -set_option -top_module "rpc_trb_v2_fpga" +set_option -top_module "trb_v2a_fpga" #map options set_option -frequency 100.000 @@ -73,7 +73,7 @@ set_option -write_vif 1 set_option -write_apr_constraint 1 #set result format/file last -project -result_file "workdir/rpc_trb_v2_fpga.edf" +project -result_file "workdir/trb_v2a_fpga.edf" # #implementation attributes -- 2.43.0