From 628921819521d1f15cc06d5d00675a392c502b1f Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 4 Feb 2016 15:41:09 +0100 Subject: [PATCH] brought projects up-to-date with last TDC version --- ADA_Addon/config.vhd | 6 ++-- ADA_Addon/tdc_release | 2 +- base/cbmtof.lpf | 18 +++++----- cbmtof/tdc_release | 2 +- cbmtof/unimportant_lines_constraints.lpf | 7 ++-- cts/tdc_release | 2 +- gpin/tdc_release | 2 +- hadesstart/currentRelease | 1 - hadesstart/tdc_release | 1 + hadesstart/trb3_periph_hadesstart.prj | 44 ++++++++++++------------ 10 files changed, 44 insertions(+), 41 deletions(-) delete mode 120000 hadesstart/currentRelease create mode 120000 hadesstart/tdc_release diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd index 07b061a..8787403 100644 --- a/ADA_Addon/config.vhd +++ b/ADA_Addon/config.vhd @@ -11,7 +11,7 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, @@ -25,8 +25,8 @@ package config is constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 --Include SPI on AddOn connector - constant INCLUDE_SPI : integer := c_YES; - constant SPI_FOR_PADI : integer := c_YES; -- YES: PADI SPI NO: Normal SPI + constant INCLUDE_SPI : integer := c_NO; + constant SPI_FOR_PADI : integer := c_NO; -- YES: PADI SPI NO: Normal SPI --Add logic to generate configurable trigger signal from input signals. constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; diff --git a/ADA_Addon/tdc_release b/ADA_Addon/tdc_release index b10de14..6a654d0 120000 --- a/ADA_Addon/tdc_release +++ b/ADA_Addon/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v2.1.2 \ No newline at end of file +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf index 7a5c3d0..637d52d 100644 --- a/base/cbmtof.lpf +++ b/base/cbmtof.lpf @@ -12,18 +12,18 @@ SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_OSC 200 MHz; FREQUENCY PORT CLK_EXT 200 MHz; FREQUENCY NET "clk_200_i" 200.000000 MHz ; -FREQUENCY NET "clk_100_i_c" 100.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; #FREQUENCY PORT CLK_CM_* 125 MHz; -#MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ; -##MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_i_c" 1 X ; +#MULTICYCLE FROM CLKNET "clk_100_osc" TO CLKNET "CLK_OSC_c" 2 X ; +##MULTICYCLE FROM CLKNET "CLK_OSC_c" TO CLKNET "clk_100_osc" 1 X ; -MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_EXT_c" 1 X ; -MULTICYCLE FROM CLKNET "CLK_EXT_c" TO CLKNET "clk_100_i_c" 2 X ; +MULTICYCLE FROM CLKNET "clk_100_osc" TO CLKNET "CLK_EXT_c" 1 X ; +MULTICYCLE FROM CLKNET "CLK_EXT_c" TO CLKNET "clk_100_osc" 2 X ; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "gen_norm_uplink/THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "gen_sync_uplink/THE_MEDIA_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_norm_uplink.THE_MEDIA_UPLINK/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_sync_uplink.THE_MEDIA_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; ################################################################# # Clock I/O @@ -61,7 +61,9 @@ IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; # DAC & SPI ################################################################# LOCATE COMP "OR_IN" SITE "B2"; -IOBUF PORT "OR_IN" IO_TYPE=LVCMOS25 PULLMODE=NONE; +#IOBUF PORT "OR_IN" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "OR_IN" IO_TYPE=LVDS25; + LOCATE COMP "DAC_SCK" SITE "K8"; LOCATE COMP "DAC_CS" SITE "H6"; diff --git a/cbmtof/tdc_release b/cbmtof/tdc_release index df11eae..6a654d0 120000 --- a/cbmtof/tdc_release +++ b/cbmtof/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v2.2 \ No newline at end of file +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/cbmtof/unimportant_lines_constraints.lpf b/cbmtof/unimportant_lines_constraints.lpf index a47fb62..381da18 100644 --- a/cbmtof/unimportant_lines_constraints.lpf +++ b/cbmtof/unimportant_lines_constraints.lpf @@ -1,4 +1,5 @@ -MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x; -MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_osc TO CLKNET clk_100_osc 5x; +MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_EXT_c 2x; diff --git a/cts/tdc_release b/cts/tdc_release index b10de14..6a654d0 120000 --- a/cts/tdc_release +++ b/cts/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v2.1.2 \ No newline at end of file +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/gpin/tdc_release b/gpin/tdc_release index 9d228ca..6a654d0 120000 --- a/gpin/tdc_release +++ b/gpin/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v2.1.4 \ No newline at end of file +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/hadesstart/currentRelease b/hadesstart/currentRelease deleted file mode 120000 index 05f3df6..0000000 --- a/hadesstart/currentRelease +++ /dev/null @@ -1 +0,0 @@ -../tdc_releases/tdc_v1.6.3 \ No newline at end of file diff --git a/hadesstart/tdc_release b/hadesstart/tdc_release new file mode 120000 index 0000000..6a654d0 --- /dev/null +++ b/hadesstart/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/hadesstart/trb3_periph_hadesstart.prj b/hadesstart/trb3_periph_hadesstart.prj index a99e7af..5d765b4 100644 --- a/hadesstart/trb3_periph_hadesstart.prj +++ b/hadesstart/trb3_periph_hadesstart.prj @@ -51,8 +51,8 @@ impl -active "workdir" #add_file options -add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "currentRelease/tdc_version.vhd" +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" @@ -147,24 +147,24 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" ############### #Change path to tdc release also in compile script! ############### -#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd" -add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd" -add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" -add_file -vhdl -lib "work" "currentRelease/Channel.vhd" -add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" -add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" -#add_file -vhdl -lib "work" "currentRelease/FIFO_36x128_OutReg_Counter.vhd" -add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" -add_file -vhdl -lib "work" "currentRelease/Readout.vhd" -#add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd" -add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" -add_file -vhdl -lib "work" "currentRelease/TDC.vhd" -add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" -add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" -add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" -add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" -add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd" +#add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd" +add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd" +add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd" +add_file -vhdl -lib "work" "tdc_release/Channel.vhd" +add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd" +add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd" +#add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd" +add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib "work" "tdc_release/Readout.vhd" +#add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd" +add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib "work" "tdc_release/TDC.vhd" +add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib "work" "tdc_release/up_counter.vhd" +add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_36x64_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_36x32_OutReg.vhd" @@ -173,8 +173,8 @@ add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x32_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x16_OutReg.vhd" -#add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd" -#add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd" +#add_file -vhdl -lib "work" "tdc_release/Reference_Channel_200.vhd" +#add_file -vhdl -lib "work" "tdc_release/Reference_Channel.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" -- 2.43.0