From 6445630be4df18f1689192297ed37657ce98d512 Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Mon, 17 Aug 2020 10:50:41 +0200
Subject: [PATCH] add trb_net_xdna to components so that it is not needed in
 every project

---
 trb_net16_endpoint_hades_full_gbe.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/trb_net16_endpoint_hades_full_gbe.vhd b/trb_net16_endpoint_hades_full_gbe.vhd
index 1bc5223..ac38bc5 100644
--- a/trb_net16_endpoint_hades_full_gbe.vhd
+++ b/trb_net16_endpoint_hades_full_gbe.vhd
@@ -907,7 +907,7 @@ begin
             REGIO_ONEWIRE_MONITOR_OUT <= '0';
             REGIO_ONEWIRE_INOUT       <= '0';
             
-            XilinxDNA : entity work.trb_net_xdna
+            XilinxDNA : trb_net_xdna
               port map(
                 CLK      => CLK,
                 RESET    => RESET,
-- 
2.43.0