From 6577b6070fda1a691a42f3006f76da95d26099ab Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Sun, 30 Dec 2007 23:56:40 +0000 Subject: [PATCH] lots of changes, Jan --- dualdatarate_flipflop.vhd | 1 - trb_net16_api_active.vhd | 70 +- trb_net16_api_base.vhd | 121 ++- trb_net16_api_passive.vhd | 65 +- trb_net16_dummy_fifo.vhd | 27 +- trb_net16_endpoint_0_trg_1_api.vhd | 285 +++---- trb_net16_endpoint_1_trg_0_api.vhd | 57 +- trb_net16_endpoint_1_trg_1_api.vhd | 30 +- trb_net16_endpoint_2_trg_1_api.vhd | 33 +- trb_net16_endpoint_2_trg_2_api.vhd | 33 +- trb_net16_fifo.vhd | 36 +- trb_net16_hub_base.vhd | 788 +++++++++--------- trb_net16_hub_func.vhd | 47 +- trb_net16_hub_logic.vhd | 140 ++-- trb_net16_ibuf.vhd | 66 +- trb_net16_io_multiplexer.vhd | 112 +-- trb_net16_iobuf.vhd | 209 +++-- trb_net16_med_tlk.vhd | 175 ++++ trb_net16_obuf.vhd | 51 +- trb_net16_obuf_nodata.vhd | 17 +- trb_net16_regIO.vhd | 26 +- trb_net16_sbuf.vhd | 27 +- trb_net16_term.vhd | 118 ++- trb_net16_term_buf.vhd | 35 +- trb_net16_term_ibuf.vhd | 37 +- trb_net_dummy_fifo.vhd | 37 +- trb_net_fifo.vhd | 42 +- trb_net_fifo_16bit_bram_dualport.vhd | 23 +- trb_net_med_8bit_fast.vhd | 1 + trb_net_med_8bit_slow.vhd | 492 ++++++----- trb_net_pattern_gen.vhd | 12 +- trb_net_priority_arbiter.vhd | 53 +- trb_net_priority_encoder.vhd | 15 +- trb_net_sbuf.vhd | 11 +- trb_net_std.vhd | 102 ++- xilinx/trb_net16_bram_fifo.vhd | 60 +- .../trb_net_fifo_16bit_bram_dualport_arch.vhd | 158 ++-- 37 files changed, 1990 insertions(+), 1622 deletions(-) create mode 100644 trb_net16_med_tlk.vhd diff --git a/dualdatarate_flipflop.vhd b/dualdatarate_flipflop.vhd index c353874..eb59727 100644 --- a/dualdatarate_flipflop.vhd +++ b/dualdatarate_flipflop.vhd @@ -1,6 +1,5 @@ --instantiates DualDataRate-Output-Flipflops with generic width - library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; diff --git a/trb_net16_api_active.vhd b/trb_net16_api_active.vhd index c803ef6..afb8865 100644 --- a/trb_net16_api_active.vhd +++ b/trb_net16_api_active.vhd @@ -7,17 +7,16 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_api_active is generic ( - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path - -- if set to 0, no buffer is used + FIFO_TO_INT_DEPTH : integer := std_FIFO_DEPTH; -- direction to medium + FIFO_TO_APL_DEPTH : integer := std_FIFO_DEPTH; -- direction to application + SBUF_VERSION : integer := std_SBUF_VERSION; ); port( @@ -27,8 +26,8 @@ entity trb_net16_api_active is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN : in std_logic; -- @@ -39,8 +38,8 @@ entity trb_net16_api_active is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out APL_READ_IN : in std_logic; -- Read data word @@ -55,26 +54,26 @@ entity trb_net16_api_active is -- to the init respectivly the reply path and vice versa in the passive api. -- lets define: the "master" path is the path that I send data on. INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_IN : in std_logic; INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_OUT : out std_logic; INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_IN : in std_logic; INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_OUT : out std_logic; -- Status and control port @@ -87,12 +86,11 @@ architecture trb_net16_api_active_arch of trb_net16_api_active is component trb_net16_api_base is generic ( - API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used + API_TYPE : integer := 1; -- type of api: 0 passive, 1 active + FIFO_TO_INT_DEPTH : integer := FIFO_TO_INT_DEPTH; + FIFO_TO_APL_DEPTH : integer := FIFO_TO_APL_DEPTH; + SBUF_VERSION : integer := std_SBUF_VERSION + ); port( -- Misc CLK : in std_logic; @@ -100,8 +98,8 @@ architecture trb_net16_api_active_arch of trb_net16_api_active is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN : in std_logic; -- @@ -112,8 +110,8 @@ architecture trb_net16_api_active_arch of trb_net16_api_active is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out APL_READ_IN : in std_logic; -- Read data word @@ -128,26 +126,26 @@ architecture trb_net16_api_active_arch of trb_net16_api_active is -- to the init respectivly the reply path and vice versa in the passive api. -- lets define: the "master" path is the path that I send data on. INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN : in std_logic; INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT : out std_logic; INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN : in std_logic; INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; -- Status and control port @@ -163,7 +161,7 @@ begin API_TYPE => 1, FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH + SBUF_VERSION => SBUF_VERSION ) port map ( CLK => CLK, diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 19c17b0..a86c88b 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -3,17 +3,18 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; - entity trb_net16_api_base is generic ( - API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 1; -- direction to application - SBUF_VERSION : integer range 0 to 1 := 0 + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; + USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION ); port( @@ -23,8 +24,8 @@ entity trb_net16_api_base is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN : in std_logic; -- @@ -35,8 +36,8 @@ entity trb_net16_api_base is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out APL_READ_IN : in std_logic; -- Read data word @@ -51,26 +52,26 @@ entity trb_net16_api_base is -- to the init respectivly the reply path and vice versa in the passive api. -- lets define: the "master" path is the path that I send data on. INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN : in std_logic; INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT : out std_logic; INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN : in std_logic; INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; -- Status and control port @@ -84,19 +85,15 @@ end entity; architecture trb_net16_api_base_arch of trb_net16_api_base is component trb_net16_dummy_fifo is - generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2 - ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic; @@ -106,19 +103,17 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is component trb_net16_fifo is generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2; DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) 64Bit packets ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic; @@ -128,8 +123,6 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is component trb_net16_sbuf is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; VERSION : integer := 0 ); port( @@ -141,12 +134,12 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); SYN_READ_IN : in STD_LOGIC; -- Status and control port STAT_BUFFER : out STD_LOGIC @@ -155,6 +148,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is component trb_net16_term is generic ( + USE_APL_PORT : integer range 0 to 1 := 0; SECURE_MODE : integer range 0 to 1 := 0 --if secure_mode is not used, apl must provide error pattern and dtype until --next trigger comes in. In secure mode these must be available when hold_trm goes low @@ -165,12 +159,12 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is RESET : in std_logic; CLK_EN : in std_logic; INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT: out std_logic; -- "mini" APL, just to see the triggers coming in APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr @@ -185,21 +179,21 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is -- signals for the APL to INT fifo: - signal fifo_to_int_data_in : std_logic_vector(15 downto 0); - signal fifo_to_int_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_to_int_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_to_int_write : std_logic; - signal fifo_to_int_data_out : std_logic_vector(15 downto 0); - signal fifo_to_int_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_int_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_to_int_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_to_int_read : std_logic; signal fifo_to_int_full : std_logic; signal fifo_to_int_empty : std_logic; -- signals for the INT to APL: - signal fifo_to_apl_data_in : std_logic_vector(15 downto 0); - signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0); + signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_to_apl_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_to_apl_write : std_logic; - signal fifo_to_apl_data_out : std_logic_vector(15 downto 0); - signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_to_apl_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_to_apl_read : std_logic; signal fifo_to_apl_full : std_logic; signal fifo_to_apl_empty : std_logic; @@ -208,14 +202,14 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal state_bits, state_bits_to_int, state_bits_to_apl : std_logic_vector(2 downto 0); signal slave_running, next_slave_running, get_slave_running, release_slave_running : std_logic; - signal next_INT_MASTER_DATA_OUT: std_logic_vector(15 downto 0); - signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal next_INT_MASTER_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal next_INT_MASTER_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); signal next_INT_MASTER_DATAREADY_OUT: std_logic; signal sbuf_free, sbuf_next_READ: std_logic; signal next_INT_SLAVE_READ_OUT, reg_INT_SLAVE_READ_OUT: std_logic; signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; - signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(15 downto 0); - signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); @@ -227,7 +221,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal current_combined_header, current_registered_trailer, current_combined_trailer, current_data : std_logic_vector(15 downto 0); signal update_registered_trailer: std_logic; - signal master_counter : std_logic_vector(1 downto 0); + signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal out_enable : std_logic_vector(1 downto 0); signal send_trm_wrong_addr, next_send_trm_wrong_addr : std_logic; signal wait_for_answer, next_wait_for_answer : std_logic; @@ -249,7 +243,8 @@ begin genterm: if API_TYPE = 1 generate TrbNetTerm: trb_net16_term generic map( - SECURE_MODE => 0 + USE_APL_PORT => 0, + SECURE_MODE => 0 ) port map( CLK => CLK, @@ -281,8 +276,6 @@ begin CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate FIFO_TO_INT: trb_net16_fifo generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, DEPTH => FIFO_TO_INT_DEPTH) port map ( CLK => CLK, @@ -301,9 +294,6 @@ begin CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate FIFO_TO_INT: trb_net16_dummy_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2) port map ( CLK => CLK, RESET => RESET, @@ -336,8 +326,6 @@ begin CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate FIFO_TO_APL: trb_net16_fifo generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, DEPTH => FIFO_TO_APL_DEPTH) port map ( CLK => CLK, @@ -356,9 +344,6 @@ begin CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate FIFO_TO_APL: trb_net16_dummy_fifo - generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2) port map ( CLK => CLK, RESET => RESET, @@ -392,8 +377,6 @@ begin --------------------------------------- SBUF: trb_net16_sbuf generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, VERSION => SBUF_VERSION) port map ( CLK => CLK, @@ -523,7 +506,7 @@ begin next_state_to_apl <= MY_ADDR; end if; if INT_SLAVE_PACKET_NUM_IN = "10" then - if INT_SLAVE_DATA_IN = APL_MY_ADDRESS_IN or and_all(INT_SLAVE_DATA_IN) = '1' then + if INT_SLAVE_DATA_IN = APL_MY_ADDRESS_IN or INT_SLAVE_DATA_IN = BROADCAST_ADDRESS then get_slave_running <= '1'; next_wait_for_answer <= '1'; next_state_to_apl <= MY_ADDR; diff --git a/trb_net16_api_passive.vhd b/trb_net16_api_passive.vhd index 3c3458c..75d9f5d 100644 --- a/trb_net16_api_passive.vhd +++ b/trb_net16_api_passive.vhd @@ -7,17 +7,15 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; - entity trb_net16_api_passive is generic ( - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets - FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium - FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path - -- if set to 0, no buffer is used + FIFO_TO_INT_DEPTH : integer := std_FIFO_DEPTH; -- direction to medium + FIFO_TO_APL_DEPTH : integer := std_FIFO_DEPTH; -- direction to application + SBUF_VERSION : integer := std_SBUF_VERSION; ); port( @@ -27,8 +25,8 @@ entity trb_net16_api_passive is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN : in std_logic; -- @@ -39,8 +37,8 @@ entity trb_net16_api_passive is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out APL_READ_IN : in std_logic; -- Read data word @@ -55,26 +53,26 @@ entity trb_net16_api_passive is -- to the init respectivly the reply path and vice versa in the passive api. -- lets define: the "master" path is the path that I send data on. INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_IN : in std_logic; INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_OUT : out std_logic; INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_IN : in std_logic; INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_OUT : out std_logic; -- Status and control port @@ -88,11 +86,10 @@ architecture trb_net16_api_passive_arch of trb_net16_api_passive is component trb_net16_api_base is generic ( API_TYPE : integer := 0; -- type of api: 0 passive, 1 active - --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium FIFO_TO_APL_DEPTH : integer := 0; -- direction to application - FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path - -- if set to 0, no buffer is used + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + ); port( -- Misc CLK : in std_logic; @@ -100,8 +97,8 @@ architecture trb_net16_api_passive_arch of trb_net16_api_passive is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN : in std_logic; -- @@ -112,8 +109,8 @@ architecture trb_net16_api_passive_arch of trb_net16_api_passive is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out APL_READ_IN : in std_logic; -- Read data word @@ -128,26 +125,26 @@ architecture trb_net16_api_passive_arch of trb_net16_api_passive is -- to the init respectivly the reply path and vice versa in the passive api. -- lets define: the "master" path is the path that I send data on. INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN : in std_logic; INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT : out std_logic; INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN : in std_logic; INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; -- Status and control port @@ -163,7 +160,7 @@ begin API_TYPE => 0, FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH + SBUF_VERSION => SBUF_VERSION ) port map ( CLK => CLK, diff --git a/trb_net16_dummy_fifo.vhd b/trb_net16_dummy_fifo.vhd index 24c0efc..c917472 100644 --- a/trb_net16_dummy_fifo.vhd +++ b/trb_net16_dummy_fifo.vhd @@ -1,26 +1,23 @@ -- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo library ieee; - use ieee.std_logic_1164.all; USE ieee.std_logic_signed.ALL; USE ieee.std_logic_arith.ALL; +library work; +use work.trb_net_std.all; entity trb_net16_dummy_fifo is - generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2 - ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic; @@ -33,7 +30,7 @@ architecture arch_trb_net16_dummy_fifo of trb_net16_dummy_fifo is component trb_net_dummy_fifo is generic ( - WIDTH : integer := DATA_WIDTH + NUM_WIDTH); + WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH); port ( CLK : in std_logic; RESET : in std_logic; @@ -48,13 +45,13 @@ architecture arch_trb_net16_dummy_fifo of trb_net16_dummy_fifo is ); end component; - signal din, dout : std_logic_vector(DATA_WIDTH + NUM_WIDTH -1 downto 0); + signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH -1 downto 0); begin - din(DATA_WIDTH - 1 downto 0) <= DATA_IN; - din(DATA_WIDTH + NUM_WIDTH -1 downto DATA_WIDTH) <= PACKET_NUM_IN; - DATA_OUT <= dout(DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT <= dout(DATA_WIDTH + NUM_WIDTH - 1 downto DATA_WIDTH); + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); fifo : trb_net_dummy_fifo port map( diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 48f7f1c..53944bc 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -5,27 +5,26 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; + --Entity decalaration for clock generator entity trb_net16_endpoint_0_trg_1_api is generic ( - API_TYPE : integer range 0 to 1 := 0; - INIT_DEPTH : integer range 0 to 6 := 1; - REPLY_DEPTH : integer range 0 to 6 := 1; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 1; - FIFO_TO_APL_DEPTH : integer range 0 to 6 := 1; - SBUF_VERSION : integer range 0 to 1 := 0; - MUX_WIDTH : integer range 1 to 5 := 3; - MUX_SECURE_MODE : integer range 0 to 1 := 0; - IBUF_SECURE_MODE : integer range 0 to 1 := 1; - IOBUF_USE_ACKNOWLEDGE : integer range 0 to 1 := 1; - INIT_CAN_SEND_DATA : integer range 0 to 1 := 1; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := 1; - DAT_CHANNEL : integer range 0 to 3 := 0; --range 0 to 2**(MUX_WIDTH-1) - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2 + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + INIT_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; + REPLY_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; + FIFO_TO_APL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; + SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL; + MUX_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE; + IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE; + OBUF_DATA_COUNT_WIDTH : integer range 0 to 1 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + DAT_CHANNEL : integer range 0 to 3 := c_SLOW_CONTROL_CHANNEL ); port( @@ -36,21 +35,21 @@ entity trb_net16_endpoint_0_trg_1_api is -- Media direction port MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out --by the media (via the TrbNetIOMultiplexer) - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_IN: in std_logic; -- Media is reading MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media -- (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_OUT: out std_logic; -- buffer reads a word from media MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN: in std_logic; -- @@ -61,8 +60,8 @@ entity trb_net16_endpoint_0_trg_1_api is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out APL_READ_IN: in std_logic; -- Read data word @@ -94,13 +93,15 @@ architecture trb_net16_endpoint_0_trg_1_api_arch of trb_net16_endpoint_0_trg_1_a component trb_net16_iobuf is generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1; - IBUF_SECURE_MODE : integer range 0 to 1 := 1; - --use sbuf in med_to_api direction? - USE_ACKNOWLEDGE : integer range 0 to 1 := 0; - INIT_CAN_SEND_DATA : integer range 0 to 1 := 0; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := 1 + INIT_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH; + REPLY_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_REPLY_CHANNEL : integer range 0 to 1 := c_YES; -- not used yet + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES ); port( -- Misc @@ -110,52 +111,52 @@ component trb_net16_iobuf is -- Media direction port MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; -- Media is reading MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; -- Media is reading MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits -- Internal direction port INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_IN: in std_logic; INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_OUT: out std_logic; INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_IN: in std_logic; INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_OUT: out std_logic; -- Status and control port @@ -172,12 +173,12 @@ end component; component trb_net16_api_base is generic ( - API_TYPE : integer := 1; - FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), - -- for the direction to - -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application - SBUF_VERSION : integer range 0 to 1 := 0 + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; + USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION ); port( @@ -187,8 +188,8 @@ component trb_net16_api_base is CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN: in std_logic; -- @@ -199,8 +200,8 @@ component trb_net16_api_base is -- the target (only for active APIs) -- Receiver port - APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out APL_READ_IN: in std_logic; -- Read data word @@ -214,26 +215,26 @@ component trb_net16_api_base is -- This is just a clone from trb_net_iobuf INT_MASTER_DATAREADY_OUT: out std_logic; - INT_MASTER_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN: in std_logic; INT_MASTER_DATAREADY_IN: in std_logic; - INT_MASTER_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT: out std_logic; INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the SLAVE path) INT_SLAVE_DATAREADY_OUT: out std_logic; - INT_SLAVE_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN: in std_logic; INT_SLAVE_DATAREADY_IN: in std_logic; - INT_SLAVE_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT: out std_logic; -- Status and control port @@ -247,9 +248,6 @@ end component; component trb_net16_io_multiplexer is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? ); port( @@ -259,26 +257,26 @@ component trb_net16_io_multiplexer is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- highest bits are mult. - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_OUT: out std_logic; MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_IN: in std_logic; -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + + INT_DATAREADY_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); -- Status and control port CTRL: in std_logic_vector (31 downto 0); @@ -292,74 +290,74 @@ end component; RESET : in std_logic; CLK_EN : in std_logic; MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_OUT: out std_logic; MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_OUT: out std_logic ); end component; signal apl_to_buf_INIT_DATAREADY: std_logic; -signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0); -signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0); +signal apl_to_buf_INIT_DATA : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (c_NUM_WIDTH-1 downto 0); signal apl_to_buf_INIT_READ : std_logic; signal buf_to_apl_INIT_DATAREADY: std_logic; -signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0); -signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0); +signal buf_to_apl_INIT_DATA : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (c_NUM_WIDTH-1 downto 0); signal buf_to_apl_INIT_READ : std_logic; signal apl_to_buf_REPLY_DATAREADY: std_logic; -signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0); -signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); +signal apl_to_buf_REPLY_DATA : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (c_NUM_WIDTH-1 downto 0); signal apl_to_buf_REPLY_READ : std_logic; signal buf_to_apl_REPLY_DATAREADY: std_logic; -signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0); -signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0); +signal buf_to_apl_REPLY_DATA : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (c_NUM_WIDTH-1 downto 0); signal buf_to_apl_REPLY_READ : std_logic; -- for the connection to the multiplexer signal MED_INIT_DATAREADY_OUT : std_logic; -signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0); -signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0); +signal MED_INIT_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal MED_INIT_READ_IN : std_logic; signal MED_INIT_DATAREADY_IN : std_logic; -signal MED_INIT_DATA_IN : std_logic_vector (15 downto 0); -signal MED_INIT_PACKET_NUM_IN : std_logic_vector (1 downto 0); +signal MED_INIT_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_INIT_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal MED_INIT_READ_OUT : std_logic; signal MED_REPLY_DATAREADY_OUT : std_logic; -signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0); -signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0); +signal MED_REPLY_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal MED_REPLY_READ_IN : std_logic; signal MED_REPLY_DATAREADY_IN : std_logic; -signal MED_REPLY_DATA_IN : std_logic_vector (15 downto 0); -signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (1 downto 0); +signal MED_REPLY_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_REPLY_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal MED_REPLY_READ_OUT : std_logic; -signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); +signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); +signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); -signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0); -signal m_DATA_IN : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0); -signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0); +signal m_DATAREADY_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); +signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0); +signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0); +signal m_READ_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0); signal buf_STAT_INIT_BUFFER : std_logic_vector (31 downto 0); signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 downto 0); @@ -367,22 +365,22 @@ signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (31 begin --Connections for data channel - genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate + genmuxcon : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate gendat: if i = DAT_CHANNEL generate m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT; m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT; - m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_INIT_DATA_OUT; - m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_REPLY_DATA_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; - m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; + m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2) <= MED_INIT_DATA_OUT; + m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH) <= MED_REPLY_DATA_OUT; + m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT; + m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT; MED_INIT_READ_IN <= m_READ_IN(i*2); MED_REPLY_READ_IN <= m_READ_IN(i*2+1); MED_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2); MED_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1); - MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2); - MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH); - MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2); - MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2); + MED_INIT_DATA_IN <= m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2); + MED_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH); + MED_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2); + MED_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2); m_READ_OUT(i*2) <= MED_INIT_READ_OUT; m_READ_OUT(i*2+1) <= MED_REPLY_READ_OUT; end generate; @@ -393,21 +391,21 @@ begin RESET => RESET, CLK_EN => CLK_EN, MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2), MED_INIT_READ_IN => m_READ_IN(i*2), MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2), MED_INIT_READ_OUT => m_READ_OUT(i*2), MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2), MED_REPLY_READ_IN => m_READ_IN(i*2+1), MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2), MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) ); end generate; @@ -418,10 +416,12 @@ begin gen_actapi: if API_TYPE = 1 generate DAT_ACTIVE_API: trb_net16_api_base generic map ( - API_TYPE => 1, + API_TYPE => API_TYPE, FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - SBUF_VERSION => SBUF_VERSION + USE_REPLY_CHANNEL => c_USE_REPLY_CHANNEL(DAT_CHANNEL), + FORCE_REPLY => c_FORCE_REPLY(DAT_CHANNEL), + SBUF_VERSION => SBUF_VERSION ) port map ( -- Misc @@ -475,10 +475,12 @@ begin gen_pasapi: if API_TYPE = 0 generate DAT_PASSIVE_API: trb_net16_api_base generic map ( - API_TYPE => 0, + API_TYPE => API_TYPE, FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, - SBUF_VERSION => SBUF_VERSION + USE_REPLY_CHANNEL => c_USE_REPLY_CHANNEL(DAT_CHANNEL), + FORCE_REPLY => c_FORCE_REPLY(DAT_CHANNEL), + SBUF_VERSION => SBUF_VERSION ) port map ( -- Misc @@ -550,10 +552,12 @@ STAT_api_control_signals(29) <= buf_api_stat_fifo_to_apl(14); IOBUF: trb_net16_iobuf generic map ( - INIT_DEPTH => INIT_DEPTH, - REPLY_DEPTH => REPLY_DEPTH, - IBUF_SECURE_MODE => IBUF_SECURE_MODE, - USE_ACKNOWLEDGE => IOBUF_USE_ACKNOWLEDGE, + INIT_DEPTH => INIT_DEPTH, + REPLY_DEPTH => REPLY_DEPTH, + IBUF_SECURE_MODE => IBUF_SECURE_MODE, + SBUF_VERSION => SBUF_VERSION, + USE_ACKNOWLEDGE => c_USE_ACKNOWLEDGE(DAT_CHANNEL), + USE_REPLY_CHANNEL => c_USE_REPLY_CHANNEL(DAT_CHANNEL), INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA, REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA ) @@ -572,7 +576,7 @@ IOBUF: trb_net16_iobuf MED_INIT_DATA_IN => MED_INIT_DATA_IN, MED_INIT_PACKET_NUM_IN => MED_INIT_PACKET_NUM_IN, MED_INIT_READ_OUT => MED_INIT_READ_OUT, - MED_INIT_ERROR_IN => (others => '0'), + MED_INIT_ERROR_IN => MED_ERROR_IN, MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT, @@ -583,7 +587,7 @@ IOBUF: trb_net16_iobuf MED_REPLY_DATA_IN => MED_REPLY_DATA_IN, MED_REPLY_PACKET_NUM_IN => MED_REPLY_PACKET_NUM_IN, MED_REPLY_READ_OUT => MED_REPLY_READ_OUT, - MED_REPLY_ERROR_IN => (others => '0'), + MED_REPLY_ERROR_IN => MED_ERROR_IN, -- Internal direction port @@ -623,9 +627,6 @@ STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER; MPLEX: trb_net16_io_multiplexer generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, MUX_SECURE_MODE => MUX_SECURE_MODE ) port map ( diff --git a/trb_net16_endpoint_1_trg_0_api.vhd b/trb_net16_endpoint_1_trg_0_api.vhd index f0398cb..4c8ada7 100644 --- a/trb_net16_endpoint_1_trg_0_api.vhd +++ b/trb_net16_endpoint_1_trg_0_api.vhd @@ -1,3 +1,30 @@ + +-- NOT UP TO DATE + + + + + + + + + + + + + + + + + + + + + + + + + -- a trigger receiver - as simple as possible LIBRARY IEEE; @@ -5,6 +32,7 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; --Entity decalaration for clock generator @@ -169,10 +197,8 @@ architecture trb_net16_endpoint_1_trg_0_api_arch of trb_net16_endpoint_1_trg_0_a end component; component trb_net16_term is generic ( - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE + USE_APL_PORT : integer range 0 to 1 := 1; + SECURE_MODE : integer range 0 to 1 := TRG_SECURE_MODE --if secure_mode is not used, apl must provide error pattern and dtype until --next trigger comes in. In secure mode these must be available when hold_trm goes low ); @@ -435,29 +461,6 @@ IOBUF: trb_net16_iobuf ); --- TRM_REPLY : trb_net16_term --- port map( --- -- Misc --- CLK => CLK, --- RESET => RESET, --- CLK_EN => CLK_EN, --- INT_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY, --- INT_DATA_OUT => apl_to_buf_INIT_DATA, --- INT_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM, --- INT_READ_IN => apl_to_buf_INIT_READ, --- INT_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY, --- INT_DATA_IN => buf_to_apl_REPLY_DATA, --- INT_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM, --- INT_READ_OUT => buf_to_apl_REPLY_READ, --- -- "mini" APL, just to see the triggers coming in --- APL_DTYPE_OUT => open, --- APL_ERROR_PATTERN_OUT => open, --- APL_SEQNR_OUT => open, --- APL_GOT_TRM => open, --- APL_RELEASE_TRM => '1', --- APL_ERROR_PATTERN_IN => (others => '0') --- -- Status and control port --- ); apl_to_buf_INIT_DATAREADY <= '0'; apl_to_buf_INIT_DATA <= (others => '0'); apl_to_buf_INIT_PACKET_NUM <= (others => '0'); diff --git a/trb_net16_endpoint_1_trg_1_api.vhd b/trb_net16_endpoint_1_trg_1_api.vhd index 1654af0..ef0b22e 100644 --- a/trb_net16_endpoint_1_trg_1_api.vhd +++ b/trb_net16_endpoint_1_trg_1_api.vhd @@ -1,3 +1,29 @@ + +-- NOT UP TO DATE + + + + + + + + + + + + + + + + + + + + + + + + -- this is an trigger receiver combined with a passive api LIBRARY IEEE; @@ -5,6 +31,7 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; --Entity decalaration for clock generator @@ -239,7 +266,8 @@ architecture trb_net16_endpoint_1_trg_1_api_arch of trb_net16_endpoint_1_trg_1_a component trb_net16_term is generic ( - SECURE_MODE : integer range 0 to 1 := 0 + USE_APL_PORT : integer range 0 to 1 := 1; + SECURE_MODE : integer range 0 to 1 := 0 --if secure_mode is not used, apl must provide error pattern and dtype until --next trigger comes in. In secure mode these must be available when hold_trm goes low ); diff --git a/trb_net16_endpoint_2_trg_1_api.vhd b/trb_net16_endpoint_2_trg_1_api.vhd index 6dacb84..f2b5d97 100644 --- a/trb_net16_endpoint_2_trg_1_api.vhd +++ b/trb_net16_endpoint_2_trg_1_api.vhd @@ -1,3 +1,29 @@ + +-- NOT UP TO DATE + + + + + + + + + + + + + + + + + + + + + + + + -- this is an trigger receiver combined with a passive api LIBRARY IEEE; @@ -5,6 +31,7 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; --Entity decalaration for clock generator @@ -262,10 +289,8 @@ architecture trb_net16_endpoint_2_trg_1_api_arch of trb_net16_endpoint_2_trg_1_a component trb_net16_term is generic ( - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - SECURE_MODE : integer range 0 to 1 := 0 + USE_APL_PORT : integer range 0 to 1 := 1; + SECURE_MODE : integer range 0 to 1 := 0 --if secure_mode is not used, apl must provide error pattern and dtype until --next trigger comes in. In secure mode these must be available when hold_trm goes low ); diff --git a/trb_net16_endpoint_2_trg_2_api.vhd b/trb_net16_endpoint_2_trg_2_api.vhd index 196a736..a9b6466 100644 --- a/trb_net16_endpoint_2_trg_2_api.vhd +++ b/trb_net16_endpoint_2_trg_2_api.vhd @@ -1,3 +1,29 @@ + +-- NOT UP TO DATE + + + + + + + + + + + + + + + + + + + + + + + + -- this is an trigger receiver combined with a passive api LIBRARY IEEE; @@ -5,6 +31,7 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; --Entity decalaration for clock generator @@ -280,10 +307,8 @@ architecture trb_net16_endpoint_2_trg_2_api_arch of trb_net16_endpoint_2_trg_2_a component trb_net16_term is generic ( - FIFO_TERM_BUFFER_DEPTH : integer := 0; -- fifo for auto-answering of - -- the master path, if set to 0 - -- no buffer is used at all - SECURE_MODE : integer range 0 to 1 := 0 + USE_APL_PORT : integer range 0 to 1 := 1; + SECURE_MODE : integer range 0 to 1 := 0 --if secure_mode is not used, apl must provide error pattern and dtype until --next trigger comes in. In secure mode these must be available when hold_trm goes low ); diff --git a/trb_net16_fifo.vhd b/trb_net16_fifo.vhd index 5468600..6b411ef 100644 --- a/trb_net16_fifo.vhd +++ b/trb_net16_fifo.vhd @@ -5,28 +5,26 @@ -- The depth is given in 64Bit-packets! library ieee; - use ieee.std_logic_1164.all; USE ieee.std_logic_signed.ALL; USE ieee.std_logic_arith.ALL; - +library work; +use work.trb_net_std.all; entity trb_net16_fifo is generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2; DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic; @@ -38,10 +36,11 @@ end entity; architecture trb_net16_fifo_arch of trb_net16_fifo is component trb_net_fifo is - generic (WIDTH : integer := DATA_WIDTH + NUM_WIDTH; -- FIFO word width - DEPTH : integer := DEPTH + 2; - FORCE_LUT : integer := 0 - ); + generic ( + WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; -- FIFO word width + DEPTH : integer := DEPTH + 2; + FORCE_LUT : integer := 0 + ); port ( CLK : in std_logic; RESET : in std_logic; @@ -56,14 +55,14 @@ architecture trb_net16_fifo_arch of trb_net16_fifo is ); end component; - signal din, dout : std_logic_vector(DATA_WIDTH + NUM_WIDTH-1 downto 0); + signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); signal depth16 : std_logic_vector(7 downto 0); begin - din(DATA_WIDTH - 1 downto 0) <= DATA_IN; - din(DATA_WIDTH + NUM_WIDTH -1 downto DATA_WIDTH) <= PACKET_NUM_IN; - DATA_OUT <= dout(DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT <= dout(DATA_WIDTH + NUM_WIDTH - 1 downto DATA_WIDTH); + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); DEPTH_OUT <= conv_std_logic_vector(DEPTH, 8); fifo : trb_net_fifo @@ -79,7 +78,4 @@ begin EMPTY_OUT => EMPTY_OUT, DEPTH_OUT => depth16 ); - - - end architecture; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 6d78455..b1ade71 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -2,7 +2,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_UNSIGNED.ALL; -LIBRARY work; +library work; use work.trb_net_std.all; use work.trb_net16_hub_func.all; @@ -10,63 +10,29 @@ use work.trb_net16_hub_func.all; entity trb_net16_hub_base is generic ( --general settings - MUX_SECURE_MODE : integer range 0 to 1 := 0; - MUX_WIDTH : integer range 1 to 3 := 1; - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2; + MUX_SECURE_MODE : integer range 0 to 1 := c_NO; --hub control - HUB_ADDRESS : std_logic_vector(15 downto 0) := x"F001"; - HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0; - HUB_CTRL_DEPTH : integer range 0 to 6 := 1; + HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL; + HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4; - IBUF_SECURE_MODE : integer range 0 to 1 := 0; + HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_NO,c_YES,c_YES); + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; --media interfaces - MII_NUMBER : integer range 2 to 16 := 12; ---each row is one media interface and each column is one channel. starting with 0,0, ending with 15,15 - --CHANNEL 3 2 1 0 - MII_INIT_DEPTH : hub_iobuf_config_t := (6,6,6,6, --MII 0 - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6); --MII 15 - MII_REPLY_DEPTH : hub_iobuf_config_t := (6,6,6,6, --MII 0 - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6, - 6,6,6,6); --MII 15 + MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12; + --each row is one media interface and each column is one channel. starting with 0,0, ending with 15,15 + MII_INIT_DEPTH : hub_iobuf_config_t := std_HUB_INIT_DEPTH; + MII_REPLY_DEPTH : hub_iobuf_config_t := std_HUB_REPLY_DEPTH; -- settings for apis - API_NUMBER : integer range 0 to 16 := 0; - API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3); + API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; + API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3); --channel, each api is connected to - API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); - API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1); - API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1); + API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0); + API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1); + API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1); --trigger reading interfaces - TRG_NUMBER : integer range 0 to 16 := 0; - TRG_SECURE_MODE : integer range 0 to 1 := 0; - TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0) + TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0; + TRG_SECURE_MODE : integer range 0 to 1 := c_NO; + TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0) ); port ( CLK : in std_logic; @@ -76,17 +42,17 @@ entity trb_net16_hub_base is --Media interfacces --each port is one bit bigger than actually necessary to avoid error messages MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_OUT : out std_logic_vector (MII_NUMBER*DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*NUM_WIDTH-1 downto 0); + MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); - MED_DATA_IN : in std_logic_vector (MII_NUMBER*DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*NUM_WIDTH-1 downto 0); + MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); -- buffer reads a word from media MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0); --API: interfaces - APL_DATA_IN : in std_logic_vector (VAL(API_NUMBER*DATA_WIDTH) downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (VAL(API_NUMBER*NUM_WIDTH) downto 0); + APL_DATA_IN : in std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0); APL_WRITE_IN : in std_logic_vector (VAL(API_NUMBER) downto 0); APL_FIFO_FULL_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0); APL_SHORT_TRANSFER_IN : in std_logic_vector (VAL(API_NUMBER) downto 0); @@ -94,8 +60,8 @@ entity trb_net16_hub_base is APL_ERROR_PATTERN_IN : in std_logic_vector (VAL(API_NUMBER*32) downto 0); APL_SEND_IN : in std_logic_vector (VAL(API_NUMBER) downto 0); APL_TARGET_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0); - APL_DATA_OUT : out std_logic_vector (VAL(API_NUMBER*16) downto 0); - APL_PACKET_NUM_OUT: out std_logic_vector (VAL(API_NUMBER*NUM_WIDTH) downto 0); + APL_DATA_OUT : out std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0); + APL_PACKET_NUM_OUT: out std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0); APL_TYP_OUT : out std_logic_vector (VAL(API_NUMBER*3) downto 0); APL_DATAREADY_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0); APL_READ_IN : in std_logic_vector (VAL(API_NUMBER) downto 0); @@ -110,70 +76,70 @@ entity trb_net16_hub_base is TRG_ERROR_PATTERN_IN : in std_logic_vector (VAL(TRG_NUMBER*32) downto 0); TRG_RELEASE_IN : in std_logic_vector (VAL(TRG_NUMBER) downto 0); --Status ports (for debugging) - HUB_STAT_CHANNEL : out std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0); - HUB_STAT_GEN : out std_logic_vector (31 downto 0); - MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); - MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0) + HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + HUB_STAT_GEN : out std_logic_vector (31 downto 0); + MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); + MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0) ); end entity; architecture trb_net16_hub_base_arch of trb_net16_hub_base is - constant total_point_num : integer := MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER + 1; - signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)-1 downto 0); - signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)*DATA_WIDTH-1 downto 0); - signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)*NUM_WIDTH-1 downto 0); - signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)-1 downto 0); - signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)-1 downto 0); - signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)*DATA_WIDTH-1 downto 0); - signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)*NUM_WIDTH-1 downto 0); - signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)-1 downto 0); - signal m_ERROR_IN : std_logic_vector (MII_NUMBER*2**(MUX_WIDTH)*3-1 downto 0); + constant total_point_num : integer := MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER + 1; + signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); + signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); + signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); + signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0); + signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0); + signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0); + signal m_ERROR_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*3-1 downto 0); signal hub_to_buf_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0); - signal hub_to_buf_INIT_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal hub_to_buf_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal hub_to_buf_INIT_READ : std_logic_vector (total_point_num-1 downto 0); signal buf_to_hub_INIT_DATAREADY : std_logic_vector (total_point_num-1 downto 0); - signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal buf_to_hub_INIT_PACKET_NUM:std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0); signal hub_to_buf_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0); - signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal hub_to_buf_REPLY_PACKET_NUM :std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal hub_to_buf_REPLY_PACKET_NUM :std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0); signal hub_to_buf_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0); signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0); - signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal buf_to_hub_REPLY_PACKET_NUM :std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal buf_to_hub_REPLY_PACKET_NUM :std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0); signal buf_to_hub_REPLY_SEND_HEADER : std_logic_vector(total_point_num-1 downto 0); signal HUB_INIT_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0); - signal HUB_INIT_DATA_OUT : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal HUB_INIT_PACKET_NUM_OUT : std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal HUB_INIT_DATA_OUT : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal HUB_INIT_PACKET_NUM_OUT : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal HUB_INIT_READ_IN : std_logic_vector (total_point_num-1 downto 0); signal HUB_INIT_DATAREADY_IN : std_logic_vector (total_point_num-1 downto 0); - signal HUB_INIT_DATA_IN : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal HUB_INIT_PACKET_NUM_IN : std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal HUB_INIT_DATA_IN : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal HUB_INIT_PACKET_NUM_IN : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal HUB_INIT_READ_OUT : std_logic_vector (total_point_num-1 downto 0); signal HUB_REPLY_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0); - signal HUB_REPLY_DATA_OUT : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal HUB_REPLY_PACKET_NUM_OUT : std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal HUB_REPLY_DATA_OUT : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal HUB_REPLY_PACKET_NUM_OUT : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal HUB_REPLY_READ_IN : std_logic_vector (total_point_num-1 downto 0); signal HUB_REPLY_DATAREADY_IN : std_logic_vector (total_point_num-1 downto 0); - signal HUB_REPLY_DATA_IN : std_logic_vector (total_point_num*DATA_WIDTH-1 downto 0); - signal HUB_REPLY_PACKET_NUM_IN : std_logic_vector (total_point_num*NUM_WIDTH-1 downto 0); + signal HUB_REPLY_DATA_IN : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0); + signal HUB_REPLY_PACKET_NUM_IN : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0); signal HUB_REPLY_READ_OUT : std_logic_vector (total_point_num-1 downto 0); signal HUB_REPLY_SEND_HEADER_OUT : std_logic_vector (total_point_num-1 downto 0); - signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0); + signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0); - signal HC_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0); - signal HC_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0); + signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); + signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); signal HC_WRITE_IN : std_logic; signal HC_FIFO_FULL_OUT : std_logic; signal HC_SHORT_TRANSFER_IN : std_logic; @@ -181,8 +147,8 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HC_ERROR_PATTERN_IN : std_logic_vector (31 downto 0); signal HC_SEND_IN : std_logic; signal HC_TARGET_ADDRESS_IN : std_logic_vector (15 downto 0); - signal HC_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0); - signal HC_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH-1 downto 0); + signal HC_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); + signal HC_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH-1 downto 0); signal HC_TYP_OUT : std_logic_vector (2 downto 0); signal HC_DATAREADY_OUT : std_logic; signal HC_READ_IN : std_logic; @@ -192,49 +158,47 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HC_STAT_REGS : std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0); signal HC_CTRL_REGS : std_logic_vector (2**(HUB_CTRL_REG_ADDR_WIDTH-1)*32-1 downto 0); - signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0); - signal HUB_CTRL_final_activepoints : std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); - signal HUB_CTRL_CHANNEL : std_logic_vector (2**(MUX_WIDTH-1)*16-1 downto 0); - signal HUB_CTRL_activepoints : std_logic_vector (2**(MUX_WIDTH-1)*32-1 downto 0); - signal HUB_CTRL_GEN : std_logic_vector (31 downto 0); + signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0); + signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); + signal HUB_CTRL_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + signal HUB_CTRL_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0); + signal HUB_CTRL_GEN : std_logic_vector (31 downto 0); + signal HUB_ADDRESS : std_logic_vector (15 downto 0); - signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_STAT_LOCKED : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_STAT_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_STAT_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_CTRL_LOCKED : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_STAT_CTRL_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); - signal IOBUF_STAT_CTRL_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_LOCKED : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_CTRL_LOCKED : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_CTRL_INIT_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_CTRL_REPLY_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); component trb_net16_hub_logic is generic ( --media interfaces - POINT_NUMBER : integer range 2 to 16 := 2; - --general settings - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 + POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2 ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); STAT : out std_logic_vector (15 downto 0); STAT_POINTS_locked : out std_logic_vector (31 downto 0); @@ -247,9 +211,6 @@ end component; component trb_net16_io_multiplexer is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; MUX_SECURE_MODE : integer range 0 to 1 := 0 ); port( @@ -259,22 +220,22 @@ end component; CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0); + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_OUT: out std_logic; MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0); + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_IN: in std_logic; -- Internal direction port - INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH *(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN: in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH *(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); -- Status and control port CTRL: in std_logic_vector (31 downto 0); STAT: out std_logic_vector (31 downto 0) @@ -294,40 +255,40 @@ end component; CLK_EN : in std_logic; -- Media direction port MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; -- Media is reading MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; -- Media is reading MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits -- Internal direction port INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_IN: in std_logic; INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_OUT: out std_logic; INT_REPLY_HEADER_IN: in std_logic; INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_IN: in std_logic; INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_OUT: out std_logic; -- Status and control port STAT_GEN: out std_logic_vector (31 downto 0); -- General Status @@ -347,15 +308,16 @@ end component; API_TYPE : integer := 1; FIFO_TO_INT_DEPTH : integer := 1; FIFO_TO_APL_DEPTH : integer := 1; - SBUF_VERSION : integer := 0); + SBUF_VERSION : integer := 0 + ); port( -- Misc CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network" - APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network" + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full APL_SHORT_TRANSFER_IN : in std_logic; -- @@ -364,8 +326,8 @@ end component; APL_SEND_IN : in std_logic; -- Release sending of the data APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of -- Receiver port - APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application" - APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application" + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out APL_READ_IN : in std_logic; -- Read data word @@ -375,21 +337,21 @@ end component; APL_SEQNR_OUT : out std_logic_vector (7 downto 0); -- Internal direction port INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_IN : in std_logic; INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_MASTER_READ_OUT : out std_logic; INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_IN : in std_logic; INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_SLAVE_READ_OUT : out std_logic; -- Status and control port STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); @@ -409,12 +371,12 @@ end component; RESET : in std_logic; CLK_EN : in std_logic; INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT: out std_logic; -- "mini" APL, just to see the triggers coming in APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr @@ -429,7 +391,6 @@ end component; component trb_net16_regIO is generic ( - MY_ADDRESS : std_logic_vector(15 downto 0) := x"F001"; REGISTER_WIDTH : integer range 32 to 32 := 32; ADDRESS_WIDTH : integer range 8 to 16 := 16; ADDRESS_USED_WIDTH : integer range 1 to 16 := HUB_CTRL_REG_ADDR_WIDTH; @@ -444,9 +405,10 @@ end component; CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; + MY_ADDRESS : in std_logic_vector (15 downto 0); -- Port to API - API_DATA_OUT : out std_logic_vector (15 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); API_WRITE_OUT : out std_logic; API_FIFO_FULL_IN : in std_logic; API_SHORT_TRANSFER_OUT : out std_logic; @@ -455,8 +417,8 @@ end component; API_SEND_OUT : out std_logic; API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); -- Receiver port - API_DATA_IN : in std_logic_vector (15 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); API_TYP_IN : in std_logic_vector (2 downto 0); API_DATAREADY_IN : in std_logic; API_READ_OUT : out std_logic; @@ -477,6 +439,35 @@ end component; ); end component; + component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_INIT_DATAREADY_IN: in std_logic; + MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_OUT: out std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_IN: in std_logic; + MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_OUT: out std_logic + ); + end component; + begin --set unused signals @@ -490,9 +481,6 @@ begin begin MPLEX: trb_net16_io_multiplexer generic map ( - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH, - MUX_WIDTH => MUX_WIDTH, MUX_SECURE_MODE => MUX_SECURE_MODE ) port map ( @@ -500,100 +488,133 @@ begin RESET => RESET, CLK_EN => CLK_EN, MED_DATAREADY_IN => MED_DATAREADY_IN(i), - MED_DATA_IN => MED_DATA_IN((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + MED_DATA_IN => MED_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_OUT => MED_READ_OUT(i), MED_DATAREADY_OUT => MED_DATAREADY_OUT(i), - MED_DATA_OUT => MED_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + MED_DATA_OUT => MED_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_IN => MED_READ_IN(i), - INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), - INT_DATA_OUT => m_DATA_IN((i+1)*DATA_WIDTH*2**MUX_WIDTH-1 downto i*DATA_WIDTH*2**MUX_WIDTH), - INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*NUM_WIDTH*2**MUX_WIDTH-1 downto i*NUM_WIDTH*2**MUX_WIDTH), - INT_READ_IN => m_READ_OUT((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), - INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), - INT_DATA_IN => m_DATA_OUT((i+1)*DATA_WIDTH*2**MUX_WIDTH-1 downto i*DATA_WIDTH*2**MUX_WIDTH), - INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*NUM_WIDTH*2**MUX_WIDTH-1 downto i*NUM_WIDTH*2**MUX_WIDTH), - INT_READ_OUT => m_READ_IN((i+1)*2**MUX_WIDTH-1 downto i*2**MUX_WIDTH), + INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), + INT_DATA_OUT => m_DATA_IN((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH), + INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto i*c_NUM_WIDTH*2**c_MUX_WIDTH), + INT_READ_IN => m_READ_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), + INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), + INT_DATA_IN => m_DATA_OUT((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH), + INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto i*c_NUM_WIDTH*2**c_MUX_WIDTH), + INT_READ_OUT => m_READ_IN((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH), CTRL => MPLEX_CTRL((i+1)*32-1 downto i*32), STAT => MPLEX_STAT((i+1)*32-1 downto i*32) ); end generate; --generate IOBufs for MII - gen_iobufs: for i in 0 to MII_NUMBER*2**(MUX_WIDTH-1)-1 generate - constant t : integer := 0; - begin - IOBUF: trb_net16_iobuf - generic map ( - INIT_DEPTH => calc_depth(i,MII_INIT_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, MUX_WIDTH, HUB_CTRL_DEPTH), - REPLY_DEPTH => calc_depth(i,MII_REPLY_DEPTH, API_FIFO_TO_INT_DEPTH, MII_NUMBER, API_NUMBER, MUX_WIDTH, HUB_CTRL_DEPTH), - IBUF_SECURE_MODE => IBUF_SECURE_MODE - ) - port map ( - -- Misc - CLK => CLK , - RESET => RESET, - CLK_EN => CLK_EN, - -- Media direction port - MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), - MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*2*DATA_WIDTH), - MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*NUM_WIDTH-1 downto i*2*NUM_WIDTH), - MED_INIT_READ_IN => m_READ_IN(i*2), - - MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), - MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*2*DATA_WIDTH), - MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*NUM_WIDTH-1 downto i*2*NUM_WIDTH), - MED_INIT_READ_OUT => m_READ_OUT(i*2), - MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + gen_bufs : for j in 0 to MII_NUMBER-1 generate + gen_iobufs: for k in 0 to 2**(c_MUX_WIDTH-1)-1 generate + constant i : integer := j*2**(c_MUX_WIDTH-1)+k; + begin + gen_iobuf: if HUB_USED_CHANNELS(k) = 1 generate + IOBUF: trb_net16_iobuf + generic map ( + INIT_DEPTH => calc_depth(i,MII_INIT_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH), + REPLY_DEPTH => calc_depth(i,MII_REPLY_DEPTH, API_FIFO_TO_INT_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH), + IBUF_SECURE_MODE => IBUF_SECURE_MODE + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + MED_INIT_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), - MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*NUM_WIDTH-1 downto (i*2+1)*NUM_WIDTH), - MED_REPLY_READ_IN => m_READ_IN(i*2+1), - - MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), - MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH), - MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*NUM_WIDTH-1 downto (i*2+1)*NUM_WIDTH), - MED_REPLY_READ_OUT => m_READ_OUT(i*2+1), - MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), - - -- Internal direction port + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + + MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_OUT => m_READ_OUT(i*2+1), + MED_REPLY_ERROR_IN => m_ERROR_IN((i+1)*3-1 downto i*3), + + -- Internal direction port - INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), + INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_hub_INIT_READ(i), - INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), - - INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i), - INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), + INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i), + + INT_REPLY_HEADER_IN => buf_to_hub_REPLY_SEND_HEADER(i), + INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i), - INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), - INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), - INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), + INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i), - -- Status and control port - STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32), - STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32-1 downto i*32), - STAT_INIT_BUFFER => IOBUF_STAT_INIT_BUFFER((i+1)*32-1 downto i*32), - STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32-1 downto i*32), - CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32), - CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32-1 downto i*32), - STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32), - STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32-1 downto i*32) - ); + -- Status and control port + STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32), + STAT_LOCKED => IOBUF_STAT_LOCKED((i+1)*32-1 downto i*32), + STAT_INIT_BUFFER => IOBUF_STAT_INIT_BUFFER((i+1)*32-1 downto i*32), + STAT_REPLY_BUFFER => IOBUF_STAT_REPLY_BUFFER((i+1)*32-1 downto i*32), + CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32), + CTRL_LOCKED => IOBUF_CTRL_LOCKED((i+1)*32-1 downto i*32), + STAT_CTRL_INIT_BUFFER => IOBUF_STAT_CTRL_INIT_BUFFER((i+1)*32-1 downto i*32), + STAT_CTRL_REPLY_BUFFER => IOBUF_STAT_CTRL_REPLY_BUFFER((i+1)*32-1 downto i*32) + ); + end generate; + gen_trmbuf: if HUB_USED_CHANNELS(k) = 0 generate + IOBUF : trb_net16_term_buf + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => m_READ_IN(i*2), + MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2), + MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_OUT => m_READ_OUT(i*2), + MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => m_READ_IN(i*2+1), + MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1), + MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_OUT => m_READ_OUT(i*2+1) + ); + end generate; + end generate; end generate; - gen_ctrl_api : if 1 = 1 generate - constant i : integer := 2**(MUX_WIDTH-1)*MII_NUMBER; + + + + gen_ctrl_api : if 1 = 1 generate --just a dummy now + constant i : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER; begin CTRL_API : trb_net16_api_base generic map( @@ -607,8 +628,8 @@ begin RESET => RESET, CLK_EN => CLK_EN, -- APL Transmitter port - APL_DATA_IN => HC_DATA_IN(DATA_WIDTH-1 downto 0), - APL_PACKET_NUM_IN => HC_PACKET_NUM_IN(NUM_WIDTH-1 downto 0), + APL_DATA_IN => HC_DATA_IN(c_DATA_WIDTH-1 downto 0), + APL_PACKET_NUM_IN => HC_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0), APL_WRITE_IN => HC_WRITE_IN, APL_FIFO_FULL_OUT => HC_FIFO_FULL_OUT, APL_SHORT_TRANSFER_IN => HC_SHORT_TRANSFER_IN, @@ -617,8 +638,8 @@ begin APL_SEND_IN => HC_SEND_IN, APL_TARGET_ADDRESS_IN => HC_TARGET_ADDRESS_IN(15 downto 0), -- Receiver port - APL_DATA_OUT => HC_DATA_OUT(DATA_WIDTH-1 downto 0), - APL_PACKET_NUM_OUT => HC_PACKET_NUM_OUT(NUM_WIDTH-1 downto 0), + APL_DATA_OUT => HC_DATA_OUT(c_DATA_WIDTH-1 downto 0), + APL_PACKET_NUM_OUT => HC_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0), APL_TYP_OUT => HC_TYP_OUT(2 downto 0), APL_DATAREADY_OUT => HC_DATAREADY_OUT, APL_READ_IN => HC_READ_IN, @@ -628,21 +649,21 @@ begin APL_SEQNR_OUT => HC_SEQNR_OUT(7 downto 0), -- Internal direction port INT_MASTER_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_MASTER_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_MASTER_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_IN => buf_to_hub_REPLY_READ(i), INT_MASTER_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), - INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_OUT => hub_to_buf_REPLY_READ(i), INT_SLAVE_HEADER_IN => hub_to_buf_REPLY_SEND_HEADER(i), INT_SLAVE_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_IN => buf_to_hub_INIT_READ(i), INT_SLAVE_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_SLAVE_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_SLAVE_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_OUT => hub_to_buf_INIT_READ(i), -- Status and control port STAT_FIFO_TO_INT => open, @@ -650,9 +671,9 @@ begin ); end generate; gen_apisa : if API_NUMBER /= 0 generate - gen_apis : for i in 2**(MUX_WIDTH-1)*MII_NUMBER+1 to 2**(MUX_WIDTH-1)*MII_NUMBER+API_NUMBER generate + gen_apis : for i in 2**(c_MUX_WIDTH-1)*MII_NUMBER+1 to 2**(c_MUX_WIDTH-1)*MII_NUMBER+API_NUMBER generate --+1 because of hub_ctrl - constant offset : integer := 2**(MUX_WIDTH-1)*MII_NUMBER + 1; + constant offset : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER + 1; constant aploffset : integer := i - offset; begin gen_pas_api : if API_TYPE(aploffset) = 0 generate @@ -670,8 +691,8 @@ begin RESET => RESET, CLK_EN => CLK_EN, -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN((aploffset+1)*DATA_WIDTH-1 downto aploffset * DATA_WIDTH), - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((aploffset+1)*NUM_WIDTH-1 downto aploffset * NUM_WIDTH), + APL_DATA_IN => APL_DATA_IN((aploffset+1)*c_DATA_WIDTH-1 downto aploffset * c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((aploffset+1)*c_NUM_WIDTH-1 downto aploffset * c_NUM_WIDTH), APL_WRITE_IN => APL_WRITE_IN(aploffset), APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(aploffset), APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(aploffset), @@ -680,8 +701,8 @@ begin APL_SEND_IN => APL_SEND_IN(aploffset), APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((aploffset+1)*16-1 downto aploffset*16), -- Receiver port - APL_DATA_OUT => APL_DATA_OUT((aploffset+1)*DATA_WIDTH-1 downto aploffset * DATA_WIDTH), - APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT((aploffset+1)*NUM_WIDTH-1 downto aploffset * NUM_WIDTH), + APL_DATA_OUT => APL_DATA_OUT((aploffset+1)*c_DATA_WIDTH-1 downto aploffset * c_DATA_WIDTH), + APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT((aploffset+1)*c_NUM_WIDTH-1 downto aploffset * c_NUM_WIDTH), APL_TYP_OUT => APL_TYP_OUT((aploffset+1)*3-1 downto aploffset*3), APL_DATAREADY_OUT => APL_DATAREADY_OUT(aploffset), APL_READ_IN => APL_READ_IN(aploffset), @@ -691,21 +712,21 @@ begin APL_SEQNR_OUT => APL_SEQNR_OUT((aploffset+1)*8-1 downto aploffset*8), -- Internal direction port INT_MASTER_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_MASTER_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_MASTER_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_IN => buf_to_hub_REPLY_READ(i), INT_MASTER_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), - INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_OUT => hub_to_buf_REPLY_READ(i), INT_SLAVE_HEADER_IN => hub_to_buf_REPLY_SEND_HEADER(i), INT_SLAVE_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_IN => buf_to_hub_INIT_READ(i), INT_SLAVE_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_SLAVE_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_SLAVE_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_OUT => hub_to_buf_INIT_READ(i), -- Status and control port STAT_FIFO_TO_INT => open, @@ -727,8 +748,8 @@ begin RESET => RESET, CLK_EN => CLK_EN, -- APL Transmitter port - APL_DATA_IN => APL_DATA_IN((aploffset+1)*DATA_WIDTH-1 downto aploffset * DATA_WIDTH), - APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((aploffset+1)*NUM_WIDTH-1 downto aploffset * NUM_WIDTH), + APL_DATA_IN => APL_DATA_IN((aploffset+1)*c_DATA_WIDTH-1 downto aploffset * c_DATA_WIDTH), + APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((aploffset+1)*c_NUM_WIDTH-1 downto aploffset * c_NUM_WIDTH), APL_WRITE_IN => APL_WRITE_IN(aploffset), APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT(aploffset), APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(aploffset), @@ -737,8 +758,8 @@ begin APL_SEND_IN => APL_SEND_IN(aploffset), APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((aploffset+1)*16-1 downto aploffset*16), -- Receiver port - APL_DATA_OUT => APL_DATA_OUT((aploffset+1)*DATA_WIDTH-1 downto aploffset * DATA_WIDTH), - APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT((aploffset+1)*NUM_WIDTH-1 downto aploffset * NUM_WIDTH), + APL_DATA_OUT => APL_DATA_OUT((aploffset+1)*c_DATA_WIDTH-1 downto aploffset * c_DATA_WIDTH), + APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT((aploffset+1)*c_NUM_WIDTH-1 downto aploffset * c_NUM_WIDTH), APL_TYP_OUT => APL_TYP_OUT((aploffset+1)*3-1 downto aploffset*3), APL_DATAREADY_OUT => APL_DATAREADY_OUT(aploffset), APL_READ_IN => APL_READ_IN(aploffset), @@ -748,21 +769,21 @@ begin APL_SEQNR_OUT => APL_SEQNR_OUT((aploffset+1)*8-1 downto aploffset*8), -- Internal direction port INT_MASTER_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i), - INT_MASTER_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_MASTER_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_MASTER_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_IN => buf_to_hub_INIT_READ(i), INT_MASTER_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_MASTER_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_MASTER_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_OUT => hub_to_buf_INIT_READ(i), INT_SLAVE_HEADER_IN => '0', INT_SLAVE_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_SLAVE_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_SLAVE_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_IN => buf_to_hub_REPLY_READ(i), INT_SLAVE_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i), - INT_SLAVE_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_SLAVE_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_SLAVE_READ_OUT => hub_to_buf_REPLY_READ(i), -- Status and control port STAT_FIFO_TO_INT => open, @@ -773,8 +794,8 @@ begin end generate; gen_trgapi : if TRG_NUMBER /= 0 generate - gen_apis : for i in 2**(MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER to 2**(MUX_WIDTH-1)*MII_NUMBER+API_NUMBER+TRG_NUMBER generate - constant trg_offset : integer := i - (2**(MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER); + gen_apis : for i in 2**(c_MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER to 2**(c_MUX_WIDTH-1)*MII_NUMBER+API_NUMBER+TRG_NUMBER generate + constant trg_offset : integer := i - (2**(c_MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER); begin TRG : trb_net16_term generic map ( @@ -786,12 +807,12 @@ begin RESET => RESET, CLK_EN => CLK_EN, INT_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i), - INT_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_READ_IN => buf_to_hub_REPLY_READ(i), INT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i), - INT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH), - INT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH), + INT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_READ_OUT => hub_to_buf_INIT_READ(i), -- "mini" APL, just to see the triggers coming in APL_DTYPE_OUT => TRG_DTYPE_OUT((trg_offset+1)*3-1 downto trg_offset*3), @@ -806,132 +827,132 @@ begin end generate; --rearrange vectors for hub logic - gen_rearrange : for CHANNEL in 0 to 2**(MUX_WIDTH-1)-1 generate + gen_rearrange : for CHANNEL in 0 to 2**(c_MUX_WIDTH-1)-1 generate constant api_num : integer := calc_special_number(CHANNEL, API_NUMBER, API_CHANNELS); constant trg_num : integer := calc_special_number(CHANNEL, TRG_NUMBER, TRG_CHANNELS); constant first_point_num : integer := calc_first_point_number(MII_NUMBER, CHANNEL, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS); constant is_ctrl_channel : integer := calc_is_ctrl_channel(CHANNEL, HUB_CTRL_CHANNELNUM); begin gen_hublogicsignals1 : for mii in 0 to MII_NUMBER-1 generate - constant buf_to_hub_num : integer := mii*2**(MUX_WIDTH-1)+CHANNEL; + constant buf_to_hub_num : integer := mii*2**(c_MUX_WIDTH-1)+CHANNEL; constant hublogic_num : integer := first_point_num + mii; begin HUB_INIT_DATAREADY_IN (hublogic_num) <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num); - HUB_INIT_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_INIT_READ(buf_to_hub_num) <= HUB_INIT_READ_OUT(hublogic_num); hub_to_buf_INIT_DATAREADY(buf_to_hub_num) <= HUB_INIT_DATAREADY_OUT(hublogic_num); - hub_to_buf_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_INIT_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_INIT_READ_IN (hublogic_num) <= hub_to_buf_INIT_READ(buf_to_hub_num); HUB_REPLY_DATAREADY_IN (hublogic_num) <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num); - HUB_REPLY_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_REPLY_READ(buf_to_hub_num) <= HUB_REPLY_READ_OUT(hublogic_num); hub_to_buf_REPLY_DATAREADY(buf_to_hub_num) <= HUB_REPLY_DATAREADY_OUT(hublogic_num); - hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_REPLY_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_REPLY_READ_IN (hublogic_num) <= hub_to_buf_REPLY_READ(buf_to_hub_num); end generate; gen_hublogicsignal_ctrl: if is_ctrl_channel = 1 generate constant hublogic_num : integer := first_point_num + MII_NUMBER; --!num of mii not num of channels! - constant buf_to_hub_num : integer := 2**(MUX_WIDTH-1)*MII_NUMBER; + constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER; begin HUB_INIT_DATAREADY_IN (hublogic_num) <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num); - HUB_INIT_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_INIT_READ(buf_to_hub_num) <= HUB_INIT_READ_OUT(hublogic_num); hub_to_buf_INIT_DATAREADY(buf_to_hub_num) <= HUB_INIT_DATAREADY_OUT(hublogic_num); - hub_to_buf_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_INIT_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_INIT_READ_IN (hublogic_num) <= hub_to_buf_INIT_READ(buf_to_hub_num); HUB_REPLY_DATAREADY_IN (hublogic_num) <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num); - HUB_REPLY_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_REPLY_READ(buf_to_hub_num) <= HUB_REPLY_READ_OUT(hublogic_num); hub_to_buf_REPLY_DATAREADY(buf_to_hub_num) <= HUB_REPLY_DATAREADY_OUT(hublogic_num); - hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_REPLY_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_REPLY_READ_IN (hublogic_num) <= hub_to_buf_REPLY_READ(buf_to_hub_num); end generate; g5: if api_num /= 0 generate gen_hublogicsignals2 : for api in 0 to API_NUMBER-1 generate constant hublogic_num : integer := first_point_num + MII_NUMBER + is_ctrl_channel + calc_special_number(CHANNEL, api, API_CHANNELS); - constant buf_to_hub_num : integer := 2**(MUX_WIDTH-1)*MII_NUMBER + 1 + api; + constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER + 1 + api; --calc_special_number(CHANNEL, api, API_CHANNELS) begin h1: if API_CHANNELS(api) = CHANNEL generate HUB_INIT_DATAREADY_IN (hublogic_num) <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num); - HUB_INIT_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_INIT_READ(buf_to_hub_num) <= HUB_INIT_READ_OUT(hublogic_num); hub_to_buf_INIT_DATAREADY(buf_to_hub_num) <= HUB_INIT_DATAREADY_OUT(hublogic_num); - hub_to_buf_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_INIT_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_INIT_READ_IN (hublogic_num) <= hub_to_buf_INIT_READ(buf_to_hub_num); HUB_REPLY_DATAREADY_IN (hublogic_num) <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num); - HUB_REPLY_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_REPLY_READ(buf_to_hub_num) <= HUB_REPLY_READ_OUT(hublogic_num); hub_to_buf_REPLY_DATAREADY(buf_to_hub_num) <= HUB_REPLY_DATAREADY_OUT(hublogic_num); - hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_REPLY_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_REPLY_READ_IN (hublogic_num) <= hub_to_buf_REPLY_READ(buf_to_hub_num); end generate; @@ -940,42 +961,42 @@ begin g3: if trg_num /= 0 generate gen_hublogicsignals3 : for trg in 0 to TRG_NUMBER-1 generate constant hublogic_num : integer := first_point_num + MII_NUMBER + is_ctrl_channel + calc_special_number(CHANNEL, API_NUMBER, API_CHANNELS) + calc_special_number(CHANNEL, trg, TRG_CHANNELS); - constant buf_to_hub_num : integer := 2**(MUX_WIDTH-1)*MII_NUMBER + 1 + API_NUMBER + trg; + constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER + 1 + API_NUMBER + trg; begin h1: if TRG_CHANNELS(trg) = CHANNEL generate HUB_INIT_DATAREADY_IN (hublogic_num) <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num); - HUB_INIT_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_INIT_READ(buf_to_hub_num) <= HUB_INIT_READ_OUT(hublogic_num); hub_to_buf_INIT_DATAREADY(buf_to_hub_num) <= HUB_INIT_DATAREADY_OUT(hublogic_num); - hub_to_buf_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_INIT_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_INIT_READ_IN (hublogic_num) <= hub_to_buf_INIT_READ(buf_to_hub_num); HUB_REPLY_DATAREADY_IN (hublogic_num) <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num); - HUB_REPLY_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16) - <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16); - HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*2-1 downto hublogic_num*2) - <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2); + HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH) + <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH); + HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH) + <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH); buf_to_hub_REPLY_READ(buf_to_hub_num) <= HUB_REPLY_READ_OUT(hublogic_num); hub_to_buf_REPLY_DATAREADY(buf_to_hub_num) <= HUB_REPLY_DATAREADY_OUT(hublogic_num); - hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16) - <= HUB_REPLY_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16); - hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*2-1 downto buf_to_hub_num*2) - <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*2-1 downto hublogic_num*2); + hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH) + <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH); + hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH) + <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH); HUB_REPLY_READ_IN (hublogic_num) <= hub_to_buf_REPLY_READ(buf_to_hub_num); end generate; @@ -1000,7 +1021,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --generate hub logic - gen_hub_logic: for i in 0 to 2**(MUX_WIDTH-1)-1 generate + gen_hub_logic: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate constant point_num : integer := calc_point_number (MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS); constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS); constant next_point_num : integer := first_point_num + point_num; @@ -1010,31 +1031,28 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); HUBLOGIC : trb_net16_hub_logic generic map ( --media interfaces - POINT_NUMBER => point_num, - --general settings - DATA_WIDTH => DATA_WIDTH, - NUM_WIDTH => NUM_WIDTH + POINT_NUMBER => point_num ) port map( CLK => CLK, RESET => RESET, CLK_EN => CLK_EN, INIT_DATAREADY_IN => HUB_INIT_DATAREADY_IN(next_point_num-1 downto first_point_num), - INIT_DATA_IN => HUB_INIT_DATA_IN(next_point_num*DATA_WIDTH-1 downto first_point_num*DATA_WIDTH), - INIT_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_IN(next_point_num*NUM_WIDTH-1 downto first_point_num*NUM_WIDTH), + INIT_DATA_IN => HUB_INIT_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH), + INIT_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH), INIT_READ_OUT => HUB_INIT_READ_OUT(next_point_num-1 downto first_point_num), INIT_DATAREADY_OUT => HUB_INIT_DATAREADY_OUT(next_point_num-1 downto first_point_num), - INIT_DATA_OUT => HUB_INIT_DATA_OUT(next_point_num*DATA_WIDTH-1 downto first_point_num*DATA_WIDTH), - INIT_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_OUT(next_point_num*NUM_WIDTH-1 downto first_point_num*NUM_WIDTH), + INIT_DATA_OUT => HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH), + INIT_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH), INIT_READ_IN => HUB_INIT_READ_IN(next_point_num-1 downto first_point_num), REPLY_HEADER_OUT => HUB_REPLY_SEND_HEADER_OUT(next_point_num-1 downto first_point_num), REPLY_DATAREADY_IN => HUB_REPLY_DATAREADY_IN(next_point_num-1 downto first_point_num), - REPLY_DATA_IN => HUB_REPLY_DATA_IN(next_point_num*DATA_WIDTH-1 downto first_point_num*DATA_WIDTH), - REPLY_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_IN(next_point_num*NUM_WIDTH-1 downto first_point_num*NUM_WIDTH), + REPLY_DATA_IN => HUB_REPLY_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH), + REPLY_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH), REPLY_READ_OUT => HUB_REPLY_READ_OUT(next_point_num-1 downto first_point_num), REPLY_DATAREADY_OUT => HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num), - REPLY_DATA_OUT => HUB_REPLY_DATA_OUT(next_point_num*DATA_WIDTH-1 downto first_point_num*DATA_WIDTH), - REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*NUM_WIDTH-1 downto first_point_num*NUM_WIDTH), + REPLY_DATA_OUT => HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH), + REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH), REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num), STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16), STAT_POINTS_locked => open, @@ -1047,7 +1065,6 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); hub_control : trb_net16_regIO generic map( - MY_ADDRESS => HUB_ADDRESS, REGISTER_WIDTH => 32, ADDRESS_WIDTH => 16, ADDRESS_USED_WIDTH => HUB_CTRL_REG_ADDR_WIDTH, @@ -1062,6 +1079,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); CLK => CLK, RESET => RESET, CLK_EN => CLK_EN, + MY_ADDRESS => HUB_ADDRESS, -- Port to API API_DATA_OUT => HC_DATA_IN, API_PACKET_NUM_OUT => HC_PACKET_NUM_IN, @@ -1101,11 +1119,11 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); HC_STAT_REGS(31 downto 0) <= buf_HUB_STAT_GEN; - HC_STAT_REGS(32+2**(MUX_WIDTH-1)*16-1 downto 32) <= buf_HUB_STAT_CHANNEL; + HC_STAT_REGS(32+2**(c_MUX_WIDTH-1)*16-1 downto 32) <= buf_HUB_STAT_CHANNEL; HUB_CTRL_GEN <= HC_CTRL_REGS(31 downto 0); - HUB_CTRL_CHANNEL <= HC_CTRL_REGS(32+2**(MUX_WIDTH-1)*16-1 downto 32); - HUB_CTRL_activepoints <= HC_CTRL_REGS(128+2**(MUX_WIDTH-1)*32-1 downto 128); + HUB_CTRL_CHANNEL <= HC_CTRL_REGS(32+2**(c_MUX_WIDTH-1)*16-1 downto 32); + HUB_CTRL_activepoints <= HC_CTRL_REGS(128+2**(c_MUX_WIDTH-1)*32-1 downto 128); HC_STAT_REGS(8*32-1 downto 96) <= (others => '0'); diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index aba2b29..5169a11 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -2,13 +2,54 @@ library ieee; use ieee.std_logic_1164.all; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; package trb_net16_hub_func is - type hub_iobuf_config_t is array(0 to 63) of integer; - type hub_api_config_t is array(0 to 15) of integer; - + type hub_iobuf_config_t is array(0 to 63) of integer; --2**(c_MUX_WIDTH-1)*c_MAX_MII_PER_HUB-1 + type hub_api_config_t is array(0 to 7) of integer; + type hub_channel_config_t is array(0 to 2**(3-1)-1) of integer; + + --hub constraints (only needed for generic configuration) + constant c_MAX_MII_PER_HUB : integer := 16; + constant c_MAX_API_PER_HUB : integer := 8; + constant c_MAX_TRG_PER_HUB : integer := 8; + constant c_MAX_POINTS_PER_HUB : integer := 18; + + constant std_HUB_INIT_DEPTH : hub_iobuf_config_t :=( 6,6,6,6, --MII 0 + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6); --MII 15 + constant std_HUB_REPLY_DEPTH : hub_iobuf_config_t:=( 6,6,6,6, --MII 0 + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6, + 6,6,6,6); --MII 15 + function calc_point_number (MII_NUMBER : integer; CHANNEL : integer; HUB_CTRL_CHANNEL : integer; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index 0e758b5..bc4093e 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -3,17 +3,14 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_hub_logic is generic ( --media interfaces - POINT_NUMBER : integer range 2 to 32 := 12; - - --general settings - DATA_WIDTH : integer range 16 to 16 := 16; - NUM_WIDTH : integer range 2 to 2 := 2 + POINT_NUMBER : integer range 2 to 32 := 12 ); port ( CLK : in std_logic; @@ -21,21 +18,21 @@ entity trb_net16_hub_logic is CLK_EN : in std_logic; --Internal interfaccs to IOBufs INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); --Status ports (for debugging) STAT : out std_logic_vector (15 downto 0); @@ -50,8 +47,6 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is component trb_net16_sbuf is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; VERSION : integer := 0 ); port( @@ -63,19 +58,21 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is COMB_DATAREADY_IN: in std_logic; --comb logic provides data word COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle COMB_READ_IN: in std_logic; --comb logic IS reading - COMB_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in std_logic_vector(NUM_WIDTH-1 downto 0); + COMB_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in std_logic_vector(c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT: out std_logic; - SYN_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out std_logic_vector(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); SYN_READ_IN: in std_logic; -- Status and control port STAT_BUFFER: out std_logic ); end component; component trb_net_priority_arbiter is - generic (WIDTH : integer := POINT_NUMBER); + generic ( + WIDTH : integer := POINT_NUMBER + ); port( -- Misc CLK : in std_logic; @@ -91,8 +88,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is --signals init_pool signal INIT_POOL_DATAREADY : std_logic; signal INIT_POOL_READ : std_logic; - signal INIT_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal INIT_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal INIT_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal INIT_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0); signal saved_INIT_TYPE, current_INIT_TYPE : std_logic_vector(2 downto 0); @@ -100,15 +97,16 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal buf_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); signal REPLY_POOL_DATAREADY : std_logic; signal REPLY_POOL_READ : std_logic; - signal REPLY_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal REPLY_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal saved_REPLY_TYPE , current_REPLY_TYPE : std_logic_vector(2 downto 0); signal REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal next_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_REPLY_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal reading_trmF1, reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0); - signal REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(DATA_WIDTH-1 downto 0); + signal REPLY_combined_trm_F1, REPLY_combined_trm_F2 : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal REPLY_MUX_real_reading : std_logic; + signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0); --general signals signal locked, next_locked : std_logic; @@ -129,8 +127,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal data_counter : std_logic_vector(7 downto 0); signal SEQ_NR : std_logic_vector(7 downto 0); signal comb_REPLY_POOL_DATAREADY : std_logic; - signal comb_REPLY_POOL_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal comb_REPLY_POOL_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal comb_REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal comb_REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal REPLY_POOL_next_read : std_logic; signal comb_REPLY_POOL_next_read : std_logic; @@ -139,8 +137,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal tmp_REPLY_READ_OUT : std_logic_vector(POINT_NUMBER-1 downto 0); signal comb_REPLY_muxed_DATAREADY : std_logic; - signal comb_REPLY_muxed_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal comb_REPLY_muxed_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal comb_REPLY_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal comb_REPLY_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal reply_arbiter_CLK_EN : std_logic; signal init_arbiter_CLK_EN : std_logic; signal init_arbiter_ENABLE : std_logic; @@ -148,8 +146,8 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal reply_arbiter_input : std_logic_vector(POINT_NUMBER-1 downto 0); signal INIT_muxed_DATAREADY : std_logic; - signal INIT_muxed_DATA : std_logic_vector(DATA_WIDTH-1 downto 0); - signal INIT_muxed_PACKET_NUM : std_logic_vector(NUM_WIDTH-1 downto 0); + signal INIT_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal INIT_muxed_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal INIT_muxed_READ : std_logic; signal comb_INIT_next_read : std_logic; signal reply_fsm_state : std_logic; @@ -164,7 +162,9 @@ STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0'); STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; INIT_POOL_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => 0) + generic map ( + Version => std_SBUF_VERSION + ) port map ( CLK => CLK, RESET => RESET, @@ -190,8 +190,6 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; end if; end process; ---mux ---generates INIT_READ_OUT --choosing reply point INIT_ARBITER: trb_net_priority_arbiter @@ -210,32 +208,32 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --Datapool for Init-Channel INIT_muxed_DATAREADY <= or_all(INIT_DATAREADY_IN) and not init_locked and INIT_muxed_READ; - INIT_POOL_READ <= and_all(INIT_READ_IN or init_has_read_from_pool or locking_point or not CTRL_activepoints(POINT_NUMBER-1 downto 0)); + INIT_POOL_READ <= and_all(INIT_READ_IN or init_has_read_from_pool or locking_point or not real_activepoints); INIT_READ_OUT <= buf_INIT_READ_OUT; gen_iro : for i in 0 to POINT_NUMBER-1 generate buf_INIT_READ_OUT(i) <= init_arbiter_read_out(i) and not init_locked and INIT_muxed_READ; end generate; - gen_init_pool_data0: for i in 0 to DATA_WIDTH-1 generate + gen_init_pool_data0: for i in 0 to c_DATA_WIDTH-1 generate process(INIT_DATA_IN, buf_INIT_READ_OUT) variable VAR_INIT_POOL_DATA : std_logic; begin VAR_INIT_POOL_DATA := '0'; gen_init_pool_data1: for j in 0 to POINT_NUMBER-1 loop - VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or (INIT_DATA_IN(j*DATA_WIDTH+i) and buf_INIT_READ_OUT(j)); + VAR_INIT_POOL_DATA := VAR_INIT_POOL_DATA or (INIT_DATA_IN(j*c_DATA_WIDTH+i) and buf_INIT_READ_OUT(j)); end loop; INIT_muxed_DATA(i) <= VAR_INIT_POOL_DATA; end process; end generate; - gen_init_pool_data2: for i in 0 to NUM_WIDTH-1 generate + gen_init_pool_data2: for i in 0 to c_NUM_WIDTH-1 generate process(INIT_PACKET_NUM_IN, buf_INIT_READ_OUT) variable VAR_INIT_POOL_PACKET_NUM : std_logic; begin VAR_INIT_POOL_PACKET_NUM := '0'; gen_init_pool_data3: for j in 0 to POINT_NUMBER-1 loop - VAR_INIT_POOL_PACKET_NUM := VAR_INIT_POOL_PACKET_NUM or (INIT_PACKET_NUM_IN(j*NUM_WIDTH+i) and buf_INIT_READ_OUT(j)); + VAR_INIT_POOL_PACKET_NUM := VAR_INIT_POOL_PACKET_NUM or (INIT_PACKET_NUM_IN(j*c_NUM_WIDTH+i) and buf_INIT_READ_OUT(j)); end loop; INIT_muxed_PACKET_NUM(i) <= VAR_INIT_POOL_PACKET_NUM; end process; @@ -260,9 +258,9 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --signals to obufs gen_init_data_out: for i in 0 to POINT_NUMBER-1 generate - INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and CTRL_activepoints(i) and not locking_point(i); - INIT_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= INIT_POOL_DATA; - INIT_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= INIT_POOL_PACKET_NUM; + INIT_DATAREADY_OUT(i) <= INIT_POOL_DATAREADY and not init_has_read_from_pool(i) and real_activepoints(i) and not locking_point(i); + INIT_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= INIT_POOL_DATA; + INIT_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= INIT_POOL_PACKET_NUM; end generate; @@ -297,8 +295,8 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; gen_reply_data_out: for i in 0 to POINT_NUMBER-1 generate REPLY_DATAREADY_OUT(i) <= REPLY_POOL_DATAREADY and locking_point(i); - REPLY_DATA_OUT((i+1)*DATA_WIDTH-1 downto i*DATA_WIDTH) <= REPLY_POOL_DATA; - REPLY_PACKET_NUM_OUT((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) <= REPLY_POOL_PACKET_NUM; + REPLY_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= REPLY_POOL_DATA; + REPLY_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= REPLY_POOL_PACKET_NUM; end generate; REPLY_POOL_READ <= or_all(REPLY_READ_IN and locking_point); @@ -356,10 +354,10 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; process(REPLY_reading_trm, REPLY_PACKET_NUM_IN, REPLY_DATA_IN) begin next_REPLY_reading_trm(i) <= REPLY_reading_trm(i); - if REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "11" then + if REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "11" then next_REPLY_reading_trm(i) <= '0'; - elsif REPLY_DATA_IN(i*DATA_WIDTH+2 downto i*DATA_WIDTH) = TYPE_TRM - and REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "00" then + elsif REPLY_DATA_IN(i*c_DATA_WIDTH+2 downto i*c_DATA_WIDTH) = TYPE_TRM + and REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "00" then next_REPLY_reading_trm(i) <= '1'; end if; end process; @@ -379,22 +377,22 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate --- reading_trmF1(i) <= '1' when REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "01" +-- reading_trmF1(i) <= '1' when REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "01" -- and REPLY_reading_trm(i) = '1' -- and REPLY_DATAREADY_IN(i) = '1' -- else '0'; --- reading_trmF2(i) <= '1' when REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1 downto i*NUM_WIDTH) = "10" +-- reading_trmF2(i) <= '1' when REPLY_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = "10" -- and REPLY_reading_trm(i) = '1' -- and REPLY_DATAREADY_IN(i) = '1' -- else '0'; - reading_trmF1(i) <= not REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1) and REPLY_PACKET_NUM_IN(i*NUM_WIDTH) + reading_trmF1(i) <= not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i); - reading_trmF2(i) <= REPLY_PACKET_NUM_IN((i+1)*NUM_WIDTH-1) and not REPLY_PACKET_NUM_IN(i*NUM_WIDTH) + reading_trmF2(i) <= REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and REPLY_reading_trm(i) and REPLY_DATAREADY_IN(i); end generate; - gen_combining_trm : for j in 0 to DATA_WIDTH-1 generate + gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate process(CLK) variable tmpF1, tmpF2 : std_logic; begin @@ -406,8 +404,8 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; tmpF1 := '0'; tmpF2 := '0'; for i in 0 to POINT_NUMBER-1 loop - tmpF1 := tmpF1 or (REPLY_DATA_IN(i*DATA_WIDTH+j) and reading_trmF1(i)); - tmpF2 := tmpF2 or (REPLY_DATA_IN(i*DATA_WIDTH+j) and reading_trmF2(i)); + tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF1(i)); + tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF2(i)); end loop; REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1; REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2; @@ -417,6 +415,19 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; end generate; +--real_activepoints can be set between transfers only, but can be cleared at any time +---------------------------------- + gen_real_activepoints : process (CLK) + begin + if rising_edge(CLK) then + if locked = '0' then + real_activepoints <= CTRL_activepoints(POINT_NUMBER-1 downto 0); + else + real_activepoints <= real_activepoints and CTRL_activepoints(POINT_NUMBER-1 downto 0); + end if; + end if; + end process; + --count received TRM ---------------------------------- @@ -426,7 +437,7 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; if RESET = '1' or send_reply_trm = '1' then got_trm <= (others => '0'); else - got_trm <= got_trm or locking_point or reading_trmF2 or not CTRL_activepoints(POINT_NUMBER-1 downto 0); + got_trm <= got_trm or locking_point or reading_trmF2 or not real_activepoints; end if; end if; end process; @@ -463,7 +474,9 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --REPLY mux select input ---------------------------------- REPLY_ARBITER: trb_net_priority_arbiter - generic map (WIDTH => POINT_NUMBER) + generic map ( + WIDTH => POINT_NUMBER + ) port map ( CLK => CLK, RESET => RESET, @@ -513,25 +526,25 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; --REPLY mux ---------------------------------- - gen_reply_mux1 : for i in 0 to DATA_WIDTH-1 generate + gen_reply_mux1 : for i in 0 to c_DATA_WIDTH-1 generate data_mux : process(REPLY_DATA_IN, REPLY_MUX_reading) variable tmp_data : std_logic; begin tmp_data := '0'; gen_data_mux : for j in 0 to POINT_NUMBER-1 loop - tmp_data := tmp_data or (REPLY_DATA_IN(j*DATA_WIDTH+i) and REPLY_MUX_reading(j)); + tmp_data := tmp_data or (REPLY_DATA_IN(j*c_DATA_WIDTH+i) and REPLY_MUX_reading(j)); end loop; comb_REPLY_muxed_DATA(i) <= tmp_data; end process; end generate; - gen_reply_mux2 : for i in 0 to NUM_WIDTH-1 generate + gen_reply_mux2 : for i in 0 to c_NUM_WIDTH-1 generate packet_num_mux : process(REPLY_PACKET_NUM_IN, REPLY_MUX_reading) variable tmp_pm : std_logic; begin tmp_pm := '0'; gen_pm_mux : for j in 0 to POINT_NUMBER-1 loop - tmp_pm := tmp_pm or (REPLY_PACKET_NUM_IN(j*NUM_WIDTH+i) and REPLY_MUX_reading(j)); + tmp_pm := tmp_pm or (REPLY_PACKET_NUM_IN(j*c_NUM_WIDTH+i) and REPLY_MUX_reading(j)); end loop; comb_REPLY_muxed_PACKET_NUM(i) <= tmp_pm; end process; @@ -602,7 +615,9 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; end process; REPLY_POOL_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => 0) + generic map ( + Version => std_SBUF_VERSION + ) port map ( CLK => CLK, RESET => RESET, @@ -618,7 +633,4 @@ STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; SYN_READ_IN => REPLY_POOL_READ ); - - - end architecture; diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 5f8fc77..71e867c 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -6,13 +6,15 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_ibuf is generic ( - DEPTH : integer range 0 to 7 := 1; - USE_ACKNOWLEDGE : integer range 0 to 1 := 1; - IBUF_SECURE_MODE : integer range 0 to 1 := 0 + DEPTH : integer range 0 to 7 := std_FIFO_DEPTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE --use sbuf in med_to_api direction? ); port( @@ -22,15 +24,15 @@ entity trb_net16_ibuf is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN :in std_logic_vector(1 downto 0); + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); MED_READ_OUT: out std_logic; -- buffer reads a word from media MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits -- Internal direction port INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT:out std_logic_vector(1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits -- Status and control port @@ -44,18 +46,17 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is component trb_net16_fifo is generic ( - DATA_WIDTH : integer := 16; -- FIFO word width - NUM_WIDTH : integer := 2; - DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1) + DEPTH : integer := 4 + ); port ( CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data - PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data - PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data READ_ENABLE_IN : in std_logic; FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic; @@ -65,8 +66,6 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is component trb_net16_sbuf is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; VERSION : integer := 0 ); port( @@ -78,22 +77,22 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is COMB_DATAREADY_IN: in std_logic; --comb logic provides data word COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle COMB_READ_IN: in std_logic; --comb logic IS reading - COMB_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in std_logic_vector(NUM_WIDTH-1 downto 0); + COMB_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in std_logic_vector(c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT: out std_logic; - SYN_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out std_logic_vector(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); SYN_READ_IN: in std_logic; -- Status and control port STAT_BUFFER: out std_logic ); end component; - signal fifo_data_in : std_logic_vector(15 downto 0); - signal fifo_data_out : std_logic_vector(15 downto 0); - signal fifo_packet_num_in : std_logic_vector(1 downto 0); - signal fifo_packet_num_out : std_logic_vector(1 downto 0); + signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal fifo_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal fifo_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal fifo_write, fifo_read : std_logic; signal fifo_full, fifo_empty : std_logic; signal fifo_depth : std_logic_vector(7 downto 0); @@ -111,8 +110,8 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal got_eob_out, reg_eob_out: std_logic; signal sbuf_free, comb_next_read: std_logic; signal tmp_INT_DATAREADY_OUT: std_logic; - signal tmp_INT_DATA_OUT: std_logic_vector(15 downto 0); - signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(1 downto 0); + signal tmp_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); signal current_last_header, next_last_header : std_logic_vector(47 downto 0); --last_header does not contain the TYPE_HDR, only packets 1 to 3 are stored. signal current_last_header_F1, current_last_header_F2, current_last_header_F3 : std_logic_vector(15 downto 0); @@ -127,9 +126,8 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is begin FIFO: trb_net16_fifo generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, - DEPTH => DEPTH) + DEPTH => DEPTH + ) port map ( CLK => CLK, RESET => RESET, @@ -228,9 +226,11 @@ begin end if; end process; - gensecure : if IBUF_SECURE_MODE = 1 generate + gensecure : if SECURE_MODE = 1 generate SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => 16, NUM_WIDTH => 2, Version => 0) + generic map ( + Version => SBUF_VERSION + ) port map ( CLK => CLK, RESET => RESET, @@ -248,7 +248,7 @@ begin sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed end generate; - gen_notsecure : if IBUF_SECURE_MODE = 0 generate + gen_notsecure : if SECURE_MODE = 0 generate INT_DATA_OUT <= tmp_INT_DATA_OUT; INT_DATAREADY_OUT <= tmp_INT_DATAREADY_OUT; INT_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT; @@ -266,7 +266,7 @@ begin tmp_INT_DATAREADY_OUT <= '0'; got_eob_out <= '0'; got_locked <= is_locked; - if IBUF_SECURE_MODE = 1 then + if SECURE_MODE = 1 then fifo_read <= sbuf_free and not fifo_empty; else fifo_read <= INT_READ_IN and buf_INT_DATAREADY_OUT and not fifo_empty; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index b638ca1..5c1805e 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -3,15 +3,13 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_io_multiplexer is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - MUX_WIDTH : integer range 1 to 5 := 3; MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not? ); @@ -23,25 +21,25 @@ entity trb_net16_io_multiplexer is -- Media direction port MED_DATAREADY_IN: in STD_LOGIC; - MED_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); MED_READ_OUT: out STD_LOGIC; MED_DATAREADY_OUT: out STD_LOGIC; - MED_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); MED_READ_IN: in STD_LOGIC; -- Internal direction port - INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0); - INT_DATA_OUT: out STD_LOGIC_VECTOR ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_IN: in STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_OUT: out STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0); - INT_DATA_IN: in STD_LOGIC_VECTOR ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**MUX_WIDTH)-1 downto 0); - INT_READ_OUT: out STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0); + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); -- Status and control port CTRL: in STD_LOGIC_VECTOR (31 downto 0); @@ -54,17 +52,17 @@ end trb_net16_io_multiplexer; architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is component trb_net_pattern_gen is - generic (MULT_WIDTH : integer := 1); + generic ( + WIDTH : integer := 1 + ); port( - INPUT_IN : in STD_LOGIC_VECTOR (MUX_WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**MUX_WIDTH-1 downto 0) + INPUT_IN : in STD_LOGIC_VECTOR (c_MUX_WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0) ); end component; component trb_net16_sbuf is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; VERSION : integer := 0 ); port( @@ -76,12 +74,12 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); SYN_READ_IN : in STD_LOGIC; -- Status and control port STAT_BUFFER : out STD_LOGIC @@ -89,7 +87,9 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is end component; component trb_net_priority_arbiter is - generic (WIDTH : integer := 2**MUX_WIDTH); + generic ( + WIDTH : integer := 2**c_MUX_WIDTH + ); port( -- Misc CLK : in std_logic; @@ -102,18 +102,18 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is ); end component; - signal MUX_SBUF_data_out : std_logic_vector(DATA_WIDTH+1 downto 0); - signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); - signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); + signal MUX_SBUF_data_out : std_logic_vector(c_DATA_WIDTH+1 downto 0); + signal demux_next_READ, current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); + signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); signal current_MED_READ_OUT, next_MED_READ_OUT: STD_LOGIC; - signal tmp_INT_READ_OUT, final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); - --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); + signal tmp_INT_READ_OUT, final_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); + --signal tmp_tmp_INT_READ_OUT: STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); signal mux_read, mux_enable, mux_next_READ: STD_LOGIC; - signal current_mux_buffer: STD_LOGIC_VECTOR (DATA_WIDTH+2-1 downto 0); + signal current_mux_buffer: STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0); signal endpoint_locked, next_endpoint_locked: std_logic; - signal demux_sbuf_data_in : std_logic_vector((DATA_WIDTH+2)-1 downto 0); - signal demux_sbuf_data_out: std_logic_vector((DATA_WIDTH+2)*(2**MUX_WIDTH)-1 downto 0); - signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**MUX_WIDTH)-1 downto 0); + signal demux_sbuf_data_in : std_logic_vector((c_DATA_WIDTH+2)-1 downto 0); + signal demux_sbuf_data_out: std_logic_vector((c_DATA_WIDTH+2)*(2**c_MUX_WIDTH)-1 downto 0); + signal current_INT_READ_OUT : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH)-1 downto 0); signal current_mux_packet_number : std_logic_vector (1 downto 0); signal last_mux_enable : std_logic; signal arbiter_CLK_EN : std_logic; @@ -122,10 +122,12 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- DEMUX ------------------------------------------------------------------------------ - G1: for i in 0 to 2**MUX_WIDTH-1 generate + G1: for i in 0 to 2**c_MUX_WIDTH-1 generate gensbuf: if MUX_SECURE_MODE = 1 generate DEMUX_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => DATA_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0) + generic map ( + VERSION => std_SBUF_VERSION + ) port map ( CLK => CLK, RESET => RESET, @@ -136,7 +138,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is COMB_DATA_IN => MED_DATA_IN, COMB_PACKET_NUM_IN => MED_PACKET_NUM_IN, SYN_DATAREADY_OUT => INT_DATAREADY_OUT(i), - SYN_DATA_OUT => INT_DATA_OUT ((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i)), + SYN_DATA_OUT => INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)), SYN_PACKET_NUM_OUT => INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i), SYN_READ_IN => INT_READ_IN(i) ); @@ -146,11 +148,11 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is begin if rising_edge(CLK) then if RESET = '1' then - INT_DATA_OUT ((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i)) <= (others => '0'); + INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)) <= (others => '0'); INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= (others => '0'); INT_DATAREADY_OUT(i) <= '0'; else - INT_DATA_OUT ((DATA_WIDTH)*(i+1)-1 downto (DATA_WIDTH)*(i)) <= MED_DATA_IN; + INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)) <= MED_DATA_IN; INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= MED_PACKET_NUM_IN; INT_DATAREADY_OUT(i) <= next_demux_dr(i); end if; @@ -192,9 +194,11 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- the output of the pattern generator is only valid for packet number 00! DEFDR: trb_net_pattern_gen - generic map (MULT_WIDTH => MUX_WIDTH) + generic map ( + WIDTH => c_MUX_WIDTH + ) port map ( - INPUT_IN => MED_DATA_IN(3+MUX_WIDTH-1 downto 3), + INPUT_IN => MED_DATA_IN(3+c_MUX_WIDTH-1 downto 3), RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case ); @@ -226,7 +230,9 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -- MUX part with arbitration scheme ------------------------------------------------------------------------------- ARBITER: trb_net_priority_arbiter - generic map (WIDTH => 2**MUX_WIDTH) + generic map ( + WIDTH => 2**c_MUX_WIDTH + ) port map ( CLK => CLK, RESET => RESET, @@ -283,7 +289,7 @@ ARBITER: trb_net_priority_arbiter -- else final_INT_READ_OUT; STAT(15 downto 0) <= (others => '0'); - STAT(17 downto 16) <= current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH) xor current_mux_packet_number; + STAT(17 downto 16) <= current_mux_buffer(c_DATA_WIDTH+1 downto c_DATA_WIDTH) xor current_mux_packet_number; STAT(31 downto 18) <= (others => '0'); @@ -314,7 +320,9 @@ ARBITER: trb_net_priority_arbiter MUX_SBUF: trb_net16_sbuf - generic map (DATA_WIDTH => DATA_WIDTH, NUM_WIDTH => NUM_WIDTH, VERSION => 0) + generic map ( + VERSION => std_SBUF_VERSION + ) port map ( CLK => CLK, RESET => RESET, @@ -322,8 +330,8 @@ ARBITER: trb_net_priority_arbiter COMB_DATAREADY_IN => mux_read, COMB_next_READ_OUT => mux_next_READ, COMB_READ_IN => '1', - COMB_DATA_IN => current_mux_buffer(DATA_WIDTH-1 downto 0), - COMB_PACKET_NUM_IN => current_mux_buffer(DATA_WIDTH+1 downto DATA_WIDTH), + COMB_DATA_IN => current_mux_buffer(c_DATA_WIDTH-1 downto 0), + COMB_PACKET_NUM_IN => current_mux_buffer(c_DATA_WIDTH+1 downto c_DATA_WIDTH), SYN_DATAREADY_OUT => MED_DATAREADY_OUT, SYN_DATA_OUT => MED_DATA_OUT, SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, @@ -332,17 +340,17 @@ ARBITER: trb_net_priority_arbiter process (current_INT_READ_OUT, INT_DATA_IN, INT_PACKET_NUM_IN) - variable var_mux_buffer : STD_LOGIC_VECTOR (DATA_WIDTH+2-1 downto 0); - variable k : integer range 0 to 2**MUX_WIDTH-1 := 0; + variable var_mux_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH+2-1 downto 0); + variable k : integer range 0 to 2**c_MUX_WIDTH-1 := 0; begin k := 0; var_mux_buffer := (others => '0'); - for i in 0 to 2**MUX_WIDTH-1 loop - for j in 0 to DATA_WIDTH+NUM_WIDTH-1 loop - if j < DATA_WIDTH then - var_mux_buffer(j) := var_mux_buffer(j) or (INT_DATA_IN(DATA_WIDTH*i+j) and current_INT_READ_OUT(i)); + for i in 0 to 2**c_MUX_WIDTH-1 loop + for j in 0 to c_DATA_WIDTH+c_NUM_WIDTH-1 loop + if j < c_DATA_WIDTH then + var_mux_buffer(j) := var_mux_buffer(j) or (INT_DATA_IN(c_DATA_WIDTH*i+j) and current_INT_READ_OUT(i)); else - var_mux_buffer(j) := var_mux_buffer(j) or (INT_PACKET_NUM_IN(NUM_WIDTH*i+j-DATA_WIDTH) and current_INT_READ_OUT(i)); + var_mux_buffer(j) := var_mux_buffer(j) or (INT_PACKET_NUM_IN(c_NUM_WIDTH*i+j-c_DATA_WIDTH) and current_INT_READ_OUT(i)); end if; if current_INT_READ_OUT(i) = '1' and INT_PACKET_NUM_IN(2*(i+1)-1 downto 2*i) = "00" then k := i; @@ -351,7 +359,7 @@ ARBITER: trb_net_priority_arbiter end if; end loop; end loop; - var_mux_buffer(3+MUX_WIDTH-1 downto 3) := var_mux_buffer(3+MUX_WIDTH-1 downto 3) or conv_std_logic_vector(k, MUX_WIDTH); + var_mux_buffer(3+c_MUX_WIDTH-1 downto 3) := var_mux_buffer(3+c_MUX_WIDTH-1 downto 3) or conv_std_logic_vector(k, c_MUX_WIDTH); current_mux_buffer <= var_mux_buffer; end process; diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 7295c92..1852bdb 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -1,24 +1,23 @@ --- main working horse for the trbnet --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIOBUF - LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; ---Entity decalaration for clock generator + entity trb_net16_iobuf is generic ( - INIT_DEPTH : integer := 1; - REPLY_DEPTH : integer := 1; - IBUF_SECURE_MODE : integer range 0 to 1 := 1; - --use sbuf in med_to_api direction? - USE_ACKNOWLEDGE : integer range 0 to 1 := 1; - INIT_CAN_SEND_DATA : integer range 0 to 1 := 1; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := 1 + INIT_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH; + REPLY_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_REPLY_CHANNEL : integer range 0 to 1 := c_YES; -- not used yet + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES ); port( -- Misc @@ -26,63 +25,59 @@ entity trb_net16_iobuf is RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port - MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_INIT_READ_IN: in std_logic; -- Media is reading - - MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media - MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits - - MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out - --by the media (via the TrbNetIOMultiplexer) - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); - MED_REPLY_READ_IN: in std_logic; -- Media is reading - - MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media - -- (the IOBUF MUST read) - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN :in std_logic_vector (1 downto 0); - MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media - MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) + MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_OUT: out std_logic; + MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) + MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_OUT: out std_logic; + MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Internal direction port INT_INIT_DATAREADY_OUT: out std_logic; - INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_IN: in std_logic; INT_INIT_DATAREADY_IN: in std_logic; - INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_READ_OUT: out std_logic; INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last -- header (only for the reply path) INT_REPLY_DATAREADY_OUT: out std_logic; - INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_IN: in std_logic; INT_REPLY_DATAREADY_IN: in std_logic; - INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_REPLY_PACKET_NUM_IN :in std_logic_vector (1 downto 0); + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_READ_OUT: out std_logic; -- Status and control port - STAT_GEN: out std_logic_vector (31 downto 0); -- General Status - STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control - STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN: in std_logic_vector (31 downto 0); - CTRL_LOCKED: in std_logic_vector (31 downto 0); + STAT_GEN: out std_logic_vector (31 downto 0); + STAT_LOCKED: out std_logic_vector (31 downto 0); + STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); + STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); + CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_LOCKED: in std_logic_vector (31 downto 0); STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0); STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0) ); @@ -93,8 +88,8 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is component trb_net16_obuf is generic ( DATA_COUNT_WIDTH : integer := 5; - CAN_SEND_DATA : integer range 0 to 1 := 1; - USE_ACKNOWLEDGE : integer range 0 to 1 + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION ); port( -- Misc @@ -103,13 +98,13 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector(1 downto 0); + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_IN: in std_logic; -- Internal direction port INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector(1 downto 0); + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT: out std_logic; -- Status and control port STAT_LOCKED: out std_logic_vector (15 downto 0); @@ -127,8 +122,8 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector(1 downto 0); + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_IN: in std_logic; --STAT STAT_LOCKED: out std_logic_vector (15 downto 0); @@ -140,10 +135,10 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is component trb_net16_ibuf is generic ( - DEPTH : integer range 0 to 7 := 1; - USE_ACKNOWLEDGE : integer range 0 to 1; - IBUF_SECURE_MODE : integer range 0 to 1 := 1 - --use sbuf in med_to_api direction? + DEPTH : integer range 0 to 7 := std_FIFO_DEPTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE ); port( -- Misc @@ -152,17 +147,17 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN :in std_logic_vector(1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Internal direction port INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT:out std_logic_vector(1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; - INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits + INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status and control port STAT_LOCKED: out std_logic_vector (15 downto 0); CTRL_LOCKED: in std_logic_vector (15 downto 0); @@ -172,9 +167,8 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is component trb_net16_term_ibuf is generic( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - VERSION : integer range 0 to 1 := 0 + SECURE_MODE : integer range 0 to 1 := std_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION ); port( -- Misc @@ -183,17 +177,17 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0); - MED_READ_OUT: out std_logic; -- buffer reads a word from media - MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Internal direction port INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; - INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits + INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status and control port STAT_LOCKED: out std_logic_vector (15 downto 0); CTRL_LOCKED: in std_logic_vector (15 downto 0); @@ -227,9 +221,11 @@ begin GEN_INIT_IBUF: if INIT_DEPTH>0 generate INITIBUF : trb_net16_ibuf generic map ( - DEPTH => INIT_DEPTH, - USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, - IBUF_SECURE_MODE => IBUF_SECURE_MODE) + DEPTH => INIT_DEPTH, + USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, + SBUF_VERSION => SBUF_VERSION, + IBUF_SECURE_MODE => IBUF_SECURE_MODE + ) port map ( CLK => CLK, RESET => RESET, @@ -254,9 +250,11 @@ begin GEN_REPLY_IBUF : if REPLY_DEPTH > 0 generate REPLYIBUF : trb_net16_ibuf generic map ( - DEPTH => REPLY_DEPTH, - USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, - IBUF_SECURE_MODE => IBUF_SECURE_MODE) + DEPTH => REPLY_DEPTH, + USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, + SBUF_VERSION => SBUF_VERSION, + IBUF_SECURE_MODE => IBUF_SECURE_MODE + ) port map ( CLK => CLK, RESET => RESET, @@ -280,6 +278,10 @@ begin GEN_TERM_INIT_IBUF: if INIT_DEPTH=0 generate INITIBUF : trb_net16_term_ibuf + generic map( + SBUF_VERSION => SBUF_VERSION, + SECURE_MODE => IBUF_SECURE_MODE + ) port map ( CLK => CLK, RESET => RESET, @@ -303,6 +305,10 @@ begin GEN_TERM_REPLY_IBUF: if REPLY_DEPTH=0 generate REPLYIBUF : trb_net16_term_ibuf + generic map( + SBUF_VERSION => SBUF_VERSION, + SECURE_MODE => IBUF_SECURE_MODE + ) port map ( CLK => CLK, RESET => RESET, @@ -327,7 +333,9 @@ begin genINITOBUF1 : if INIT_CAN_SEND_DATA = 1 generate INITOBUF : trb_net16_obuf generic map ( - USE_ACKNOWLEDGE => USE_ACKNOWLEDGE + DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH, + USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, + SBUF_VERSION => SBUF_VERSION ) port map ( CLK => CLK, @@ -376,7 +384,9 @@ begin genREPLYOBUF1 : if REPLY_CAN_SEND_DATA = 1 generate REPLYOBUF : trb_net16_obuf generic map ( - USE_ACKNOWLEDGE => USE_ACKNOWLEDGE + DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH, + USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, + SBUF_VERSION => SBUF_VERSION ) port map ( CLK => CLK, @@ -422,29 +432,6 @@ begin end generate; --- REPLYOBUF : trb_net16_obuf --- generic map ( --- USE_ACKNOWLEDGE => USE_ACKNOWLEDGE --- ) --- port map ( --- CLK => CLK, --- RESET => RESET, --- CLK_EN => CLK_EN, --- MED_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT, --- MED_DATA_OUT => MED_REPLY_DATA_OUT, --- MED_PACKET_NUM_OUT => MED_REPLY_PACKET_NUM_OUT, --- MED_READ_IN => MED_REPLY_READ_IN, --- INT_DATAREADY_IN => INT_REPLY_DATAREADY_IN, --- INT_DATA_IN => INT_REPLY_DATA_IN, --- INT_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, --- INT_READ_OUT => INT_REPLY_READ_OUT, --- STAT_LOCKED(15 downto 0) => REPLYOBUF_stat_locked, --- CTRL_LOCKED(15 downto 0) => REPLYOBUF_ctrl_locked, --- STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer, --- CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer --- ); - - -- build the registers according to the wiki page STAT_INIT_BUFFER(8 downto 0) <= INITIBUF_stat_buffer(8 downto 0); STAT_INIT_BUFFER(11 downto 9) <= INITOBUF_stat_buffer(17 downto 15); diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd new file mode 100644 index 0000000..912c322 --- /dev/null +++ b/trb_net16_med_tlk.vhd @@ -0,0 +1,175 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +LIBRARY unisim; +USE UNISIM.VComponents.all; +library work; +use work.trb_net_std.all; + + +entity trb_net16_med_tlk is + port ( + RESET : in std_logic; + CLK : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + MED_DATAREADY_IN : in std_logic; + MED_READ_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (15 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (15 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + MED_ERROR_OUT : out std_logic_vector (2 downto 0); + STAT : out std_logic_vector (31 downto 0) + ); +end trb_net16_med_tlk; + +architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is + + component trb_net_fifo_16bit_bram_dualport + port ( + read_clock_in: IN std_logic; + write_clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + fifo_gsr_in: IN std_logic; --reset + write_data_in: IN std_logic_vector(17 downto 0); + read_data_out: OUT std_logic_vector(17 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + fifostatus_out: OUT std_logic_vector(3 downto 0) + ); + end component trb_net_fifo_16bit_bram_dualport; + + + signal fifo_din_a : std_logic_vector(17 downto 0); + signal fifo_dout_a : std_logic_vector(17 downto 0); + signal fifo_rd_en_a : std_logic; + signal fifo_empty_a : std_logic; + signal fifo_full_a : std_logic; + signal fifo_din_m : std_logic_vector(17 downto 0); + signal fifo_dout_m : std_logic_vector(17 downto 0); + signal fifo_rd_en_m : std_logic; + signal fifo_empty_m : std_logic; + signal fifo_full_m : std_logic; + + signal fifo_reset : std_logic; + signal fifo_status_a : std_logic_vector(3 downto 0); + signal fifo_status_m : std_logic_vector(3 downto 0); + signal last_fifo_rd_en_a, last_fifo_rd_en_m : std_logic; + signal buf_MED_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + +begin + + STAT(3 downto 0) <= fifo_status_a; + STAT(5 downto 4) <= fifo_empty_a & fifo_full_a; + STAT(7 downto 6) <= (others => '0'); + STAT(11 downto 8) <= fifo_status_m; + STAT(13 downto 12) <= fifo_empty_m & fifo_full_m; + STAT(31 downto 14) <= (others => '0'); + + TLK_TX_ER <= '0'; + TLK_ENABLE <= not RESET; + TLK_LCKREFN <= '1'; + TLK_PRBSEN <= '0'; + TLK_LOOPEN <= '0'; + + MED_READ_OUT <= not RESET; + +------------- +--Receiver +------------- + + FIFO_OPT_TO_MED: trb_net_fifo_16bit_bram_dualport + port map( + read_clock_in => CLK, + write_clock_in => TLK_RX_CLK, + read_enable_in => fifo_rd_en_a, + write_enable_in => TLK_RX_DV, + fifo_gsr_in => fifo_reset, + write_data_in => fifo_din_a, + read_data_out => fifo_dout_a, + full_out => fifo_full_a, + empty_out => fifo_empty_a, + fifostatus_out => fifo_status_a + ); + + fifo_din_a <= '0' & TLK_RX_ER & TLK_RXD; + fifo_rd_en_a <= not fifo_empty_a; + fifo_reset <= RESET; + MED_DATA_OUT <= fifo_dout_a(15 downto 0); + MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16); + MED_ERROR_OUT <= ERROR_OK when TLK_RX_ER = '0' else ERROR_NC; + MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_MED_PACKET_NUM_OUT <= "11"; + elsif fifo_rd_en_a = '1' then + buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_fifo_rd_en_a <= '0'; + else + last_fifo_rd_en_a <= fifo_rd_en_a; + end if; + end if; + end process; + + +------------- +--Sender +------------- + + FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport + port map( + read_clock_in => TLK_CLK, + write_clock_in => CLK, + read_enable_in => fifo_rd_en_m, + write_enable_in => MED_DATAREADY_IN, + fifo_gsr_in => fifo_reset, + write_data_in => fifo_din_m, + read_data_out => fifo_dout_m, + full_out => fifo_full_m, + empty_out => fifo_empty_m, + fifostatus_out => fifo_status_m + ); + + fifo_rd_en_m <= not TLK_RX_ER and not fifo_empty_m; + fifo_din_m <= "00" & MED_DATA_IN; + TLK_TXD <= fifo_dout_m(15 downto 0); + TLK_TX_EN <= last_fifo_rd_en_m; + + process(TLK_CLK) + begin + if rising_edge(TLK_CLK) then + if RESET = '1' then + last_fifo_rd_en_m <= '0'; + else + last_fifo_rd_en_m <= fifo_rd_en_m; + end if; + end if; + end process; + +end architecture; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 1d412a1..94db7e4 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -5,14 +5,16 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_obuf is generic ( - USE_ACKNOWLEDGE : integer range 0 to 1 := 1; - CAN_SEND_DATA : integer range 0 to 1 := 1; - DATA_COUNT_WIDTH : integer range 1 to 7 := 5 -- max used buffer size is 2**DATA_COUNT_WIDTH. + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + DATA_COUNT_WIDTH : integer range 1 to 7 := std_DATA_COUNT_WIDTH; + -- max used buffer size is 2**DATA_COUNT_WIDTH. + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION ); port( -- Misc @@ -20,20 +22,20 @@ entity trb_net16_obuf is RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector(1 downto 0); - MED_READ_IN: in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; -- Internal direction port - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector(1 downto 0); - INT_READ_OUT: out std_logic; + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; -- Status and control port - STAT_LOCKED: out std_logic_vector (15 downto 0); - CTRL_LOCKED: in std_logic_vector (15 downto 0); - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0) + STAT_LOCKED : out std_logic_vector (15 downto 0); + CTRL_LOCKED : in std_logic_vector (15 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0); + CTRL_BUFFER : in std_logic_vector (31 downto 0) ); end entity; @@ -41,8 +43,6 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is component trb_net16_sbuf is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; VERSION : integer := 0 ); port( @@ -54,12 +54,12 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is COMB_DATAREADY_IN: in std_logic; --comb logic provides data word COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle COMB_READ_IN: in std_logic; --comb logic IS reading - COMB_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in std_logic_vector(NUM_WIDTH-1 downto 0); + COMB_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT: out std_logic; - SYN_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out std_logic_vector(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); SYN_READ_IN: in std_logic; -- Status and control port STAT_BUFFER: out std_logic @@ -97,9 +97,7 @@ begin SBUF: trb_net16_sbuf generic map ( - DATA_WIDTH => 16, - NUM_WIDTH => 2, - VERSION => 0 + VERSION => SBUF_VERSION ) port map ( CLK => CLK, @@ -352,9 +350,4 @@ begin end process; end generate; - - - - - end architecture; \ No newline at end of file diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd index 31f0ce4..32d2671 100644 --- a/trb_net16_obuf_nodata.vhd +++ b/trb_net16_obuf_nodata.vhd @@ -2,6 +2,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_obuf_nodata is @@ -11,15 +12,15 @@ entity trb_net16_obuf_nodata is RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_PACKET_NUM_OUT:out std_logic_vector(1 downto 0); - MED_READ_IN: in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; --STAT - STAT_LOCKED: out std_logic_vector (15 downto 0); - CTRL_LOCKED: in std_logic_vector (15 downto 0); - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0) + STAT_LOCKED : out std_logic_vector (15 downto 0); + CTRL_LOCKED : in std_logic_vector (15 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0); + CTRL_BUFFER : in std_logic_vector (31 downto 0) ); end entity; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index d39f307..6abf310 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -2,6 +2,7 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; @@ -15,7 +16,6 @@ use work.trb_net_std.all; entity trb_net16_regIO is generic ( - MY_ADDRESS : std_logic_vector(15 downto 0) := x"F001"; REGISTER_WIDTH : integer range 32 to 32 := 32; ADDRESS_WIDTH : integer range 8 to 16 := 16; ADDRESS_USED_WIDTH : integer range 1 to 5 := 4; @@ -36,9 +36,10 @@ entity trb_net16_regIO is RESET : in std_logic; CLK_EN : in std_logic; + MY_ADDRESS : in std_logic_vector (15 downto 0); -- Port to API - API_DATA_OUT : out std_logic_vector (15 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); API_WRITE_OUT : out std_logic; API_FIFO_FULL_IN : in std_logic; API_SHORT_TRANSFER_OUT : out std_logic; @@ -47,8 +48,8 @@ entity trb_net16_regIO is API_SEND_OUT : out std_logic; API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); -- Receiver port - API_DATA_IN : in std_logic_vector (15 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); API_TYP_IN : in std_logic_vector (2 downto 0); API_DATAREADY_IN : in std_logic; API_READ_OUT : out std_logic; @@ -77,10 +78,12 @@ end entity; architecture trb_net16_regIO_arch of trb_net16_regIO is component trb_net_pattern_gen is - generic (MULT_WIDTH : integer := ADDRESS_USED_WIDTH-1); + generic ( + WIDTH : integer := ADDRESS_USED_WIDTH-1 + ); port( - INPUT_IN : in STD_LOGIC_VECTOR (ADDRESS_USED_WIDTH-2 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**(ADDRESS_USED_WIDTH-1)-1 downto 0) + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) ); end component; @@ -116,8 +119,11 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is begin - pattern_gen_inst : trb_net_pattern_gen port map(address(ADDRESS_USED_WIDTH-2 downto 0), reg_enable_pattern); - + pattern_gen_inst : trb_net_pattern_gen + port map( + INPUT_IN => address(ADDRESS_USED_WIDTH-2 downto 0), + RESULT_OUT => reg_enable_pattern + ); fsm : process(current_state, diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd index 60e944e..2663850 100644 --- a/trb_net16_sbuf.vhd +++ b/trb_net16_sbuf.vhd @@ -20,12 +20,12 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; +use work.trb_net_cfg.all; entity trb_net16_sbuf is generic ( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; VERSION : integer := 0 ); port( @@ -37,12 +37,12 @@ entity trb_net16_sbuf is COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); SYN_READ_IN : in STD_LOGIC; -- Status and control port STAT_BUFFER : out STD_LOGIC @@ -52,8 +52,9 @@ end entity; architecture trb_net16_sbuf_arch of trb_net16_sbuf is component trb_net_sbuf is - generic (DATA_WIDTH : integer := DATA_WIDTH + NUM_WIDTH; - VERSION: integer := VERSION); --VERSION); + generic ( + DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; + VERSION: integer := VERSION); port( -- Misc CLK : in std_logic; @@ -78,13 +79,13 @@ component trb_net_sbuf is ); end component; -signal comb_in, syn_out : std_logic_vector (DATA_WIDTH + NUM_WIDTH - 1 downto 0); +signal comb_in, syn_out : std_logic_vector (c_DATA_WIDTH + c_NUM_WIDTH - 1 downto 0); begin -comb_in(DATA_WIDTH - 1 downto 0) <= COMB_DATA_IN; -comb_in(DATA_WIDTH + NUM_WIDTH -1 downto DATA_WIDTH) <= COMB_PACKET_NUM_IN; -SYN_DATA_OUT <= syn_out(DATA_WIDTH - 1 downto 0); -SYN_PACKET_NUM_OUT <= syn_out(DATA_WIDTH + NUM_WIDTH - 1 downto DATA_WIDTH); +comb_in(c_DATA_WIDTH - 1 downto 0) <= COMB_DATA_IN; +comb_in(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= COMB_PACKET_NUM_IN; +SYN_DATA_OUT <= syn_out(c_DATA_WIDTH - 1 downto 0); +SYN_PACKET_NUM_OUT <= syn_out(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); sbuf: trb_net_sbuf port map( diff --git a/trb_net16_term.vhd b/trb_net16_term.vhd index b52b413..57bbe04 100644 --- a/trb_net16_term.vhd +++ b/trb_net16_term.vhd @@ -2,19 +2,22 @@ -- for a description see HADES wiki -- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetTerm ---can only be used in combination with term_ibuf -> no check for packet type! +-- can only be used in combination with term_ibuf -> no check for packet type! LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_term is generic ( - SECURE_MODE : integer range 0 to 1 := 0 + USE_APL_PORT : integer range 0 to 1 := 0; + --even when 0, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE --if secure_mode is not used, apl must provide error pattern and dtype until --next trigger comes in. In secure mode these need to be available while relase_trg is high ); @@ -25,13 +28,13 @@ entity trb_net16_term is CLK_EN : in std_logic; INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT: out std_logic; -- "mini" APL, just to see the triggers coming in @@ -64,12 +67,21 @@ architecture trb_net16_term_arch of trb_net16_term is begin - + g1: if USE_APL_PORT = 1 generate APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; APL_GOT_TRM <= reg_APL_GOT_TRM; INT_READ_OUT <= not send_trm and not reg_APL_GOT_TRM; + end generate; + g1n: if USE_APL_PORT = 0 generate + APL_DTYPE_OUT <= (others => '0'); + APL_ERROR_PATTERN_OUT <= (others => '0'); + APL_SEQNR_OUT <= (others => '0'); + APL_GOT_TRM <= '0'; + INT_READ_OUT <= not send_trm; + end generate; + process(RESET, reg_APL_DTYPE_OUT, reg_APL_SEQNR_OUT, reg_APL_GOT_TRM, current_packet_type, INT_PACKET_NUM_IN, INT_DATA_IN, APL_RELEASE_TRM, send_trm, @@ -77,21 +89,24 @@ begin buf_APL_DTYPE_IN, buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT) begin --next_APL_ERROR_PATTERN_OUT <= reg_APL_ERROR_PATTERN_OUT; - next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; - next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; - next_APL_GOT_TRM <= reg_APL_GOT_TRM; + if USE_APL_PORT = 1 then + next_APL_DTYPE_OUT <= reg_APL_DTYPE_OUT; + next_APL_SEQNR_OUT <= reg_APL_SEQNR_OUT; + next_APL_GOT_TRM <= reg_APL_GOT_TRM; + if saved_packet_type = TYPE_TRM then + if INT_PACKET_NUM_IN = "11" then + next_APL_DTYPE_OUT <= INT_DATA_IN(3 downto 0); + next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4); + next_APL_GOT_TRM <= '1'; + end if; + end if; + end if; next_send_trm <= '0'; next_INT_DATAREADY_OUT <= '0'; next_INT_DATA_OUT <= buf_INT_DATA_OUT; next_transfer_counter <= transfer_counter; - if saved_packet_type = TYPE_TRM then - if INT_PACKET_NUM_IN = "11" then - next_APL_DTYPE_OUT <= INT_DATA_IN(3 downto 0); - next_APL_SEQNR_OUT <= INT_DATA_IN(11 downto 4); - next_APL_GOT_TRM <= '1'; - end if; - end if; - if (reg_APL_GOT_TRM = '1' and APL_RELEASE_TRM = '1') or send_trm = '1' then + + if (reg_APL_GOT_TRM = '1' and APL_RELEASE_TRM = '1') or send_trm = '1' or USE_APL_PORT = 0 then --next_transfer_counter is used for transmission! if transfer_counter = "10" and INT_READ_IN = '1' then next_send_trm <= '0'; @@ -113,7 +128,7 @@ begin next_INT_DATA_OUT(11 downto 4) <= reg_APL_SEQNR_OUT; end if; end if; - if APL_RELEASE_TRM = '1' and reg_APL_GOT_TRM = '1' then + if APL_RELEASE_TRM = '1' and reg_APL_GOT_TRM = '1' and USE_APL_PORT = 0 then next_APL_GOT_TRM <= '0'; end if; end process; @@ -135,6 +150,7 @@ begin SECURE_GEN2: if SECURE_MODE = 0 generate buf_APL_ERROR_PATTERN_IN <= APL_ERROR_PATTERN_IN; end generate; + --count packets REG_TRANSFER_COUNTER : process(CLK) @@ -176,43 +192,53 @@ begin end if; end process; - CLK_REG: process(CLK) + REG_send_trm: process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - reg_APL_GOT_TRM <= '0'; - reg_APL_DTYPE_OUT <= (others => '0'); - reg_APL_SEQNR_OUT <= (others => '0'); send_trm <= '0'; + reg_APL_SEQNR_OUT <= (others => '0'); else - reg_APL_GOT_TRM <= next_APL_GOT_TRM; - reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT; - reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT; send_trm <= next_send_trm; + reg_APL_SEQNR_OUT <= next_APL_SEQNR_OUT; end if; end if; - end process; + end process; + + g2: if USE_APL_PORT = 1 generate + CLK_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_APL_GOT_TRM <= '0'; + reg_APL_DTYPE_OUT <= (others => '0'); + else + reg_APL_GOT_TRM <= next_APL_GOT_TRM; + reg_APL_DTYPE_OUT <= next_APL_DTYPE_OUT; + end if; + end if; + end process; - ERROROUT1_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= (others => '0'); - elsif INT_PACKET_NUM_IN = "01" then - reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN; + ERROROUT1_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= (others => '0'); + elsif INT_PACKET_NUM_IN = "01" then + reg_APL_ERROR_PATTERN_OUT(31 downto 16) <= INT_DATA_IN; + end if; end if; - end if; - end process; - ERROROUT2_REG: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= (others => '0'); - elsif INT_PACKET_NUM_IN = "10" then - reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN; + end process; + ERROROUT2_REG: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= (others => '0'); + elsif INT_PACKET_NUM_IN = "10" then + reg_APL_ERROR_PATTERN_OUT(15 downto 0) <= INT_DATA_IN; + end if; end if; - end if; - end process; - + end process; + end generate; end architecture; diff --git a/trb_net16_term_buf.vhd b/trb_net16_term_buf.vhd index d33a14a..dc04115 100644 --- a/trb_net16_term_buf.vhd +++ b/trb_net16_term_buf.vhd @@ -1,12 +1,11 @@ --- this is just a terminator, which auto-answers requests. Answer is a TRM only. - --- only to be used on unused channels +-- only to be used on unused channels - every transfer is terminated asap. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_ARITH.ALL; USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; @@ -18,23 +17,23 @@ entity trb_net16_term_buf is CLK_EN : in std_logic; MED_INIT_DATAREADY_OUT: out std_logic; - MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_IN: in std_logic; MED_INIT_DATAREADY_IN: in std_logic; - MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_INIT_READ_OUT: out std_logic; MED_REPLY_DATAREADY_OUT: out std_logic; - MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0); + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_IN: in std_logic; MED_REPLY_DATAREADY_IN: in std_logic; - MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word - MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0); + MED_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_REPLY_READ_OUT: out std_logic ); end entity; @@ -56,9 +55,9 @@ architecture trb_net16_term_buf_arch of trb_net16_term_buf is signal buf_MED_REPLY_DATAREADY_OUT, next_MED_REPLY_DATAREADY_OUT : std_logic; signal buf_MED_REPLY_DATA_OUT, next_MED_REPLY_DATA_OUT : std_logic_vector(15 downto 0); signal buf_MED_REPLY_PACKET_NUM_OUT : std_logic_vector(1 downto 0); - signal send_REPLY_ack, send_REPLY_trm : std_logic; - signal next_send_REPLY_ack, next_send_REPLY_trm : std_logic; - signal sent_REPLY_ack, sent_REPLY_trm : std_logic; + signal send_REPLY_trm : std_logic; + signal next_send_REPLY_trm : std_logic; + signal sent_REPLY_trm : std_logic; signal sending_REPLY_ACK, next_sending_REPLY_ACK : std_logic; begin @@ -67,19 +66,19 @@ begin process(MED_INIT_DATAREADY_IN, MED_INIT_PACKET_NUM_IN, MED_INIT_DATA_IN, MED_REPLY_DATAREADY_IN, MED_REPLY_PACKET_NUM_IN, MED_REPLY_DATA_IN, - send_INIT_ack, send_REPLY_ack, send_REPLY_trm, sending_REPLY_ACK, + send_INIT_ack, send_REPLY_trm, REPLY_transfer_counter, REPLY_saved_packet_type, MED_INIT_READ_IN, INIT_SEQNR, INIT_transfer_counter, INIT_saved_packet_type, MED_REPLY_READ_IN, buf_MED_INIT_DATA_OUT, buf_MED_REPLY_DATA_OUT, buf_MED_INIT_DATAREADY_OUT, buf_MED_REPLY_DATAREADY_OUT) begin sent_INIT_ack <= '0'; - sent_REPLY_ack <= '0'; +-- sent_REPLY_ack <= '0'; sent_REPLY_trm <= '0'; next_send_INIT_ack <= send_INIT_ack; - next_send_REPLY_ack <= send_REPLY_ack; +-- next_send_REPLY_ack <= send_REPLY_ack; next_send_REPLY_trm <= send_REPLY_trm; - next_sending_REPLY_ACK <= sending_REPLY_ACK; +-- next_sending_REPLY_ACK <= sending_REPLY_ACK; next_MED_INIT_DATA_OUT <= buf_MED_INIT_DATA_OUT; next_MED_INIT_DATAREADY_OUT <= '0'; next_MED_REPLY_DATA_OUT <= buf_MED_REPLY_DATA_OUT; diff --git a/trb_net16_term_ibuf.vhd b/trb_net16_term_ibuf.vhd index 0df636d..49a1a44 100644 --- a/trb_net16_term_ibuf.vhd +++ b/trb_net16_term_ibuf.vhd @@ -1,6 +1,4 @@ --- for a description see HADES wiki --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF --- This has in principle the same output ports, but internally +-- term_ibuf can be used instead of ibuf, if only short transfers are received. -- it keeps only the TRM words -- EOB are killed -- ACK are regognized @@ -11,14 +9,14 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net16_term_ibuf is generic( - DATA_WIDTH : integer := 16; - NUM_WIDTH : integer := 2; - VERSION : integer range 0 to 1 := 0 + SECURE_MODE : integer range 0 to 1 := std_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION ); port( -- Misc @@ -27,15 +25,15 @@ entity trb_net16_term_ibuf is CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read) - MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN :in std_logic_vector(NUM_WIDTH-1 downto 0); + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); MED_READ_OUT: out std_logic; -- buffer reads a word from media MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits -- Internal direction port INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT:out std_logic_vector(NUM_WIDTH-1 downto 0); + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); INT_READ_IN: in std_logic; INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits -- Status and control port @@ -49,9 +47,7 @@ architecture trb_net16_term_ibuf_arch of trb_net16_term_ibuf is component trb_net16_sbuf is generic ( - DATA_WIDTH : integer := DATA_WIDTH; - NUM_WIDTH : integer := NUM_WIDTH; - VERSION : integer := VERSION + VERSION : integer := SBUF_VERSION ); port( -- Misc @@ -62,12 +58,12 @@ architecture trb_net16_term_ibuf_arch of trb_net16_term_ibuf is COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0); + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); SYN_READ_IN : in STD_LOGIC; -- Status and control port STAT_BUFFER : out STD_LOGIC @@ -79,8 +75,8 @@ architecture trb_net16_term_ibuf_arch of trb_net16_term_ibuf is signal got_eob_out, reg_eob_out: std_logic; signal sbuf_free, comb_next_read: std_logic; signal tmp_INT_DATAREADY_OUT: std_logic; - signal tmp_INT_DATA_OUT: std_logic_vector(DATA_WIDTH-1 downto 0); - signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(NUM_WIDTH-1 downto 0); + signal tmp_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_LOCKED_ERROR, GOT_UNDEFINED_ERROR); signal current_error_state, next_error_state : ERROR_STATE; signal next_rec_buffer_size_out, current_rec_buffer_size_out : std_logic_vector(3 downto 0); @@ -170,6 +166,9 @@ begin SBUF: trb_net16_sbuf + generic map( + VERSION => SBUF_VERSION + ) port map ( CLK => CLK, RESET => RESET, diff --git a/trb_net_dummy_fifo.vhd b/trb_net_dummy_fifo.vhd index 22bac51..6f8a20a 100644 --- a/trb_net_dummy_fifo.vhd +++ b/trb_net_dummy_fifo.vhd @@ -1,31 +1,28 @@ --- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo library ieee; - use ieee.std_logic_1164.all; - USE ieee.std_logic_signed.ALL; - USE ieee.std_logic_arith.ALL; - +library work; +use work.trb_net_std.all; entity trb_net_dummy_fifo is - - generic (WIDTH : integer := 51); - - port (CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); + generic ( + WIDTH : integer := 18 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); end trb_net_dummy_fifo; diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd index 83e8243..e30c2c9 100644 --- a/trb_net_fifo.vhd +++ b/trb_net_fifo.vhd @@ -1,34 +1,34 @@ -- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo library ieee; - use ieee.std_logic_1164.all; - USE ieee.std_logic_signed.ALL; - USE ieee.std_logic_arith.ALL; - +library work; +use work.trb_net_std.all; entity trb_net_fifo is - generic (WIDTH : integer := 18; -- FIFO word width - DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1) - FORCE_LUT : integer range 0 to 1 := 0); --don't allow use of BlockRAM - - port (CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - --output data MUST BE 0 if no data is available - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); + generic ( + WIDTH : integer := 18; -- FIFO word width + DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1) + FORCE_LUT : integer range 0 to 1 := 0 --don't allow use of BlockRAM + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data + --output data MUST BE 0 if no data is available + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); end trb_net_fifo; diff --git a/trb_net_fifo_16bit_bram_dualport.vhd b/trb_net_fifo_16bit_bram_dualport.vhd index e0797cf..e9e14d2 100644 --- a/trb_net_fifo_16bit_bram_dualport.vhd +++ b/trb_net_fifo_16bit_bram_dualport.vhd @@ -9,15 +9,16 @@ use UNISIM.VComponents.all; entity trb_net_fifo_16bit_bram_dualport is - port (read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0) --counter for 1/16th of fifo - ); + port ( + read_clock_in: IN std_logic; + write_clock_in: IN std_logic; + read_enable_in: IN std_logic; + write_enable_in: IN std_logic; + fifo_gsr_in: IN std_logic; + write_data_in: IN std_logic_vector(17 downto 0); + read_data_out: OUT std_logic_vector(17 downto 0); + full_out: OUT std_logic; + empty_out: OUT std_logic; + fifostatus_out: OUT std_logic_vector(3 downto 0) --counter for 1/16th of fifo + ); end entity trb_net_fifo_16bit_bram_dualport; \ No newline at end of file diff --git a/trb_net_med_8bit_fast.vhd b/trb_net_med_8bit_fast.vhd index 1eb18fe..7f73599 100644 --- a/trb_net_med_8bit_fast.vhd +++ b/trb_net_med_8bit_fast.vhd @@ -59,6 +59,7 @@ USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use UNISIM.VComponents.all; +library work; use work.trb_net_std.all; --Entity decalaration for clock generator diff --git a/trb_net_med_8bit_slow.vhd b/trb_net_med_8bit_slow.vhd index 3fb31d0..759d31f 100644 --- a/trb_net_med_8bit_slow.vhd +++ b/trb_net_med_8bit_slow.vhd @@ -4,20 +4,18 @@ --are for debugging -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net_med_8bit_slow is -generic( - TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only! - ); - - + generic( + TRANSMISSION_CLOCK_DIVIDER: integer range 2 to 62 := 2 --even values only! + ); port( -- Misc CLK : in std_logic; @@ -28,14 +26,14 @@ generic( -- 1st part: from the medium to the internal logic (trbnet) INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media --and ready to be read out (the IOBUF MUST read) - INT_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - INT_PACKET_NUM_OUT:out STD_LOGIC_VECTOR (1 downto 0); + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT:out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); INT_READ_IN: in STD_LOGIC; INT_ERROR_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Status bits -- 2nd part: from the internal logic (trbnet) to the medium INT_DATAREADY_IN: in STD_LOGIC; -- Data word is offered for the Media - INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); INT_READ_OUT: out STD_LOGIC; -- offered word is read INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits -- (end do not change this interface!!!) @@ -59,7 +57,6 @@ generic( CTRL: in STD_LOGIC_VECTOR (31 downto 0) --CTRL(24..31) -> lvds-data(63 downto 56) via lvds --once for each packet - ); end entity trb_net_med_8bit_slow; @@ -103,207 +100,210 @@ architecture trb_net_med_8bit_slow_arch of trb_net_med_8bit_slow is signal transmission_running, next_transmission_running : std_logic; signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0); begin -INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; -INT_DATA_OUT <= buf_INT_DATA_OUT; -INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; -INT_ERROR_OUT <= "000";--my_error; -INT_READ_OUT <= buf_INT_READ_OUT; -STAT <= buf_STAT; + INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; + INT_DATA_OUT <= buf_INT_DATA_OUT; + INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; + INT_ERROR_OUT <= "000";--my_error; + INT_READ_OUT <= buf_INT_READ_OUT; + STAT <= buf_STAT; -MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT; ---MED_DATA_OUT(10 downto 8) <= recv_counter; + MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT; + --MED_DATA_OUT(10 downto 8) <= recv_counter; --- MED_DATA_OUT(8) <= buf_INT_DATAREADY_OUT; --- MED_DATA_OUT(9) <= INT_READ_IN; --- MED_DATA_OUT(10)<= buf_INT_PACKET_NUM_OUT(0); -MED_DATA_OUT(10 downto 8) <= buf_INT_DATA_OUT(2 downto 0); + -- MED_DATA_OUT(8) <= buf_INT_DATAREADY_OUT; + -- MED_DATA_OUT(9) <= INT_READ_IN; + -- MED_DATA_OUT(10)<= buf_INT_PACKET_NUM_OUT(0); + MED_DATA_OUT(10 downto 8) <= buf_INT_DATA_OUT(2 downto 0); -MED_DATA_OUT(11) <= not reset; -MED_DATA_OUT(12) <= buf_MED_FIRST_PACKET_OUT; -MED_DATA_OUT(13) <= buf_MED_TRANSMISSION_CLK_OUT; -MED_DATA_OUT(14) <= buf_MED_CARRIER_OUT; -MED_DATA_OUT(15) <= buf_MED_PARITY_OUT; + MED_DATA_OUT(11) <= not reset; + MED_DATA_OUT(12) <= buf_MED_FIRST_PACKET_OUT; + MED_DATA_OUT(13) <= buf_MED_TRANSMISSION_CLK_OUT; + MED_DATA_OUT(14) <= buf_MED_CARRIER_OUT; + MED_DATA_OUT(15) <= buf_MED_PARITY_OUT; ---TODO: --------------------------------- -fatal_error <= '0'; + --TODO: + -------------------------------- + fatal_error <= '0'; ---CTRL register --------------------------------- -CTRL_reg: process (CLK,RESET) - begin - if RESET = '1' then - buf_CTRL <= (others => '0'); - elsif rising_edge(CLK) then - buf_CTRL <= CTRL; - else - buf_CTRL <= buf_CTRL; - end if; - end process; + --CTRL register + -------------------------------- + CTRL_reg: process (CLK,RESET) + begin + if RESET = '1' then + buf_CTRL <= (others => '0'); + elsif rising_edge(CLK) then + buf_CTRL <= CTRL; + else + buf_CTRL <= buf_CTRL; + end if; + end process; ---My error bits --------------------------------- -gen_my_error: process(media_not_connected,fatal_error, MED_DATA_IN) - begin - if media_not_connected = '1' or MED_DATA_IN(11) = '0' then - next_my_error <= ERROR_NC; - elsif fatal_error = '1' then - next_my_error <= "011"; - else - next_my_error <= "000"; - end if; - end process; + --My error bits + -------------------------------- + gen_my_error: process(media_not_connected,fatal_error, MED_DATA_IN) + begin + if media_not_connected = '1' or MED_DATA_IN(11) = '0' then + next_my_error <= ERROR_NC; + elsif fatal_error = '1' then + next_my_error <= "011"; + else + next_my_error <= "000"; + end if; + end process; -reg_my_error: process(CLK,RESET) - begin - if rising_edge(CLK) then + reg_my_error: process(CLK,RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + my_error <= "000"; + else + my_error <= next_my_error; + end if; + end if; + end process; + + + --Transmission clock generator + -------------------------------- + trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT) + begin + if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then + next_transmission_clk_Counter <= (others => '0'); + next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT; + else + next_transmission_clk_Counter <= transmission_clk_Counter + 1; + next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT; + end if; + end process; + + + trans_clk_counter_reg: process (CLK,RESET) + begin if RESET = '1' then - my_error <= "000"; + transmission_clk_Counter <= (others => '0'); + buf_MED_TRANSMISSION_CLK_OUT <= '0'; + elsif rising_edge(CLK) then + transmission_clk_Counter <= next_transmission_clk_Counter; + buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK; else - my_error <= next_my_error; + transmission_clk_Counter <= transmission_clk_Counter; + buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; end if; - end if; - end process; - + end process; ---Transmission clock generator --------------------------------- -trans_clk_counter: process (transmission_clk_Counter, buf_MED_TRANSMISSION_CLK_OUT) - begin - if transmission_clk_Counter = (TRANSMISSION_CLOCK_DIVIDER/2) - 1 then - next_transmission_clk_Counter <= (others => '0'); - next_TRANSMISSION_CLK <= not buf_MED_TRANSMISSION_CLK_OUT; - else - next_transmission_clk_Counter <= transmission_clk_Counter + 1; - next_TRANSMISSION_CLK <= buf_MED_TRANSMISSION_CLK_OUT; - end if; - end process; -trans_clk_counter_reg: process (CLK,RESET) - begin - if RESET = '1' then - transmission_clk_Counter <= (others => '0'); - buf_MED_TRANSMISSION_CLK_OUT <= '0'; - elsif rising_edge(CLK) then - transmission_clk_Counter <= next_transmission_clk_Counter; - buf_MED_TRANSMISSION_CLK_OUT <= next_TRANSMISSION_CLK; - else - transmission_clk_Counter <= transmission_clk_Counter; - buf_MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT; - end if; - end process; + --Transmission Clock detection + -------------------------------- + trans_clk_reg: process (RESET,CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_TRCLK <= '0'; + this_TRCLK <= '0'; + CLK_counter <= (others => '0'); + media_not_connected <= '0'; + else + last_TRCLK <= this_TRCLK; + this_TRCLK <= reg_MED_TRANSMISSION_CLK_IN; + CLK_counter <= next_CLK_counter; + media_not_connected <= next_media_not_connected; + end if; + end if; + end process; ---Transmission Clock detection --------------------------------- -trans_clk_reg: process (RESET,CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - last_TRCLK <= '0'; - this_TRCLK <= '0'; - CLK_counter <= (others => '0'); - media_not_connected <= '0'; + transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter, + buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, + buf_MED_PARITY_OUT, buf_CTRL) + begin + next_media_not_connected <= '0'; + if last_TRCLK = '0' and this_TRCLK = '1' then + next_CLK_counter <= (others => '0'); + elsif CLK_counter = 255 then + next_media_not_connected <= '1'; + next_CLK_counter <= CLK_counter; else - last_TRCLK <= this_TRCLK; - this_TRCLK <= reg_MED_TRANSMISSION_CLK_IN; - CLK_counter <= next_CLK_counter; - media_not_connected <= next_media_not_connected; + next_CLK_counter <= CLK_counter + 1; end if; - end if; - end process; + end process; + -transCLK_counter: process (this_TRCLK, last_TRCLK, CLK_counter, - buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, - buf_MED_PARITY_OUT, buf_CTRL) + --INT to MED direction + -------------------------------- + INT2MED_fsm: process(buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_INT_DATA_IN, + transmission_running, buf_MED_FIRST_PACKET_OUT, next_TRANSMISSION_CLK, + buf_MED_TRANSMISSION_CLK_OUT, INT_DATAREADY_IN, INT_DATA_IN, + buf_INT_READ_OUT, INT_PACKET_NUM_IN) begin - next_media_not_connected <= '0'; - if last_TRCLK = '0' and this_TRCLK = '1' then - next_CLK_counter <= (others => '0'); - elsif CLK_counter = 255 then - next_media_not_connected <= '1'; - next_CLK_counter <= CLK_counter; - else - next_CLK_counter <= CLK_counter + 1; - end if; + next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT; + next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; + next_MED_PARITY_OUT <= buf_MED_PARITY_OUT; + next_buf_INT_DATA_IN <= buf_INT_DATA_IN; + next_buf_INT_READ_OUT <= buf_INT_READ_OUT; + next_transmission_running <= transmission_running; + next_MED_FIRST_PACKET_OUT <= buf_MED_FIRST_PACKET_OUT; + buf_INT_READ_OUT <= '0'; + if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' and transmission_running = '0' then + next_MED_CARRIER_OUT <= '0'; + end if; + if(INT_DATAREADY_IN = '1' and transmission_running = '0') then + if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then + next_buf_MED_DATA_OUT <= INT_DATA_IN(15 downto 8); + next_buf_INT_DATA_IN <= INT_DATA_IN(7 downto 0); + next_MED_CARRIER_OUT <= '1'; + next_MED_PARITY_OUT <= xor_all(INT_DATA_IN(15 downto 8)); + next_transmission_running <= '1'; + buf_INT_READ_OUT <= '1'; + if INT_PACKET_NUM_IN = "00" then + next_MED_FIRST_PACKET_OUT <= '1'; + else + next_MED_FIRST_PACKET_OUT <= '0'; + end if; + end if; + elsif transmission_running = '1' then + if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then + next_buf_MED_DATA_OUT <= buf_INT_DATA_IN; + next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN); + next_transmission_running <= '0'; + end if; + end if; end process; - - ---INT to MED direction --------------------------------- -INT2MED_fsm: process(buf_MED_DATA_OUT, buf_MED_CARRIER_OUT, buf_MED_PARITY_OUT, buf_INT_DATA_IN, - transmission_running, buf_MED_FIRST_PACKET_OUT, next_TRANSMISSION_CLK, - buf_MED_TRANSMISSION_CLK_OUT, INT_DATAREADY_IN, INT_DATA_IN, - buf_INT_READ_OUT, INT_PACKET_NUM_IN) -begin - next_buf_MED_DATA_OUT <= buf_MED_DATA_OUT; - next_MED_CARRIER_OUT <= buf_MED_CARRIER_OUT; - next_MED_PARITY_OUT <= buf_MED_PARITY_OUT; - next_buf_INT_DATA_IN <= buf_INT_DATA_IN; - next_buf_INT_READ_OUT <= buf_INT_READ_OUT; - next_transmission_running <= transmission_running; - next_MED_FIRST_PACKET_OUT <= buf_MED_FIRST_PACKET_OUT; - buf_INT_READ_OUT <= '0'; - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' and transmission_running = '0' then - next_MED_CARRIER_OUT <= '0'; - end if; - if(INT_DATAREADY_IN = '1' and transmission_running = '0') then - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT <= INT_DATA_IN(15 downto 8); - next_buf_INT_DATA_IN <= INT_DATA_IN(7 downto 0); - next_MED_CARRIER_OUT <= '1'; - next_MED_PARITY_OUT <= xor_all(INT_DATA_IN(15 downto 8)); - next_transmission_running <= '1'; - buf_INT_READ_OUT <= '1'; - if INT_PACKET_NUM_IN = "00" then - next_MED_FIRST_PACKET_OUT <= '1'; + INT2MED_fsm_reg: process(CLK,RESET) + begin + if rising_edge(CLK) then + if RESET='1' then + buf_MED_DATA_OUT <= (others => '0'); + buf_INT_DATA_IN <= (others => '0'); + buf_MED_CARRIER_OUT <= '0'; + buf_MED_PARITY_OUT <= '0'; + buf_MED_FIRST_PACKET_OUT <= '0'; + transmission_running <= '0'; else - next_MED_FIRST_PACKET_OUT <= '0'; + buf_INT_DATA_IN <= next_buf_INT_DATA_IN; + buf_MED_DATA_OUT <= next_buf_MED_DATA_OUT; + buf_MED_FIRST_PACKET_OUT <= next_MED_FIRST_PACKET_OUT; + buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT; + buf_MED_PARITY_OUT <= next_MED_PARITY_OUT; + transmission_running <= next_transmission_running; end if; end if; - elsif transmission_running = '1' then - if next_TRANSMISSION_CLK = '0' and buf_MED_TRANSMISSION_CLK_OUT = '1' then - next_buf_MED_DATA_OUT <= buf_INT_DATA_IN; - next_MED_PARITY_OUT <= xor_all(buf_INT_DATA_IN); - next_transmission_running <= '0'; - end if; - end if; -end process; + end process; + -INT2MED_fsm_reg: process(CLK,RESET) - begin - if rising_edge(CLK) then - if RESET='1' then - buf_MED_DATA_OUT <= (others => '0'); - buf_INT_DATA_IN <= (others => '0'); - buf_MED_CARRIER_OUT <= '0'; - buf_MED_PARITY_OUT <= '0'; - buf_MED_FIRST_PACKET_OUT <= '0'; - transmission_running <= '0'; - else - buf_INT_DATA_IN <= next_buf_INT_DATA_IN; - buf_MED_DATA_OUT <= next_buf_MED_DATA_OUT; - buf_MED_FIRST_PACKET_OUT <= next_MED_FIRST_PACKET_OUT; - buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT; - buf_MED_PARITY_OUT <= next_MED_PARITY_OUT; - transmission_running <= next_transmission_running; - end if; - end if; - end process; @@ -316,88 +316,84 @@ INT2MED_fsm_reg: process(CLK,RESET) + --MED to INT direction + -------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + recv_counter <= "111"; + elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then + recv_counter <= recv_counter + 1; + end if; + end if; + end process; ---MED to INT direction --------------------------------- - process(CLK) + MED2INT_fsm: process(buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT, buf_MED_DATA_IN, last_MED_TRANSMISSION_CLK_IN, + reg_MED_TRANSMISSION_CLK_IN, reg_MED_DATA_IN, recv_counter, INT_READ_IN, reg_MED_CARRIER_IN, + buf_INT_PACKET_NUM_OUT) begin - if rising_edge(CLK) then - if RESET = '1' then - recv_counter <= "111"; - elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then - recv_counter <= recv_counter + 1; + next_INT_DATA_OUT <= buf_INT_DATA_OUT; + next_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; + next_buf_MED_DATA_IN <= buf_MED_DATA_IN; + next_INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; + + if reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then + if recv_counter(0) = '1' then + next_buf_MED_DATA_IN <= reg_MED_DATA_IN; + else + next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN; + next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN; + next_INT_PACKET_NUM_OUT <= recv_counter(2 downto 1); + next_INT_DATAREADY_OUT <= '1'; end if; end if; - end process; - - - -MED2INT_fsm: process(buf_INT_DATA_OUT, buf_INT_DATAREADY_OUT, buf_MED_DATA_IN, last_MED_TRANSMISSION_CLK_IN, - reg_MED_TRANSMISSION_CLK_IN, reg_MED_DATA_IN, recv_counter, INT_READ_IN, reg_MED_CARRIER_IN, - buf_INT_PACKET_NUM_OUT) - begin - next_INT_DATA_OUT <= buf_INT_DATA_OUT; - next_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT; - next_buf_MED_DATA_IN <= buf_MED_DATA_IN; - next_INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT; - - if reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then - if recv_counter(0) = '1' then - next_buf_MED_DATA_IN <= reg_MED_DATA_IN; - else - next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN; - next_INT_DATA_OUT(15 downto 8) <= buf_MED_DATA_IN; - next_INT_PACKET_NUM_OUT <= recv_counter(2 downto 1); - next_INT_DATAREADY_OUT <= '1'; + if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then + next_INT_DATAREADY_OUT <= '0'; end if; - end if; - if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then - next_INT_DATAREADY_OUT <= '0'; - end if; - end process; + end process; -MED2INT_fsm_reg: process(CLK) - begin - if rising_edge(CLK) then - if RESET='1' then - buf_INT_DATAREADY_OUT <= '0'; - buf_INT_DATA_OUT <= (others => '0'); - last_MED_TRANSMISSION_CLK_IN <= '1'; - buf_MED_DATA_IN <= (others => '0'); - buf_INT_PACKET_NUM_OUT <= "00"; - else - buf_INT_DATA_OUT <= next_INT_DATA_OUT; - buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; - last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN; - buf_MED_DATA_IN <= next_buf_MED_DATA_IN; - buf_INT_PACKET_NUM_OUT <= next_INT_PACKET_NUM_OUT; + MED2INT_fsm_reg: process(CLK) + begin + if rising_edge(CLK) then + if RESET='1' then + buf_INT_DATAREADY_OUT <= '0'; + buf_INT_DATA_OUT <= (others => '0'); + last_MED_TRANSMISSION_CLK_IN <= '1'; + buf_MED_DATA_IN <= (others => '0'); + buf_INT_PACKET_NUM_OUT <= "00"; + else + buf_INT_DATA_OUT <= next_INT_DATA_OUT; + buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT; + last_MED_TRANSMISSION_CLK_IN <= reg_MED_TRANSMISSION_CLK_IN; + buf_MED_DATA_IN <= next_buf_MED_DATA_IN; + buf_INT_PACKET_NUM_OUT <= next_INT_PACKET_NUM_OUT; + end if; end if; - end if; - end process; + end process; -LVDS_IN_reg: process(CLK) - begin - if rising_edge(CLK) then - if RESET='1' then - reg_MED_TRANSMISSION_CLK_IN <= '0'; - reg_MED_CARRIER_IN <= '0'; - reg_MED_PARITY_IN <= '0'; - reg_MED_DATA_IN <= (others => '0'); - reg_MED_FIRST_PACKET_IN <= '0'; - else - reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13); - reg_MED_CARRIER_IN <= MED_DATA_IN(14); - reg_MED_PARITY_IN <= MED_DATA_IN(15); - reg_MED_DATA_IN <= MED_DATA_IN(7 downto 0); - reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12); + LVDS_IN_reg: process(CLK) + begin + if rising_edge(CLK) then + if RESET='1' then + reg_MED_TRANSMISSION_CLK_IN <= '0'; + reg_MED_CARRIER_IN <= '0'; + reg_MED_PARITY_IN <= '0'; + reg_MED_DATA_IN <= (others => '0'); + reg_MED_FIRST_PACKET_IN <= '0'; + else + reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13); + reg_MED_CARRIER_IN <= MED_DATA_IN(14); + reg_MED_PARITY_IN <= MED_DATA_IN(15); + reg_MED_DATA_IN <= MED_DATA_IN(7 downto 0); + reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12); + end if; end if; - end if; - end process; - + end process; end architecture; diff --git a/trb_net_pattern_gen.vhd b/trb_net_pattern_gen.vhd index db4fd99..f9d5beb 100644 --- a/trb_net_pattern_gen.vhd +++ b/trb_net_pattern_gen.vhd @@ -7,22 +7,24 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net_pattern_gen is - generic (MULT_WIDTH : integer := 3); - + generic ( + WIDTH : integer := 3 + ); port( - INPUT_IN : in STD_LOGIC_VECTOR (MULT_WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**MULT_WIDTH-1 downto 0) + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) ); END trb_net_pattern_gen; architecture trb_net_pattern_gen_arch of trb_net_pattern_gen is begin - G1: for i in 0 to 2**MULT_WIDTH-1 generate + G1: for i in 0 to 2**WIDTH-1 generate G2: process (INPUT_IN) begin -- process if i = INPUT_IN then diff --git a/trb_net_priority_arbiter.vhd b/trb_net_priority_arbiter.vhd index 751e01d..a812d1f 100755 --- a/trb_net_priority_arbiter.vhd +++ b/trb_net_priority_arbiter.vhd @@ -3,24 +3,23 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net_priority_arbiter is --- generic (WIDTH : integer := 16); - generic (WIDTH : integer := 2); - + generic ( + WIDTH : integer := 2 + ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - - ENABLE : in std_logic; - CTRL: in STD_LOGIC_VECTOR (31 downto 0) + ENABLE : in std_logic; + CTRL : in STD_LOGIC_VECTOR (31 downto 0) ); END trb_net_priority_arbiter; @@ -28,12 +27,13 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is component trb_net_priority_encoder is - generic (WIDTH : integer := 8); - + generic ( + WIDTH : integer := 8 + ); port( - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - PATTERN_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0) + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + PATTERN_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) ); END component; @@ -57,11 +57,13 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is --------------------------------------------------------------------------- ENC1: trb_net_priority_encoder - generic map (WIDTH => WIDTH) + generic map ( + WIDTH => WIDTH + ) port map( INPUT_IN => INPUT_IN, RESULT_OUT => next_fixed_pattern - ); + ); ------------------------------------------------------------------------------- -- round robin: determine next pattern @@ -72,20 +74,24 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is -- we call this proposed pattern ENC2: trb_net_priority_encoder - generic map (WIDTH => WIDTH) + generic map ( + WIDTH => WIDTH + ) port map( INPUT_IN => sampled_rr_pattern1, RESULT_OUT => proposed_rr_pattern1, PATTERN_OUT => leading_rr_pattern1 - ); + ); ENC3: trb_net_priority_encoder - generic map (WIDTH => WIDTH) + generic map ( + WIDTH => WIDTH + ) port map( INPUT_IN => sampled_rr_pattern2, RESULT_OUT => proposed_rr_pattern2, PATTERN_OUT => leading_rr_pattern2 - ); + ); sampled_rr_pattern1 <= INPUT_IN and current_p1_pattern; sampled_rr_pattern2 <= INPUT_IN and current_p2_pattern; @@ -165,8 +171,5 @@ architecture trb_net_priority_arbiter_arch of trb_net_priority_arbiter is end if; end process; - - - -end trb_net_priority_arbiter_arch; +end architecture; diff --git a/trb_net_priority_encoder.vhd b/trb_net_priority_encoder.vhd index e2a3c57..9eca237 100755 --- a/trb_net_priority_encoder.vhd +++ b/trb_net_priority_encoder.vhd @@ -3,16 +3,17 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; entity trb_net_priority_encoder is - - generic (WIDTH : integer := 4); - - port( - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - PATTERN_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0) + generic ( + WIDTH : integer := 4 + ); + port ( + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + PATTERN_OUT : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) ); end trb_net_priority_encoder; diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd index a62f4cd..8ba832b 100644 --- a/trb_net_sbuf.vhd +++ b/trb_net_sbuf.vhd @@ -17,14 +17,15 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; +library work; use work.trb_net_std.all; +use work.trb_net_cfg.all; entity trb_net_sbuf is - - generic (DATA_WIDTH : integer := 18; - VERSION: integer := 0); - - + generic ( + DATA_WIDTH : integer := 18; + VERSION: integer := 0 + ); port( -- Misc CLK : in std_logic; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index eb365cc..929b22a 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -1,23 +1,70 @@ -- std package - - library ieee; use ieee.std_logic_1164.all; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_UNSIGNED.ALL; package trb_net_std is + + type channel_config_t is array(0 to 3) of integer; + + +-- some basic definitions for the whole network +----------------------------------------------- + + constant c_DATA_WIDTH : integer := 16; + constant c_NUM_WIDTH : integer := 2; + constant c_MUX_WIDTH : integer := 1; + constant c_USE_ACKNOWLEDGE : channel_config_t := (1,1,1,1); + constant c_FORCE_REPLY : channel_config_t := (1,1,1,1); + constant c_USE_REPLY_CHANNEL : channel_config_t := (1,1,1,1); + +--assigning channel names + constant c_TRG_LVL1_CHANNEL : integer := 0; + constant c_TRG_LVL2_CHANNEL : integer := 1; + constant c_DATA_CHANNEL : integer := 2; + constant c_SLOW_CTRL_CHANNEL : integer := 3; + +--standard values + constant std_SBUF_VERSION : integer := 0; + constant std_IBUF_SECURE_MODE : integer := 1; + constant std_USE_ACKNOWLEDGE : integer := 1; + constant std_FIFO_DEPTH : integer := 1; + constant std_DATA_COUNT_WIDTH : integer := 5; --max 7 + constant std_TERM_SECURE_MODE : integer := 0; + constant std_MUX_SECURE_MODE : integer := 0; + constant std_FORCE_REPLY : integer := 1; + +--api_type generic + constant c_API_ACTIVE : integer := 1; + constant c_API_PASSIVE : integer := 0; + +--sbuf_version generic + constant c_SBUF_FULL : integer := 0; + constant c_SBUF_FAST : integer := 0; + constant c_SBUF_HALF : integer := 1; + constant c_SBUF_SLOW : integer := 1; + constant c_SECURE_MODE : integer := 1; + constant c_NON_SECURE_MODE : integer := 0; + +--fifo_depth + constant c_FIFO_NONE : integer := 0; + constant c_FIFO_2PCK : integer := 1; + constant c_FIFO_SMALL : integer := 1; + constant c_FIFO_4PCK : integer := 2; + constant c_FIFO_MEDIUM : integer := 2; + constant c_FIFO_8PCK : integer := 3; + constant c_FIFO_BIG : integer := 3; + constant c_FIFO_BRAM : integer := 6; + constant c_FIFO_BIGGEST : integer := 6; + constant c_FIFO_INFTY : integer := 7; + +--simple logic + constant c_YES : integer := 1; + constant c_NO : integer := 0; - function and_all (arg : std_logic_vector) - return std_logic; - function or_all (arg : std_logic_vector) - return std_logic; - function all_zero (arg : std_logic_vector) - return std_logic; - function xor_all (arg : std_logic_vector) - return std_logic; - subtype TYPE_POSITION is integer range 50 downto 48; +--packet types constant TYPE_DAT : std_logic_vector(2 downto 0) := "000"; constant TYPE_HDR : std_logic_vector(2 downto 0) := "001"; constant TYPE_EOB : std_logic_vector(2 downto 0) := "010"; @@ -25,31 +72,28 @@ package trb_net_std is constant TYPE_ACK : std_logic_vector(2 downto 0) := "101"; constant TYPE_ILLEGAL : std_logic_vector(2 downto 0) := "111"; +--Media interface error codes constant ERROR_OK : std_logic_vector(2 downto 0) := "000"; --transmission ok constant ERROR_ENCOD : std_logic_vector(2 downto 0) := "001"; --transmission error by encoding constant ERROR_RECOV : std_logic_vector(2 downto 0) := "010"; --transmission error, reconstructed constant ERROR_FATAL : std_logic_vector(2 downto 0) := "011"; --transmission error, fatal constant ERROR_NC : std_logic_vector(2 downto 0) := "101"; --media not connected - subtype F1_POSITION is integer range 47 downto 32; - subtype F2_POSITION is integer range 31 downto 16; - subtype F3_POSITION is integer range 15 downto 0; - subtype DWORD_POSITION is integer range 47 downto 0; - --- this is for TRM - subtype DTYPE_POSITION is integer range 3 downto 0; - subtype SEQNR_POSITION is integer range 11 downto 4; - subtype ERRORPATTERN_POSITION is integer range 47 downto 16; - - subtype SOURCE_POSITION is integer range 47 downto 32; - subtype TARGET_POSITION is integer range 31 downto 16; - - constant ILLEGAL_ADRESS : std_logic_vector(15 downto 0) := x"0000"; - constant BROADCAST_ADRESS : std_logic_vector(15 downto 0) := x"ffff"; - - constant F1_CHECK_ACK : std_logic_vector(15 downto 0) := x"0000"; - subtype BUFFER_SIZE_POSITION is integer range 19 downto 16; +--special addresses + constant ILLEGAL_ADDRESS : std_logic_vector(15 downto 0) := x"0000"; + constant BROADCAST_ADDRESS : std_logic_vector(15 downto 0) := x"ffff"; + + + function and_all (arg : std_logic_vector) + return std_logic; + function or_all (arg : std_logic_vector) + return std_logic; + function all_zero (arg : std_logic_vector) + return std_logic; + function xor_all (arg : std_logic_vector) + return std_logic; + end package trb_net_std; package body trb_net_std is diff --git a/xilinx/trb_net16_bram_fifo.vhd b/xilinx/trb_net16_bram_fifo.vhd index 5037621..4886c36 100644 --- a/xilinx/trb_net16_bram_fifo.vhd +++ b/xilinx/trb_net16_bram_fifo.vhd @@ -182,11 +182,13 @@ emptyg <= (not or_all(fcounter(9 downto 1)) AND ra_or_fcnt0) AND NOT write_allow proc3: process (clock, fifo_gsr) begin - if (fifo_gsr = '1') then + if rising_edge(clock) then + if (fifo_gsr = '1') then empty <= '1'; - elsif (clock'EVENT AND clock = '1') then + else empty <= emptyg; - end if; + end if; + end if; end process proc3; --------------------------------------------------------------- @@ -206,11 +208,13 @@ fullg <= (and_all(fcounter(9 downto 1)) AND wa_or_fcnt0 AND NOT read_allow); proc4: process (clock, fifo_gsr) begin - if (fifo_gsr = '1') then + if rising_edge(clock) then + if (fifo_gsr = '1') then full <= '1'; - elsif (clock'EVENT AND clock = '1') then + else full <= fullg; - end if; + end if; + end if; end process proc4; ---------------------------------------------------------------- @@ -224,24 +228,24 @@ end process proc4; proc5: process (clock, fifo_gsr) begin - if (fifo_gsr = '1') then - read_addr <= "0000000000"; - elsif (clock'EVENT AND clock = '1') then - if (read_allow = '1') then - read_addr <= read_addr + '1'; - end if; - end if; + if rising_edge(clock) then + if (fifo_gsr = '1') then + read_addr <= (others => '0'); + elsif (read_allow = '1') then + read_addr <= read_addr + '1'; + end if; + end if; end process proc5; proc6: process (clock, fifo_gsr) begin - if (fifo_gsr = '1') then + if rising_edge(clock) then + if (fifo_gsr = '1') then write_addr <= "0000000000"; - elsif (clock'EVENT AND clock = '1') then - if (write_allow = '1') then - write_addr <= write_addr + '1'; - end if; - end if; + elsif (write_allow = '1') then + write_addr <= write_addr + '1'; + end if; + end if; end process proc6; ---------------------------------------------------------------- @@ -256,17 +260,17 @@ end process proc6; proc7: process (clock, fifo_gsr) begin - if (fifo_gsr = '1') then + if rising_edge(clock) then + if (fifo_gsr = '1') then fcounter <= "0000000000"; - elsif (clock'EVENT AND clock = '1') then - if (fcnt_allow = '1') then - if (read_allow = '1') then -- and read_after_write = '0' - fcounter <= fcounter - '1'; - elsE - fcounter <= fcounter + '1'; - end if; + elsif (fcnt_allow = '1') then + if (read_allow = '1') then -- and read_after_write = '0' + fcounter <= fcounter - '1'; + else + fcounter <= fcounter + '1'; end if; - end if; + end if; + end if; end process proc7; fifocount_out <= fcounter(9 downto 6); diff --git a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd index 9f62d18..5842c5e 100644 --- a/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd +++ b/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd @@ -182,15 +182,15 @@ empty_allow <= (empty OR read_enable); -- -- --------------------------------------------------------------- -proc1: PROCESS (read_clock, fifo_gsr) +proc1: PROCESS (read_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(read_clock) then + IF (fifo_gsr = '1') THEN empty <= '1'; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - IF (empty_allow = '1') THEN - empty <= emptyg; - end IF; - end IF; + ELSIF (empty_allow = '1') THEN + empty <= emptyg; + end IF; + end IF; end PROCESS proc1; --------------------------------------------------------------- @@ -206,15 +206,15 @@ end PROCESS proc1; -- -- --------------------------------------------------------------- -proc2: PROCESS (write_clock, fifo_gsr) +proc2: PROCESS (write_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(write_clock) then + IF (fifo_gsr = '1') THEN full <= '1'; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - IF (full_allow = '1') THEN - full <= fullg; - end IF; - end IF; + ELSIF (full_allow = '1') THEN + full <= fullg; + end IF; + end IF; end PROCESS proc2; ---------------------------------------------------------------- @@ -233,56 +233,56 @@ end PROCESS proc2; -- -- ---------------------------------------------------------------- -proc3: PROCESS (read_clock, fifo_gsr) +proc3: PROCESS (read_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(read_clock) then + IF (fifo_gsr = '1') THEN read_addr(8 downto 0) <= "000000000"; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - IF (read_allow = '1') THEN - read_addr(8 downto 0) <= read_addr(8 downto 0) + 1; - end IF; - end IF; + ELSIF (read_allow = '1') THEN + read_addr(8 downto 0) <= read_addr(8 downto 0) + 1; + end IF; + end IF; end PROCESS proc3; -proc4: PROCESS (read_clock, fifo_gsr) +proc4: PROCESS (read_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(read_clock) then + IF (fifo_gsr = '1') THEN read_nextgray <= "100000000"; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - IF (read_allow = '1') THEN - read_nextgray(8) <= read_addr(8); - read_nextgray(7) <= read_addr(8) XOR read_addr(7); - read_nextgray(6) <= read_addr(7) XOR read_addr(6); - read_nextgray(5) <= read_addr(6) XOR read_addr(5); - read_nextgray(4) <= read_addr(5) XOR read_addr(4); - read_nextgray(3) <= read_addr(4) XOR read_addr(3); - read_nextgray(2) <= read_addr(3) XOR read_addr(2); - read_nextgray(1) <= read_addr(2) XOR read_addr(1); - read_nextgray(0) <= read_addr(1) XOR read_addr(0); - end IF; - end IF; + ELSIF (read_allow = '1') THEN + read_nextgray(8) <= read_addr(8); + read_nextgray(7) <= read_addr(8) XOR read_addr(7); + read_nextgray(6) <= read_addr(7) XOR read_addr(6); + read_nextgray(5) <= read_addr(6) XOR read_addr(5); + read_nextgray(4) <= read_addr(5) XOR read_addr(4); + read_nextgray(3) <= read_addr(4) XOR read_addr(3); + read_nextgray(2) <= read_addr(3) XOR read_addr(2); + read_nextgray(1) <= read_addr(2) XOR read_addr(1); + read_nextgray(0) <= read_addr(1) XOR read_addr(0); + end IF; + end IF; end PROCESS proc4; -proc5: PROCESS (read_clock, fifo_gsr) +proc5: PROCESS (read_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(read_clock) then + IF (fifo_gsr = '1') THEN read_addrgray <= "100000001"; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - IF (read_allow = '1') THEN - read_addrgray <= read_nextgray; - end IF; - end IF; + ELSIF (read_allow = '1') THEN + read_addrgray <= read_nextgray; + end IF; + end IF; end PROCESS proc5; -proc6: PROCESS (read_clock, fifo_gsr) +proc6: PROCESS (read_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(read_clock) then + IF (fifo_gsr = '1') THEN read_lastgray <= "100000011"; - ELSIF (read_clock'EVENT AND read_clock = '1') THEN - IF (read_allow = '1') THEN - read_lastgray <= read_addrgray; - end IF; - end IF; + ELSIF (read_allow = '1') THEN + read_lastgray <= read_addrgray; + end IF; + end IF; end PROCESS proc6; ---------------------------------------------------------------- @@ -292,45 +292,45 @@ end PROCESS proc6; -- -- ---------------------------------------------------------------- -proc7: PROCESS (write_clock, fifo_gsr) +proc7: PROCESS (write_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(write_clock) then + IF (fifo_gsr = '1') THEN write_addr(8 downto 0) <= "000000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - IF (write_allow = '1') THEN - write_addr(8 downto 0) <= write_addr(8 downto 0) + 1; - end IF; - end IF; + ELSIF (write_allow = '1') THEN + write_addr(8 downto 0) <= write_addr(8 downto 0) + 1; + end IF; + end IF; end PROCESS proc7; -proc8: PROCESS (write_clock, fifo_gsr) +proc8: PROCESS (write_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(write_clock) then + IF (fifo_gsr = '1') THEN write_nextgray <= "100000000"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - IF (write_allow = '1') THEN - write_nextgray(8) <= write_addr(8); - write_nextgray(7) <= write_addr(8) XOR write_addr(7); - write_nextgray(6) <= write_addr(7) XOR write_addr(6); - write_nextgray(5) <= write_addr(6) XOR write_addr(5); - write_nextgray(4) <= write_addr(5) XOR write_addr(4); - write_nextgray(3) <= write_addr(4) XOR write_addr(3); - write_nextgray(2) <= write_addr(3) XOR write_addr(2); - write_nextgray(1) <= write_addr(2) XOR write_addr(1); - write_nextgray(0) <= write_addr(1) XOR write_addr(0); - end IF; - end IF; + ELSIF (write_allow = '1') THEN + write_nextgray(8) <= write_addr(8); + write_nextgray(7) <= write_addr(8) XOR write_addr(7); + write_nextgray(6) <= write_addr(7) XOR write_addr(6); + write_nextgray(5) <= write_addr(6) XOR write_addr(5); + write_nextgray(4) <= write_addr(5) XOR write_addr(4); + write_nextgray(3) <= write_addr(4) XOR write_addr(3); + write_nextgray(2) <= write_addr(3) XOR write_addr(2); + write_nextgray(1) <= write_addr(2) XOR write_addr(1); + write_nextgray(0) <= write_addr(1) XOR write_addr(0); + end IF; + end IF; end PROCESS proc8; -proc9: PROCESS (write_clock, fifo_gsr) +proc9: PROCESS (write_clock) BEGIN - IF (fifo_gsr = '1') THEN + if rising_edge(write_clock) then + IF (fifo_gsr = '1') THEN write_addrgray <= "100000001"; - ELSIF (write_clock'EVENT AND write_clock = '1') THEN - IF (write_allow = '1') THEN - write_addrgray <= write_nextgray; - end IF; - end IF; + ELSIF (write_allow = '1') THEN + write_addrgray <= write_nextgray; + end IF; + end IF; end PROCESS proc9; ---------------------------------------------------------------- -- 2.43.0