From 667479903c0f84b08cf4f5d06765bbcdbb07f9cd Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Mon, 14 Apr 2014 17:45:59 +0200 Subject: [PATCH] link loss-of-lock problems. seem fixed. Creating separate serdesses for : 1) source down, 2) hub up, 3) hub down and 4) client up --- soda_client.ldf | 6 +- soda_client.lpf | 6 +- soda_client_probe.rvl | 384 +++++++++++++----------------- soda_hub_probe.rvl | 195 ++++++++------- soda_source.ldf | 50 ++-- soda_source.lpf | 10 +- soda_source/soda_source_syn.prj | 36 ++- soda_source_probe.rvl | 261 ++++++++++---------- source/TB_soda_chain.vhd | 48 ++-- source/med_ecp3_sfp_sync_down.vhd | 36 +-- source/med_ecp3_sfp_sync_up.vhd | 102 ++++---- source/serdes_sync_downstream.ipx | 14 +- source/serdes_sync_downstream.lpc | 28 +-- source/serdes_sync_downstream.txt | 111 +-------- source/serdes_sync_downstream.vhd | 6 +- source/serdes_sync_upstream.ipx | 14 +- source/serdes_sync_upstream.lpc | 4 +- source/soda_SOB_faker.vhd | 2 +- source/soda_components.vhd | 129 ++++++++-- source/soda_hub.vhd | 67 +++--- source/trb3_periph_sodaclient.vhd | 45 ++-- source/trb3_periph_sodasource.vhd | 308 +++++++++++++----------- trb3_soda_client.xcf | 228 ++++++++++++++++++ trb3_soda_dual_client.xcf | 224 +++++++++++++++++ trb3_soda_hub.xcf | 228 ++++++++++++++++++ trb3_soda_source.xcf | 227 ++++++++++++++++++ 26 files changed, 1842 insertions(+), 927 deletions(-) create mode 100644 trb3_soda_client.xcf create mode 100644 trb3_soda_dual_client.xcf create mode 100644 trb3_soda_hub.xcf create mode 100644 trb3_soda_source.xcf diff --git a/soda_client.ldf b/soda_client.ldf index 26aa3e2..68940a9 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -29,13 +29,13 @@ - + - + - + diff --git a/soda_client.lpf b/soda_client.lpf index e7e32a2..e65d083 100644 --- a/soda_client.lpf +++ b/soda_client.lpf @@ -1,4 +1,4 @@ -rvl_alias "reveal_ist_458" "the_sync_link/clk_rx_full"; +rvl_alias "soda_rx_clock_full" "soda_rx_clock_full"; RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; @@ -217,7 +217,7 @@ USE PRIMARY NET "clk_raw_internal" ; USE PRIMARY NET "clk_sys_internal" ; #USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ; #USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ; -USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; -USE PRIMARY PURE NET "GPLL_CLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +#USE PRIMARY PURE NET "CLK_PCLK_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; USE PRIMARY NET "soda_rx_clock_full" ; USE PRIMARY NET "soda_rx_clock_half" ; diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl index a0d27a9..4b2f652 100644 --- a/soda_client_probe.rvl +++ b/soda_client_probe.rvl @@ -1,29 +1,83 @@ - + - + - - + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - @@ -35,7 +89,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -46,97 +129,30 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - - - - - - + + + + + @@ -147,130 +163,68 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - + + + + + + + + + + + + + diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index 642e560..6ca046c 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,102 +1,137 @@ - + - + - + - + - - - - - - - - - - + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + - - - - + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - + + + + + - - - + + + + + + + + + + + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - + - - - - - diff --git a/soda_source.ldf b/soda_source.ldf index 76f8658..c15cb96 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -14,16 +14,13 @@ - - - - + - + - + @@ -47,18 +44,21 @@ - + - + - + + + + @@ -68,12 +68,6 @@ - - - - - - @@ -155,24 +149,24 @@ - - - - + - + + + + @@ -278,6 +272,9 @@ + + + @@ -299,9 +296,6 @@ - - - @@ -314,7 +308,13 @@ - + + + + + + + @@ -323,7 +323,7 @@ - + diff --git a/soda_source.lpf b/soda_source.lpf index 44e7920..1bb7ff1 100644 --- a/soda_source.lpf +++ b/soda_source.lpf @@ -1,4 +1,4 @@ -rvl_alias "rx_clock_full" "rx_clock_full"; +rvl_alias "clk_raw_internal" "clk_raw_internal"; RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; @@ -183,12 +183,11 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# # Basic Settings ################################################################# -SYSCONFIG MCCLK_FREQ=20 ; + SYSCONFIG MCCLK_FREQ=20 ; + FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; # FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; # FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; # FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -#FREQUENCY NET "rx_clock_half" 100.000000 MHz ; -#FREQUENCY NET "rx_clock_full" 200.000000 MHz ; ################################################################# # Reset Nets ################################################################# @@ -218,7 +217,8 @@ MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; MULTICYCLE TO CELL "THE_SODA_SOURCE.packet_builder.soda_cmd_word_S*" 10.000000 ns ; BLOCK JTAGPATHS ; ## IOBUF ALLPORTS ; -#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; +USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ; FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ; diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj index 0eba5b7..19fbdfe 100644 --- a/soda_source/soda_source_syn.prj +++ b/soda_source/soda_source_syn.prj @@ -1,33 +1,32 @@ #-- Synopsys, Inc. -#-- Version G-2012.09L-SP1 +#-- Version I-2013.09L #-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj -#-- Written on Mon Dec 23 12:02:08 2013 +#-- Written on Wed Apr 9 12:12:25 2014 #project files -add_file -constraint "/local/lemmens/lattice/soda/source/soda_source_clock_constraints.sdc" -add_file -vhdl -lib work "/usr/local/diamond/2.2_x64/cae_library/synthesis/vhdl/ecp3.vhd" +add_file -fpga_constraint "/local/lemmens/lattice/soda/source/soda_source_synconstraints.fdc" +add_file -vhdl -lib work "/usr/local/diamond/3.1_x64/cae_library/synthesis/vhdl/ecp3.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/version.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_components.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_source.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_superburst_gen.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_builder.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_cmd_window_generator.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_d8crc8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/med_ecp3_sfp_sync_down.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_handler.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_pkt_builder.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_superburst_gen.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/med_ecp3_sfp_sync_up.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/serdes_sync_downstream.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_SOB_faker.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_calibration_timer.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/posedge_to_pulse.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_tx_control.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC8.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_data.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_ipu.vhd" @@ -55,12 +54,12 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_sbuf.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf5.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf6.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regIO.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_dummy_fifo.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_arbiter.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf.vhd" @@ -96,6 +95,7 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/med_sync_define.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_control.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_reset_fsm.vhd" @@ -103,13 +103,12 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/tx add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/trb3_periph_sodasource.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" -add_file -fpga_constraint "./FDC_constraints/soda_source/soda_source_syn_translated.fdc" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/trb3_periph_sodasource.vhd" + #implementation: "soda_source" @@ -121,9 +120,6 @@ impl -add soda_source -type fpga set_option -vlog_std v2001 set_option -project_relative_includes 1 -#set constraint files -set_option -constraint -clear - #device options set_option -technology LATTICE-ECP3 set_option -part LFE3_150EA diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index dc0203a..16425f8 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,135 +1,136 @@ - + - + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + + + + + - - - - - + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - - + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -148,18 +149,34 @@ - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - - + + + + + diff --git a/source/TB_soda_chain.vhd b/source/TB_soda_chain.vhd index 52967e6..50b2445 100644 --- a/source/TB_soda_chain.vhd +++ b/source/TB_soda_chain.vhd @@ -14,29 +14,29 @@ use work.soda_components.all; entity TB_soda_chain is end entity; - -architecture TestBench of TB_soda_chain is - + +architecture TestBench of TB_soda_chain is + -- Clock period definitions constant sysclk_period: time:= 10ns; constant sodaclk_period: time:= 5ns; - - + + --Inputs signal rst_S : std_logic; signal sys_clk_S : std_logic; signal soda_clk_S : std_logic; signal enable_S : std_logic := '0'; signal SOB_S : std_logic := '0'; - signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); - signal src_dnstream_dlm_valid_S : std_logic; - signal src_upstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); - signal src_upstream_dlm_valid_S : std_logic; + signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); + signal src_dnstream_dlm_valid_S : std_logic; + signal src_upstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); + signal src_upstream_dlm_valid_S : std_logic; - signal hub_dnstream_dlm_word_S : t_HUB_DLM_WORD; - signal hub_dnstream_dlm_valid_S : t_HUB_DLM; - signal hub_upstream_dlm_word_S : t_HUB_DLM_WORD; - signal hub_upstream_dlm_valid_S : t_HUB_DLM; + signal hub_dnstream_dlm_word_S : t_HUB_WORD; + signal hub_dnstream_dlm_valid_S : t_HUB_BIT; + signal hub_upstream_dlm_word_S : t_HUB_WORD; + signal hub_upstream_dlm_valid_S : t_HUB_BIT; --SODA signal soda_ack : std_logic; @@ -47,7 +47,7 @@ architecture TestBench of TB_soda_chain is signal soda_hub_data_out : std_logic_vector(31 downto 0); signal soda_clt_data_out : std_logic_vector(31 downto 0); signal soda_addr : std_logic_vector(3 downto 0) := (others => '0'); - signal soda_leds : std_logic_vector(3 downto 0); + signal soda_leds : std_logic_vector(3 downto 0); begin THE_SOB_SOURCE : soda_start_of_burst_faker @@ -56,8 +56,8 @@ begin RESET => rst_S, SODA_BURST_PULSE_OUT => SOB_S ); - - + + THE_SODA_SOURCE : soda_source port map( SYSCLK => sys_clk_S, @@ -77,7 +77,7 @@ begin SODA_ADDR_IN => soda_addr, SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, - SODA_ACK_OUT => soda_ack, + SODA_ACK_OUT => soda_ack, LEDS_OUT => soda_leds ); @@ -104,12 +104,12 @@ begin SODA_ADDR_IN => soda_addr, SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, - SODA_ACK_OUT => soda_ack, + SODA_ACK_OUT => soda_ack, STAT => open ); channel : for i in c_HUB_CHILDREN-1 downto 0 generate - + A_SODA_CLIENT : soda_client port map( SYSCLK => sys_clk_S, @@ -128,14 +128,14 @@ begin SODA_ADDR_IN => soda_addr, SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, - SODA_ACK_OUT => soda_ack, + SODA_ACK_OUT => soda_ack, LEDS_OUT => open, LINK_DEBUG_IN => (others => '0') ); end generate; - + ------------------------------------------------------------------------------------------------------------ -- SODA command packet ------------------------------------------------------------------------------------------------------------ @@ -212,6 +212,6 @@ begin rst_S <= '0'; wait; end process; - -end TestBench; - + +end TestBench; + diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd index de1076c..cfc43b1 100644 --- a/source/med_ecp3_sfp_sync_down.vhd +++ b/source/med_ecp3_sfp_sync_down.vhd @@ -170,8 +170,8 @@ type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GE signal sci_state : sci_ctrl; signal sci_timer : unsigned(12 downto 0) := (others => '0'); signal start_timer : unsigned(18 downto 0) := (others => '0'); -signal watchdog_timer : unsigned(20 downto 0) := (others => '0'); -signal watchdog_trigger : std_logic :='0'; +--signal watchdog_timer : unsigned(20 downto 0) := (others => '0'); +--signal watchdog_trigger : std_logic :='0'; begin @@ -188,8 +188,10 @@ SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches --rst_n <= not CLEAR; PL! -rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger); -rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger); +--rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); +--rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); +rst_n <= not(CLEAR or internal_make_link_reset_out); +rst <= (CLEAR or internal_make_link_reset_out); gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate @@ -218,7 +220,7 @@ THE_SERDES : entity work.serdes_sync_downstream rx_half_clk_ch0 => clk_rx_half, tx_full_clk_ch0 => clk_tx_full, tx_half_clk_ch0 => clk_tx_half, - fpga_rxrefclk_ch0 => clk_200_internal, + fpga_rxrefclk_ch0 => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT txdata_ch0 => tx_data, tx_k_ch0 => tx_k, tx_force_disp_ch0 => '0', @@ -249,7 +251,7 @@ THE_SERDES : entity work.serdes_sync_downstream SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_i, + fpga_txrefclk => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT tx_serdes_rst_c => tx_serdes_rst, tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -325,22 +327,22 @@ PROC_START_TIMER : process(clk_200_i) begin if rising_edge(clk_200_i) then if got_link_ready_i = '1' then - watchdog_timer <= (others => '0'); +-- watchdog_timer <= (others => '0'); if start_timer(start_timer'left) = '0' then start_timer <= start_timer + 1; end if; else start_timer <= (others => '0'); - if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 1) = '1')) then - watchdog_trigger <= '1'; - else - watchdog_trigger <= '0'; - end if; - if watchdog_trigger = '0' then - watchdog_timer <= watchdog_timer + 1; - else - watchdog_timer <= (others => '0'); - end if; +-- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 1) = '1')) then +-- watchdog_trigger <= '1'; +-- else +-- watchdog_trigger <= '0'; +-- end if; +-- if watchdog_trigger = '0' then +-- watchdog_timer <= watchdog_timer + 1; +-- else +-- watchdog_timer <= (others => '0'); +-- end if; end if; end if; end process; diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd index c96cf4a..fb2e98c 100644 --- a/source/med_ecp3_sfp_sync_up.vhd +++ b/source/med_ecp3_sfp_sync_up.vhd @@ -156,7 +156,7 @@ attribute syn_preserve of sci_write_shift_i : signal is true; attribute syn_keep of sci_write_shift_i : signal is true; attribute syn_preserve of sci_read_shift_i : signal is true; attribute syn_keep of sci_read_shift_i : signal is true; - + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF"; signal tx_allow : std_logic; @@ -196,7 +196,8 @@ CLK_RX_FULL_OUT <= clk_rx_full; -SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready +--SD_TXDIS_OUT <= not (rx_allow_q or not IS_SYNC_SLAVE); --slave only switches on when RX is ready +SD_TXDIS_OUT <= '0'; --not (rx_allow_q); --slave only switches on when RX is ready --rst_n <= not CLEAR; PL! @@ -216,45 +217,45 @@ end generate; ------------------------------------------------- -- Serdes ------------------------------------------------- -THE_SERDES : entity work.serdes_sync_upstream +THE_SERDES : entity work.serdes_sync_client_upstream port map( - hdinp_ch3 => SD_RXD_P_IN, - hdinn_ch3 => SD_RXD_N_IN, - hdoutp_ch3 => SD_TXD_P_OUT, - hdoutn_ch3 => SD_TXD_N_OUT, --- rxiclk_ch3 => clk_200_i, -- no more RX-fifo - txiclk_ch3 => clk_200_i, - rx_full_clk_ch3 => clk_rx_full, - rx_half_clk_ch3 => clk_rx_half, - tx_full_clk_ch3 => clk_tx_full, - tx_half_clk_ch3 => clk_tx_half, - fpga_rxrefclk_ch3 => clk_200_internal, - txdata_ch3 => tx_data, - tx_k_ch3 => tx_k, - tx_force_disp_ch3 => '0', - tx_disp_sel_ch3 => '0', - rxdata_ch3 => rx_data, - rx_k_ch3 => rx_k, - rx_disp_err_ch3 => open, - rx_cv_err_ch3 => rx_error, - rx_serdes_rst_ch3_c => rx_serdes_rst, - sb_felb_ch3_c => '0', - sb_felb_rst_ch3_c => '0', - tx_pcs_rst_ch3_c => tx_pcs_rst, - tx_pwrup_ch3_c => '1', - rx_pcs_rst_ch3_c => rx_pcs_rst, - rx_pwrup_ch3_c => '1', - rx_los_low_ch3_s => rx_los_low, - lsm_status_ch3_s => lsm_status, - rx_cdr_lol_ch3_s => rx_cdr_lol, - tx_div2_mode_ch3_c => '0', - rx_div2_mode_ch3_c => '0', + hdinp_ch0 => SD_RXD_P_IN, + hdinn_ch0 => SD_RXD_N_IN, + hdoutp_ch0 => SD_TXD_P_OUT, + hdoutn_ch0 => SD_TXD_N_OUT, +-- rxiclk_ch0 => clk_200_i, -- no more RX-fifo + txiclk_ch0 => clk_200_i, + rx_full_clk_ch0 => clk_rx_full, + rx_half_clk_ch0 => clk_rx_half, + tx_full_clk_ch0 => clk_tx_full, + tx_half_clk_ch0 => clk_tx_half, + fpga_rxrefclk_ch0 => clk_200_internal, + txdata_ch0 => tx_data, + tx_k_ch0 => tx_k, + tx_force_disp_ch0 => '0', + tx_disp_sel_ch0 => '0', + rxdata_ch0 => rx_data, + rx_k_ch0 => rx_k, + rx_disp_err_ch0 => open, + rx_cv_err_ch0 => rx_error, + rx_serdes_rst_ch0_c => rx_serdes_rst, + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pcs_rst_ch0_c => tx_pcs_rst, + tx_pwrup_ch0_c => '1', + rx_pcs_rst_ch0_c => rx_pcs_rst, + rx_pwrup_ch0_c => '1', + rx_los_low_ch0_s => rx_los_low, + lsm_status_ch0_s => lsm_status, + rx_cdr_lol_ch0_s => rx_cdr_lol, + tx_div2_mode_ch0_c => '0', + rx_div2_mode_ch0_c => '0', SCI_WRDATA => sci_data_in_i, SCI_RDDATA => sci_data_out_i, SCI_ADDR => sci_addr_i(5 downto 0), SCI_SEL_QUAD => sci_qd_i, - SCI_SEL_CH3 => sci_ch_i(0), + SCI_SEL_ch0 => sci_ch_i(0), SCI_RD => sci_read_i, SCI_WRN => sci_write_i, @@ -315,27 +316,27 @@ rx_allow_q <= rx_allow when rising_edge(SYSCLK); tx_allow_q <= tx_allow when rising_edge(SYSCLK); -PROC_START_TIMER : process(clk_200_i) -begin +PROC_START_TIMER : process(clk_200_i) +begin if rising_edge(clk_200_i) then - if got_link_ready_i = '1' then + if got_link_ready_i = '1' then watchdog_timer <= (others => '0'); if start_timer(start_timer'left) = '0' then start_timer <= start_timer + 1; end if; else - start_timer <= (others => '0'); - if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then - watchdog_trigger <= '1'; + start_timer <= (others => '0'); + if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then + watchdog_trigger <= '1'; else - watchdog_trigger <= '0'; + watchdog_trigger <= '0'; end if; - if watchdog_trigger = '0' then - watchdog_timer <= watchdog_timer + 1; - else + if watchdog_trigger = '0' then + watchdog_timer <= watchdog_timer + 1; + else watchdog_timer <= (others => '0'); - end if; - end if; + end if; + end if; end if; end process; @@ -537,8 +538,8 @@ sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK); STAT_OP(14) <= '0'; STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset -STAT_OP(12) <= '0'; -STAT_OP(11) <= '0'; +STAT_OP(12) <= tx_pll_lol; --'0'; +STAT_OP(11) <= rx_cdr_lol; --'0'; STAT_OP(10) <= rx_allow; STAT_OP(9) <= tx_allow; --STAT_OP(8 downto 4) <= (others => '0'); @@ -548,5 +549,4 @@ STAT_OP(6) <= make_link_reset_i; STAT_OP(5) <= request_retr_i; STAT_OP(4) <= start_retr_i; STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; -end med_ecp3_sfp_sync_up_arch; - +end med_ecp3_sfp_sync_up_arch; \ No newline at end of file diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx index 6674ab9..5ace6b2 100644 --- a/source/serdes_sync_downstream.ipx +++ b/source/serdes_sync_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc index f120186..450fb27 100644 --- a/source/serdes_sync_downstream.lpc +++ b/source/serdes_sync_downstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/20/2014 -Time=15:47:38 +Date=04/07/2014 +Time=16:16:00 [Parameters] Verilog=0 @@ -56,17 +56,17 @@ _tx_data_width1=8 _tx_data_width2=8 _tx_data_width3=8 _tx_fifo0=DISABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED +_tx_fifo1=DISABLED +_tx_fifo2=DISABLED +_tx_fifo3=DISABLED _tx_ficlk_rate0=200 _tx_ficlk_rate1=200 _tx_ficlk_rate2=200 _tx_ficlk_rate3=200 _pll_rxsrc0=INTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=EXTERNAL +_pll_rxsrc1=INTERNAL +_pll_rxsrc2=INTERNAL +_pll_rxsrc3=INTERNAL Multiplier0= Multiplier1= Multiplier2= @@ -92,9 +92,9 @@ _rx_data_width1=8 _rx_data_width2=8 _rx_data_width3=8 _rx_fifo0=DISABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED +_rx_fifo1=DISABLED +_rx_fifo2=DISABLED +_rx_fifo3=DISABLED _rx_ficlk_rate0=200 _rx_ficlk_rate1=250.0 _rx_ficlk_rate2=250.0 @@ -120,9 +120,9 @@ _rterm_rx1=50 _rterm_rx2=50 _rterm_rx3=50 _rx_dcc0=DC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC +_rx_dcc1=DC +_rx_dcc2=DC +_rx_dcc3=DC _los_threshold_mode0=LOS_E _los_threshold_mode1=LOS_E _los_threshold_mode2=LOS_E diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt index 2bb812f..ec77632 100644 --- a/source/serdes_sync_downstream.txt +++ b/source/serdes_sync_downstream.txt @@ -5,158 +5,53 @@ DEVICE_NAME "LFE3-150EA" CH0_PROTOCOL "G8B10B" -CH1_PROTOCOL "G8B10B" -CH2_PROTOCOL "G8B10B" -CH3_PROTOCOL "G8B10B" CH0_MODE "RXTX" -CH1_MODE "RXTX" -CH2_MODE "RXTX" -CH3_MODE "RXTX" +CH1_MODE "DISABLED" +CH2_MODE "DISABLED" +CH3_MODE "DISABLED" CH0_CDR_SRC "REFCLK_CORE" -CH1_CDR_SRC "REFCLK_CORE" -CH2_CDR_SRC "REFCLK_CORE" -CH3_CDR_SRC "REFCLK_CORE" PLL_SRC "REFCLK_CORE" TX_DATARATE_RANGE "MEDHIGH" CH0_RX_DATARATE_RANGE "MEDHIGH" -CH1_RX_DATARATE_RANGE "MEDHIGH" -CH2_RX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" REFCK_MULT "10X" #REFCLK_RATE 200 CH0_RX_DATA_RATE "FULL" -CH1_RX_DATA_RATE "FULL" -CH2_RX_DATA_RATE "FULL" -CH3_RX_DATA_RATE "FULL" CH0_TX_DATA_RATE "FULL" -CH1_TX_DATA_RATE "FULL" -CH2_TX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" CH0_TX_DATA_WIDTH "8" -CH1_TX_DATA_WIDTH "8" -CH2_TX_DATA_WIDTH "8" -CH3_TX_DATA_WIDTH "8" CH0_RX_DATA_WIDTH "8" -CH1_RX_DATA_WIDTH "8" -CH2_RX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" CH0_TX_FIFO "DISABLED" -CH1_TX_FIFO "ENABLED" -CH2_TX_FIFO "ENABLED" -CH3_TX_FIFO "ENABLED" CH0_RX_FIFO "DISABLED" -CH1_RX_FIFO "DISABLED" -CH2_RX_FIFO "DISABLED" -CH3_RX_FIFO "DISABLED" CH0_TDRV "0" -CH1_TDRV "0" -CH2_TDRV "0" -CH3_TDRV "0" #CH0_TX_FICLK_RATE 200 -#CH1_TX_FICLK_RATE 200 -#CH2_TX_FICLK_RATE 200 -#CH3_TX_FICLK_RATE 200 #CH0_RXREFCLK_RATE "200" -#CH1_RXREFCLK_RATE "200" -#CH2_RXREFCLK_RATE "200" -#CH3_RXREFCLK_RATE "200" #CH0_RX_FICLK_RATE 200 -#CH1_RX_FICLK_RATE 200 -#CH2_RX_FICLK_RATE 200 -#CH3_RX_FICLK_RATE 200 CH0_TX_PRE "DISABLED" -CH1_TX_PRE "DISABLED" -CH2_TX_PRE "DISABLED" -CH3_TX_PRE "DISABLED" CH0_RTERM_TX "50" -CH1_RTERM_TX "50" -CH2_RTERM_TX "50" -CH3_RTERM_TX "50" CH0_RX_EQ "DISABLED" -CH1_RX_EQ "DISABLED" -CH2_RX_EQ "DISABLED" -CH3_RX_EQ "DISABLED" CH0_RTERM_RX "50" -CH1_RTERM_RX "50" -CH2_RTERM_RX "50" -CH3_RTERM_RX "50" CH0_RX_DCC "DC" -CH1_RX_DCC "DC" -CH2_RX_DCC "DC" -CH3_RX_DCC "DC" CH0_LOS_THRESHOLD_LO "2" -CH1_LOS_THRESHOLD_LO "2" -CH2_LOS_THRESHOLD_LO "2" -CH3_LOS_THRESHOLD_LO "2" PLL_TERM "50" PLL_DCC "AC" PLL_LOL_SET "0" CH0_TX_SB "DISABLED" -CH1_TX_SB "DISABLED" -CH2_TX_SB "DISABLED" -CH3_TX_SB "DISABLED" CH0_RX_SB "DISABLED" -CH1_RX_SB "DISABLED" -CH2_RX_SB "DISABLED" -CH3_RX_SB "DISABLED" CH0_TX_8B10B "ENABLED" -CH1_TX_8B10B "ENABLED" -CH2_TX_8B10B "ENABLED" -CH3_TX_8B10B "ENABLED" CH0_RX_8B10B "ENABLED" -CH1_RX_8B10B "ENABLED" -CH2_RX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" CH0_COMMA_A "1100000101" -CH1_COMMA_A "1100000101" -CH2_COMMA_A "1100000101" -CH3_COMMA_A "1100000101" CH0_COMMA_B "0011111010" -CH1_COMMA_B "0011111010" -CH2_COMMA_B "0011111010" -CH3_COMMA_B "0011111010" CH0_COMMA_M "1111111100" -CH1_COMMA_M "1111111100" -CH2_COMMA_M "1111111100" -CH3_COMMA_M "1111111100" CH0_RXWA "ENABLED" -CH1_RXWA "ENABLED" -CH2_RXWA "ENABLED" -CH3_RXWA "ENABLED" CH0_ILSM "ENABLED" -CH1_ILSM "ENABLED" -CH2_ILSM "ENABLED" -CH3_ILSM "ENABLED" CH0_CTC "DISABLED" -CH1_CTC "DISABLED" -CH2_CTC "DISABLED" -CH3_CTC "DISABLED" CH0_CC_MATCH4 "0100011100" -CH1_CC_MATCH4 "0100011100" -CH2_CC_MATCH4 "0100011100" -CH3_CC_MATCH4 "0100011100" CH0_CC_MATCH_MODE "1" -CH1_CC_MATCH_MODE "1" -CH2_CC_MATCH_MODE "1" -CH3_CC_MATCH_MODE "1" CH0_CC_MIN_IPG "3" -CH1_CC_MIN_IPG "3" -CH2_CC_MIN_IPG "3" -CH3_CC_MIN_IPG "3" CCHMARK "9" CCLMARK "7" CH0_SSLB "DISABLED" -CH1_SSLB "DISABLED" -CH2_SSLB "DISABLED" -CH3_SSLB "DISABLED" CH0_SPLBPORTS "DISABLED" -CH1_SPLBPORTS "DISABLED" -CH2_SPLBPORTS "DISABLED" -CH3_SPLBPORTS "DISABLED" CH0_PCSLBPORTS "DISABLED" -CH1_PCSLBPORTS "DISABLED" -CH2_PCSLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" INT_ALL "DISABLED" QD_REFCK2CORE "ENABLED" diff --git a/source/serdes_sync_downstream.vhd b/source/serdes_sync_downstream.vhd index 17cfd20..10f2d1a 100644 --- a/source/serdes_sync_downstream.vhd +++ b/source/serdes_sync_downstream.vhd @@ -20,9 +20,9 @@ GENERIC( -- CONFIG_FILE : String := "serdes_sync_downstream.txt"; -- QUAD_MODE : String := "SINGLE"; -- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_EXT"; +-- CH1_CDR_SRC : String := "REFCLK_CORE"; +-- CH2_CDR_SRC : String := "REFCLK_CORE"; +-- CH3_CDR_SRC : String := "REFCLK_CORE"; -- PLL_SRC : String := "REFCLK_CORE" ); port ( diff --git a/source/serdes_sync_upstream.ipx b/source/serdes_sync_upstream.ipx index 1a5ec6c..1485eb0 100644 --- a/source/serdes_sync_upstream.ipx +++ b/source/serdes_sync_upstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/source/serdes_sync_upstream.lpc b/source/serdes_sync_upstream.lpc index 872bc8c..15a05bb 100644 --- a/source/serdes_sync_upstream.lpc +++ b/source/serdes_sync_upstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_upstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/05/2014 -Time=09:13:21 +Date=02/25/2014 +Time=13:39:52 [Parameters] Verilog=0 diff --git a/source/soda_SOB_faker.vhd b/source/soda_SOB_faker.vhd index e1e2427..9296601 100644 --- a/source/soda_SOB_faker.vhd +++ b/source/soda_SOB_faker.vhd @@ -7,7 +7,7 @@ use ieee.std_logic_unsigned.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.trb_net16_hub_func.all; +use work.trb_net16_hub_func.all; use work.soda_components.all; entity soda_start_of_burst_faker is diff --git a/source/soda_components.vhd b/source/soda_components.vhd index 180f201..c0845e9 100644 --- a/source/soda_components.vhd +++ b/source/soda_components.vhd @@ -17,27 +17,39 @@ package soda_components is constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda - constant c_HUB_CHILDREN : natural range 1 to 4 := 2; -- number of children per soda-hub + constant c_HUB_CHILDREN : natural range 1 to 4 := 4; -- number of children per soda-hub constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns + constant cSYS_CLOCK_PERIOD : natural range 1 to 20 := 10; -- soda clock-period in ns constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns constant cSODA_COMMAND_WINDOS_SIZE : natural range 1 to 65535 := 5000; -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns constant cWINDOW_delay : std_logic_vector(7 downto 0) := conv_std_logic_vector(28, 8); -- in clock-cycles constant cCLOCKS_PER_WINDOW : std_logic_vector(15 downto 0) := conv_std_logic_vector((cSODA_COMMAND_WINDOS_SIZE / cSODA_CLOCK_PERIOD) - 1, 16); -- in clock-cycles + constant c_QUAD_DATA_WIDTH : integer := 4*c_DATA_WIDTH; + constant c_QUAD_NUM_WIDTH : integer := 4*c_NUM_WIDTH; + constant c_QUAD_MUX_WIDTH : integer := 3; --!!! + + subtype t_HUB_BIT is std_logic_vector(c_HUB_CHILDREN-1 downto 0); + type t_HUB_NUM is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(c_NUM_WIDTH-1 downto 0); + type t_HUB_NIBL is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(3 downto 0); + type t_HUB_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); + type t_HUB_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); + type t_HUB_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); + + type t_HUB_TIMER13 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(12 downto 0); + type t_HUB_TIMER19 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(18 downto 0); + type t_HUB_TIMER21 is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(20 downto 0); - type t_HUB_DLM is array(c_HUB_CHILDREN-1 downto 0) of std_logic; - type t_HUB_DLM_BYTE is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); - type t_HUB_DLM_WORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); - type t_HUB_DLM_LWORD is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); type t_PACKET_TYPE_SENT is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET); type t_PACKET_TYPE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of t_PACKET_TYPE_SENT; - type t_HUB_BIT_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic; + + subtype t_HUB_BIT_ARRAY is std_logic_vector(c_HUB_CHILDREN-1 downto 0); type t_HUB_BYTE_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0); type t_HUB_WORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(15 downto 0); type t_HUB_LWORD_ARRAY is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(31 downto 0); - type t_QUAD_BIT is array(3 downto 0) of std_logic; + subtype t_QUAD_BIT is std_logic_vector(3 downto 0); type t_QUAD_NIBL is array(3 downto 0) of std_logic_vector(3 downto 0); type t_QUAD_BYTE is array(3 downto 0) of std_logic_vector(7 downto 0); type t_QUAD_9WORD is array(3 downto 0) of std_logic_vector(8 downto 0); @@ -129,7 +141,7 @@ package soda_components is SODA_READ_IN : in std_logic := '0'; SODA_WRITE_IN : in std_logic := '0'; SODA_ACK_OUT : out std_logic := '0'; - LEDS_OUT : out std_logic_vector(3 downto 0) + LEDS_OUT : out std_logic_vector(3 downto 0) ); end component; @@ -150,12 +162,12 @@ package soda_components is UPLINK_PHASE_IN : in std_logic := '0'; --PL! -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM - RXDN_DLM_IN : in t_HUB_DLM; - RXDN_DLM_WORD_IN : in t_HUB_DLM_BYTE; - TXDN_DLM_OUT : out t_HUB_DLM; - TXDN_DLM_WORD_OUT : out t_HUB_DLM_BYTE; - TXDN_DLM_PREVIEW_OUT : out t_HUB_DLM; --PL! - DNLINK_PHASE_IN : in t_HUB_DLM; --PL! + RXDN_DLM_IN : in t_HUB_BIT; + RXDN_DLM_WORD_IN : in t_HUB_BYTE; + TXDN_DLM_OUT : out t_HUB_BIT; + TXDN_DLM_WORD_OUT : out t_HUB_BYTE; + TXDN_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL! + DNLINK_PHASE_IN : in t_HUB_BIT; --PL! SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); @@ -288,7 +300,7 @@ package soda_components is PULSE_OUT : out std_logic ); end component; - + component med_ecp3_sfp_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; @@ -324,15 +336,15 @@ component med_ecp3_sfp_sync_down is LINK_PHASE_OUT : out std_logic := '0'; --PL! --SFP Connection - SD_RXD_P_IN : in t_QUAD_BIT; - SD_RXD_N_IN : in t_QUAD_BIT; - SD_TXD_P_OUT : out t_QUAD_BIT; - SD_TXD_N_OUT : out t_QUAD_BIT; - SD_REFCLK_P_IN : in t_QUAD_BIT; --not used - SD_REFCLK_N_IN : in t_QUAD_BIT; --not used - SD_PRSNT_N_IN : in t_QUAD_BIT; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - SD_LOS_IN : in t_QUAD_BIT; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out t_QUAD_BIT := (others => '0'); -- SFP disable + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; --not used + SD_REFCLK_N_IN : in std_logic; --not used + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable --Control Interface SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); @@ -349,6 +361,66 @@ component med_ecp3_sfp_sync_down is ); end component; + +component med_ecp3_sfp_4_sync_down is + generic( SERDES_NUM : integer range 0 to 3 := 0; + IS_SYNC_SLAVE : integer := c_NO); --select slave mode + port( + CLK : in std_logic; -- _internal_ 200 MHz reference clock + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + --------------------------------------------------------------------------------------------------------------------------------------------------------- + LINK_DISABLE_IN : in std_logic; -- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established. + --------------------------------------------------------------------------------------------------------------------------------------------------------- + --Internal Connection TX + MED_DATA_IN : in t_HUB_WORD; --std_logic_vector(c_QUAD_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in t_HUB_NUM; --std_logic_vector(c_QUAD_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0) := (others => '0'); + --Internal Connection RX + MED_DATA_OUT : out t_HUB_WORD; -- std_logic_vector(4*c_DATA_WIDTH-1 downto 0) := (others => '0'); + MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); + MED_READ_IN : in std_logic_vector(3 downto 0); + + CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + + --Sync operation + RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + RX_DLM_WORD : out t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); + TX_DLM_WORD : in t_HUB_BYTE; --std_logic_vector(4*8 - 1 downto 0) := (others => '0'); + TX_DLM_PREVIEW_IN : in t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! + LINK_PHASE_OUT : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); --PL! + + --SFP Connection + SD_RXD_P_IN : in t_HUB_BIT; --std_logic; + SD_RXD_N_IN : in t_HUB_BIT; --std_logic; + SD_TXD_P_OUT : out t_HUB_BIT; --std_logic; + SD_TXD_N_OUT : out t_HUB_BIT; --std_logic; + SD_REFCLK_P_IN : in t_HUB_BIT; --std_logic; --not used + SD_REFCLK_N_IN : in t_HUB_BIT; --std_logic; --not used + SD_PRSNT_N_IN : in t_HUB_BIT; --std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in t_HUB_BIT; --std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out t_HUB_BIT; --std_logic := '0'; -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; + SCI_NACK : out std_logic := '0'; + -- Status and control port + STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0); + CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0'); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end component; + + component med_ecp3_sfp_sync_up is generic( SERDES_NUM : integer range 0 to 3 := 0; @@ -451,5 +523,14 @@ component soda_cmd_window_generator SODA_CMD_WINDOW_OUT : out std_logic := '0' ); end component; + +component soda_clockscaler is + port( + CLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLOCK_ENABLE_OUT : out std_logic := '0'; + CLOCK_OUT : out std_logic + ); +end component; end package; \ No newline at end of file diff --git a/source/soda_hub.vhd b/source/soda_hub.vhd index dec3e52..e4ad825 100644 --- a/source/soda_hub.vhd +++ b/source/soda_hub.vhd @@ -11,35 +11,35 @@ use work.soda_components.all; entity soda_hub is port( - SYSCLK : in std_logic; -- fabric clock - SODACLK : in std_logic; -- recovered clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- recovered clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; -- SINGLE DUBPLEX UP-LINK TO THE TOP RXUP_DLM_IN : in std_logic; RXUP_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); - TXUP_DLM_OUT : out std_logic; + TXUP_DLM_OUT : out std_logic; TXUP_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0'); TXUP_DLM_PREVIEW_OUT : out std_logic := '0'; --PL! - UPLINK_PHASE_IN : in std_logic := '0'; --PL! + UPLINK_PHASE_IN : in std_logic := '0'; --PL! -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM - RXDN_DLM_IN : in t_HUB_DLM; - RXDN_DLM_WORD_IN : in t_HUB_DLM_BYTE; - TXDN_DLM_OUT : out t_HUB_DLM; - TXDN_DLM_WORD_OUT : out t_HUB_DLM_BYTE; - TXDN_DLM_PREVIEW_OUT : out t_HUB_DLM; --PL! - DNLINK_PHASE_IN : in t_HUB_DLM; --PL! + RXDN_DLM_IN : in t_HUB_BIT; + RXDN_DLM_WORD_IN : in t_HUB_BYTE; + TXDN_DLM_OUT : out t_HUB_BIT; + TXDN_DLM_WORD_OUT : out t_HUB_BYTE; + TXDN_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL! + DNLINK_PHASE_IN : in t_HUB_BIT; --PL! - SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0'); - SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); - SODA_READ_IN : in std_logic := '0'; + SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + SODA_READ_IN : in std_logic := '0'; SODA_WRITE_IN : in std_logic := '0'; - SODA_ACK_OUT : out std_logic := '0'; - LEDS_OUT : out std_logic_vector(3 downto 0); + SODA_ACK_OUT : out std_logic := '0'; + LEDS_OUT : out std_logic_vector(3 downto 0); LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0') ); end soda_hub; @@ -110,19 +110,19 @@ begin hub_reply_packet_builder : soda_reply_pkt_builder port map( - SODACLK => SODACLK, - RESET => RESET, - CLEAR => '0', - CLK_EN => CLK_EN, + SODACLK => SODACLK, + RESET => RESET, + CLEAR => '0', + CLK_EN => CLK_EN, --Internal Connection LINK_PHASE_IN => UPLINK_PHASE_IN, START_OF_SUPERBURST => start_of_superburst_S, SUPER_BURST_NR_IN => super_burst_nr_S, - SODA_CMD_STROBE_IN => soda_cmd_valid_S, + SODA_CMD_STROBE_IN => soda_cmd_valid_S, SODA_CMD_WORD_IN => soda_cmd_word_S, - TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT, - TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT, - TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT + TX_DLM_PREVIEW_OUT => TXUP_DLM_PREVIEW_OUT, + TX_DLM_OUT => txup_dlm_out_S, --TX_DLM_OUT, + TX_DLM_WORD_OUT => TXUP_DLM_WORD_OUT ); channel :for i in c_HUB_CHILDREN-1 downto 0 generate @@ -131,17 +131,18 @@ begin packet_builder : soda_packet_builder port map( - SODACLK => SODACLK, - RESET => RESET, + SODACLK => SODACLK, + RESET => RESET, --Internal Connection SODA_CMD_STROBE_IN => soda_cmd_valid_S, START_OF_SUPERBURST => start_of_superburst_S, SUPER_BURST_NR_IN => super_burst_nr_S, SODA_CMD_WORD_IN => soda_cmd_word_S, - EXPECTED_REPLY_OUT => open, - TIME_CAL_OUT => open, --start_calibration_S(i), - TX_DLM_OUT => TXDN_DLM_OUT(i), - TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i) + EXPECTED_REPLY_OUT => open, + TIME_CAL_OUT => open, --start_calibration_S(i), + TX_DLM_PREVIEW_OUT => TXDN_DLM_PREVIEW_OUT(i), + TX_DLM_OUT => TXDN_DLM_OUT(i), + TX_DLM_WORD_OUT => TXDN_DLM_WORD_OUT(i) ); hub_reply_handler : soda_reply_handler @@ -375,4 +376,4 @@ end process TRANSFORM; SODA_DATA_OUT <= buf_bus_data_out; SODA_ACK_OUT <= bus_ack; -end architecture; \ No newline at end of file +end architecture; diff --git a/source/trb3_periph_sodaclient.vhd b/source/trb3_periph_sodaclient.vhd index 2971a3f..6d5203e 100644 --- a/source/trb3_periph_sodaclient.vhd +++ b/source/trb3_periph_sodaclient.vhd @@ -1,7 +1,7 @@ ---------------- --- TOP LEVEL -- --------------- - +-- TOP LEVEL -- +--------------- + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; @@ -189,6 +189,8 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is signal sci1_data_out : std_logic_vector(7 downto 0); signal sci1_addr : std_logic_vector(8 downto 0); signal sci1_nack : std_logic; + signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); + --SODA signal soda_rx_clock_half : std_logic; @@ -215,7 +217,7 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is signal general_reset_i : std_logic := '1'; signal soda_counter_i : unsigned(3 downto 0); - attribute syn_keep of soda_counter_i : signal is true; + attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining attribute syn_preserve of soda_rx_clock_full : signal is true; attribute syn_keep of soda_rx_clock_full : signal is true; @@ -239,13 +241,13 @@ begin --------------------------------------------------------------------------- -- Reset Generation --------------------------------------------------------------------------- - - - TEST_LINE <= (others => '0'); -- otherwise it is floating + + + TEST_LINE <= (others => '0'); -- otherwise it is floating LED_RX <= (others => '0'); -- otherwise it is floating LED_TX <= (others => '0'); -- otherwise it is floating LED_LINKOK <= (others => '0'); -- otherwise it is floating - + GSR_N <= pll_lock; THE_RESET_HANDLER : trb_net_reset_handler @@ -558,7 +560,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up SD_REFCLK_N_IN => '0', SD_PRSNT_N_IN => SFP_MOD0(1), SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TXDIS(1), + SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1), SCI_DATA_IN => sci1_data_in, SCI_DATA_OUT => sci1_data_out, @@ -575,13 +577,16 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up ); +-- SFP_TXDIS(1) <= sfp_txdis_S(1); + SFP_TXDIS <= sfp_txdis_S; + --------------------------------------------------------------------------- -- The Soda Central --------------------------------------------------------------------------- - + A_SODA_CLIENT : soda_client port map( - SYSCLK => clk_sys_internal, --clk_sys_i, + SYSCLK => clk_sys_internal, --clk_sys_i, SODACLK => clk_soda_i, RESET => reset_i, CLEAR => clear_i, @@ -599,7 +604,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, SODA_ACK_OUT => soda_ack, - LEDS_OUT => soda_leds, + LEDS_OUT => soda_leds, LINK_DEBUG_IN => link_debug_in_S ); @@ -607,10 +612,10 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= med_stat_op(8); - LED_YELLOW <= med_stat_op(10); - LED_GREEN <= med_stat_op(9); - LED_RED <= med_stat_op(6); + LED_ORANGE <= SFP_LOS(1); --med_stat_op(8); + LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); + LED_GREEN <= med_stat_op(12); --tx_pll_lol + LED_RED <= med_stat_op(11); --rx_cdr_lol -- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal); -- LED_YELLOW <= soda_leds(0); --'1'; -- LED_GREEN <= not med_stat_op(9); @@ -621,7 +626,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up -- LED_RED <= soda_leds(3); --------------------------------------------------------------------------- --- DEBUG +-- DEBUG --------------------------------------------------------------------------- link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0); link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0'); @@ -629,9 +634,9 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up -- Test Circuits --------------------------------------------------------------------------- clock_counter_proc : process(clk_sys_internal) - begin + begin if rising_edge(clk_sys_internal) then - time_counter <= time_counter + 1; + time_counter <= time_counter + 1; end if; end process; @@ -643,4 +648,4 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up end process; -end trb3_periph_sodaclient_arch; +end trb3_periph_sodaclient_arch; \ No newline at end of file diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd index 22c620e..6499977 100644 --- a/source/trb3_periph_sodasource.vhd +++ b/source/trb3_periph_sodasource.vhd @@ -77,125 +77,126 @@ entity trb3_periph_sodasource is ); - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - attribute syn_useioff of CODE_LINE : signal is false; - attribute syn_useioff of LED_LINKOK : signal is false; - attribute syn_useioff of LED_TX : signal is false; - attribute syn_useioff of LED_RX : signal is false; - attribute syn_useioff of SFP_MOD0 : signal is false; - attribute syn_useioff of SFP_TXDIS : signal is false; - attribute syn_useioff of SFP_LOS : signal is false; - attribute syn_useioff of TEST_LINE : signal is false; - - --important signals _with_ IO-FF - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of LED_LINKOK : signal is false; + attribute syn_useioff of LED_TX : signal is false; + attribute syn_useioff of LED_RX : signal is false; + attribute syn_useioff of SFP_MOD0 : signal is false; + attribute syn_useioff of SFP_TXDIS : signal is false; + attribute syn_useioff of SFP_LOS : signal is false; + attribute syn_useioff of TEST_LINE : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; end entity; architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is - --Constants - constant REGIO_NUM_STAT_REGS : integer := 0; - constant REGIO_NUM_CTRL_REGS : integer := 2; - - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - constant USE_200_MHZ : integer := 1 - USE_125_MHZ; - - --Clock / Reset --- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL --- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - signal clk_sys_internal : std_logic; - signal clk_raw_internal : std_logic; - signal rx_clock_half : std_logic; - signal rx_clock_full : std_logic; - signal clk_tdc : std_logic; - signal time_counter, time_counter2 : unsigned(31 downto 0); - --Media Interface - signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); - signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0); - signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0); - signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); - signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); - signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0); - signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); - signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); - - --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - - --RegIO - signal my_address : std_logic_vector (15 downto 0); - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - - --Flash - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(8 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_dataready_out : std_logic; - signal spimem_no_more_data_out : std_logic; - signal spimem_unknown_addr_out : std_logic; - signal spimem_write_ack_out : std_logic; - - signal sci1_ack : std_logic; - signal sci1_write : std_logic; - signal sci1_read : std_logic; - signal sci1_data_in : std_logic_vector(7 downto 0); - signal sci1_data_out : std_logic_vector(7 downto 0); - signal sci1_addr : std_logic_vector(8 downto 0); - signal sci2_ack : std_logic; - signal sci2_nack : std_logic; - signal sci2_write : std_logic; - signal sci2_read : std_logic; - signal sci2_data_in : std_logic_vector(7 downto 0); - signal sci2_data_out : std_logic_vector(7 downto 0); - signal sci2_addr : std_logic_vector(8 downto 0); + --Constants + constant REGIO_NUM_STAT_REGS : integer := 0; + constant REGIO_NUM_CTRL_REGS : integer := 2; + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + constant USE_200_MHZ : integer := 1 - USE_125_MHZ; + + --Clock / Reset + -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + signal clk_sys_internal : std_logic; + signal clk_raw_internal : std_logic; + signal rx_clock_half : std_logic; + signal rx_clock_full : std_logic; + signal clk_tdc : std_logic; + signal time_counter, time_counter2 : unsigned(31 downto 0); + --Media Interface + signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0); + signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0); + signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0); + signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0); + + --Slow Control channel + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + + --RegIO + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Flash + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(8 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_dataready_out : std_logic; + signal spimem_no_more_data_out : std_logic; + signal spimem_unknown_addr_out : std_logic; + signal spimem_write_ack_out : std_logic; + + signal sci1_ack : std_logic; + signal sci1_write : std_logic; + signal sci1_read : std_logic; + signal sci1_data_in : std_logic_vector(7 downto 0); + signal sci1_data_out : std_logic_vector(7 downto 0); + signal sci1_addr : std_logic_vector(8 downto 0); + signal sci2_ack : std_logic; + signal sci2_nack : std_logic; + signal sci2_write : std_logic; + signal sci2_read : std_logic; + signal sci2_data_in : std_logic_vector(7 downto 0); + signal sci2_data_out : std_logic_vector(7 downto 0); + signal sci2_addr : std_logic_vector(8 downto 0); + signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); --SODA signal soda_ack : std_logic; @@ -205,19 +206,19 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal soda_data_out : std_logic_vector(31 downto 0); signal soda_addr : std_logic_vector(3 downto 0); signal soda_leds : std_logic_vector(3 downto 0); - + --TDC - signal hit_in_i : std_logic_vector(63 downto 0); - - signal soda_rx_clock_half : std_logic; - signal soda_rx_clock_full : std_logic; - signal soda_tx_clock_half : std_logic; - signal soda_tx_clock_full : std_logic; - signal tx_dlm_i : std_logic; - signal rx_dlm_i : std_logic; - signal tx_dlm_word : std_logic_vector(7 downto 0); - signal rx_dlm_word : std_logic_vector(7 downto 0); + signal hit_in_i : std_logic_vector(63 downto 0); + + signal soda_rx_clock_half : std_logic; + signal soda_rx_clock_full : std_logic; + signal soda_tx_clock_half : std_logic; + signal soda_tx_clock_full : std_logic; + signal tx_dlm_i : std_logic; + signal rx_dlm_i : std_logic; + signal tx_dlm_word : std_logic_vector(7 downto 0); + signal rx_dlm_word : std_logic_vector(7 downto 0); signal tx_dlm_preview_S : std_logic; --PL! signal link_phase_S : std_logic; --PL! @@ -236,7 +237,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is attribute syn_preserve of CLK_PCLK_RIGHT : signal is true; attribute syn_keep of CLK_PCLK_RIGHT : signal is true; -- attribute syn_noprune of CLK_PCLK_RIGHT : signal is true; - + attribute syn_preserve of soda_rx_clock_full : signal is true; attribute syn_keep of soda_rx_clock_full : signal is true; attribute syn_preserve of soda_rx_clock_half : signal is true; @@ -339,8 +340,8 @@ end generate; MED_DATAREADY_OUT => med_dataready_in(0), MED_READ_IN => med_read_out(0), REFCLK2CORE_OUT => open, - CLK_RX_HALF_OUT => rx_clock_half, - CLK_RX_FULL_OUT => rx_clock_full, + CLK_RX_HALF_OUT => open, --rx_clock_half, + CLK_RX_FULL_OUT => open, --rx_clock_full, --SFP Connection SD_RXD_P_IN => SERDES_ADDON_RX(2), @@ -560,8 +561,8 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down CLK => clk_raw_internal, --clk_200_i, SYSCLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, - CLEAR => clear_i, --- PCSA_REFCLKP => PCSA_REFCLKP, -- external refclock straight into serdes PL! + CLEAR => clear_i, +-- PCSA_REFCLKP => PCSA_REFCLKP, -- external refclock straight into serdes PL! -- PCSA_REFCLKN => PCSA_REFCLKN, -- external refclock straight into serdes PL! --Internal Connection for TrbNet data -> not used a.t.m. MED_DATA_IN => med_data_out(31 downto 16), @@ -580,9 +581,9 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down RX_DLM => rx_dlm_i, RX_DLM_WORD => rx_dlm_word, TX_DLM => tx_dlm_i, - TX_DLM_WORD => tx_dlm_word, - TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL! - LINK_PHASE_OUT => link_phase_S, --PL! + TX_DLM_WORD => tx_dlm_word, + TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL! + LINK_PHASE_OUT => link_phase_S, --PL! --SFP Connection SD_RXD_P_IN => SERDES_ADDON_RX(0), SD_RXD_N_IN => SERDES_ADDON_RX(1), @@ -592,7 +593,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down SD_REFCLK_N_IN => '0', SD_PRSNT_N_IN => SFP_MOD0(1), SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TXDIS(1), + SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1), SCI_DATA_IN => sci2_data_in, SCI_DATA_OUT => sci2_data_out, @@ -608,14 +609,19 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down CTRL_DEBUG => (others => '0') ); - + SFP_TXDIS(1) <= sfp_txdis_S(1); + --------------------------------------------------------------------------- -- The Soda Central --------------------------------------------------------------------------- -THE_SOB_SOURCE : soda_start_of_burst_faker +THE_SOB_SOURCE : soda_start_of_burst_faker + generic map( + CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns + BURST_PERIOD => cBURST_PERIOD -- burst-period in ns + ) port map( - SYSCLK => clk_raw_internal, --soda_rx_clock_half, -- + SYSCLK => clk_sys_internal, --soda_rx_clock_half, -- RESET => reset_i, SODA_BURST_PULSE_OUT => SOB_S ); @@ -644,16 +650,32 @@ THE_SODA_SOURCE : soda_source SODA_ACK_OUT => soda_ack, LEDS_OUT => soda_leds ); - + + +--alive : soda_clockscaler +-- port map( +-- CLK => clk_raw_internal, +-- RESET => reset_i, +-- CLOCK_ENABLE_OUT => open, +-- CLOCK_OUT => LED_GREEN +-- ); + +--rx_alive : soda_clockscaler +-- port map( +-- CLK => soda_rx_clock_full, +-- RESET => reset_i, +-- CLOCK_ENABLE_OUT => open, +-- CLOCK_OUT => LED_RED +-- ); --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= med_stat_op(16+8); - LED_YELLOW <= med_stat_op(16+10); - LED_GREEN <= med_stat_op(16+9); - LED_RED <= med_stat_op(16+6); + LED_ORANGE <= SFP_LOS(1); --med_stat_op(8); + LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); + LED_GREEN <= med_stat_op(12); --tx_pll_lol + LED_RED <= med_stat_op(11); --rx_cdr_lol -- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal); -- LED_YELLOW <= soda_leds(0); --'1'; -- LED_GREEN <= not med_stat_op(9); @@ -679,4 +701,4 @@ THE_SODA_SOURCE : soda_source -end trb3_periph_sodasource_arch; +end trb3_periph_sodasource_arch; \ No newline at end of file diff --git a/trb3_soda_client.xcf b/trb3_soda_client.xcf new file mode 100644 index 0000000..4b65926 --- /dev/null +++ b/trb3_soda_client.xcf @@ -0,0 +1,228 @@ + + + + + + JTAG + + + 1 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit + 09/24/13 10:52:51 + Bypass + + + + + 2 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140325.bit + 03/26/14 14:07:54 + Fast Program + + + + + 3 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit + 09/03/13 16:32:30 + N/A + Bypass + + + + + 4 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit + 04/10/13 14:12:21 + N/A + Bypass + + + + + 5 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodasource_20140325.bit + 03/26/14 09:09:00 + N/A + Fast Program + + + + + 6 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed + 04/10/13 09:35:41 + 0x1C57 + Erase,Program,Verify + + + + + 7 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + USB + EzUSB-0 + + diff --git a/trb3_soda_dual_client.xcf b/trb3_soda_dual_client.xcf new file mode 100644 index 0000000..c0d5af8 --- /dev/null +++ b/trb3_soda_dual_client.xcf @@ -0,0 +1,224 @@ + + + + + + JTAG + + + 1 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + 2 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140121.bit + 01/21/14 11:21:53 + Fast Program + + + + + 3 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + 4 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + 5 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140121.bit + 01/21/14 11:21:53 + N/A + Fast Program + + + + + 6 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/trb3/base/clockmanager/CM1.jed + 04/10/13 09:35:41 + 0x1C8C + Erase,Program,Verify + + + + + 7 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + USB + EzUSB-0 + + TRST HIGH; + ISPEN HIGH; + + + + + diff --git a/trb3_soda_hub.xcf b/trb3_soda_hub.xcf new file mode 100644 index 0000000..0ce5e3e --- /dev/null +++ b/trb3_soda_hub.xcf @@ -0,0 +1,228 @@ + + + + + + JTAG + + + 1 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit + 09/24/13 10:52:51 + Bypass + + + + + 2 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodahub_20140320.bit + 03/20/14 12:21:09 + Fast Program + + + + + 3 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit + 09/03/13 16:32:30 + N/A + Bypass + + + + + 4 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit + 04/10/13 14:12:21 + N/A + Bypass + + + + + 5 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodasource_20140320.bit + 03/18/14 15:42:08 + N/A + Fast Program + + + + + 6 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed + 04/10/13 09:35:41 + 0x1C57 + Erase,Program,Verify + + + + + 7 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + USB + EzUSB-0 + + diff --git a/trb3_soda_source.xcf b/trb3_soda_source.xcf new file mode 100644 index 0000000..a0368f7 --- /dev/null +++ b/trb3_soda_source.xcf @@ -0,0 +1,227 @@ + + + + + + JTAG + + + 1 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit + 09/24/13 10:52:51 + Bypass + + + + + 2 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140414.bit + 04/14/14 11:17:17 + Fast Program + + + + + 3 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit + 09/03/13 16:32:30 + N/A + Bypass + + + + + 4 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit + 04/10/13 14:12:21 + N/A + Bypass + + + + + 5 + Lattice + LatticeECP3 + LFE3-150EA + 0x01015043 + All + LFE3-150EA + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/soda/trb3_periph_sodasource_20140414.bit + 04/14/14 11:19:05 + N/A + Fast Program + + + + + 6 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + /local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed + 04/10/13 09:35:41 + 0x1C57 + Erase,Program,Verify + + + + + 7 + Lattice + ispCLOCK + ispPAC-CLK5410D + 0x00190043 + 64-pin QFNS + ispPAC-CLK5410D-XXSN64C + + 8 + 11111111 + 1 + 0 + + Bypass + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + + + USB + EzUSB-0 + + -- 2.43.0