From 668c90f658117a5fbdd0f7efc27f48858fa34778 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Thu, 5 Mar 2015 17:32:13 +0100 Subject: [PATCH] add specific multicycle to config register --- ADC/trb3_periph_adc_constraints.lpf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 0344ab3..d6fccd7 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -91,6 +91,9 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_LEFT/clk_data_c" TO CLKNET "P_CLOCK_c" 2 X; #MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_RIGHT/clk_data" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; +MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_adc*" 4 X; + + # we define everything doubled to make it work with all lattice/synplify versions # due to _ vs . notation of generate statements args... -- 2.43.0