From 66b2b839cc6f21bfd2b92882e9bd6b79880263cf Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 4 Jun 2009 17:00:06 +0000 Subject: [PATCH] *** empty log message *** --- trb_net16_hub_func.vhd | 396 ------------------- trb_net16_hub_ipu_logic.vhd | 75 +--- trb_net_components.vhd | 742 +++++++++++++++++++++++++++++++++++- 3 files changed, 727 insertions(+), 486 deletions(-) diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index f831c8f..165a400 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -78,402 +78,6 @@ package trb_net16_hub_func is function VAL(i : integer) return integer; - component trb_net16_hub_logic is - generic ( - --media interfaces - POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - STAT : out std_logic_vector (15 downto 0); - STAT_POINTS_locked : out std_logic_vector (31 downto 0); - STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); - CTRL_activepoints : in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_hub_ipu_logic is - generic ( - POINT_NUMBER : integer range 2 to 32 := 3 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - --Internal interfaces to IOBufs - INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); - REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); - REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - --Status ports - STAT_DEBUG : out std_logic_vector (31 downto 0); - STAT_POINTS_locked : out std_logic_vector (31 downto 0); - STAT_ERRORBITS : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (15 downto 0); - CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') - ); - end component; - - component trb_net16_io_multiplexer is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in STD_LOGIC; - MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out STD_LOGIC; - MED_DATAREADY_OUT : out STD_LOGIC; - MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in STD_LOGIC; - -- Internal direction port - INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL : in STD_LOGIC_VECTOR (31 downto 0); - STAT : out STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - component trb_net16_iobuf is - generic ( - IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN : in std_logic; - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - -- Status and control port - STAT_GEN : out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0); - STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); - STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) - ); - end component; - - - component trb_net16_api_base is - generic ( - API_TYPE : integer range 0 to 1 := c_API_PASSIVE; - FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; - FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; - FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; - SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; - APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; - BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" - ); - - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - -- APL Transmitter port - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_DATAREADY_IN : in std_logic; - APL_READ_OUT : out std_logic; - APL_SHORT_TRANSFER_IN : in std_logic; - APL_DTYPE_IN : in std_logic_vector (3 downto 0); - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - APL_SEND_IN : in std_logic; - APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) - -- Receiver port - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - APL_TYP_OUT : out std_logic_vector (2 downto 0); - APL_DATAREADY_OUT : out std_logic; - APL_READ_IN : in std_logic; - -- APL Control port - APL_RUN_OUT : out std_logic; - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - APL_LENGTH_IN : in std_logic_vector (15 downto 0); - -- Internal direction port - -- the ports with master or slave in their name are to be mapped by the active api - -- to the init respectivly the reply path and vice versa in the passive api. - -- lets define: the "master" path is the path that I send data on. - -- master_data_out and slave_data_in are only used in active API for termination - INT_MASTER_DATAREADY_OUT : out std_logic; - INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_IN : in std_logic; - INT_MASTER_DATAREADY_IN : in std_logic; - INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_MASTER_READ_OUT : out std_logic; - INT_SLAVE_DATAREADY_OUT : out std_logic; - INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_IN : in std_logic; - INT_SLAVE_DATAREADY_IN : in std_logic; - INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_SLAVE_READ_OUT : out std_logic; - -- Status and control port - STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); - STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := c_YES; - --even when 0, ERROR_PACKET_IN is used for automatic replys - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these need to be available while relase_trg is high - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - -- "mini" APL, just to see terminations coming in - APL_DTYPE_OUT : out std_logic_vector (3 downto 0); - APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); - APL_SEQNR_OUT : out std_logic_vector (7 downto 0); - APL_GOT_TRM : out std_logic; - APL_RELEASE_TRM : in std_logic; - APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) - ); - end component; - - component trb_net16_regIO is - generic ( - NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers - NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers - --standard values for output registers - INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); - --set to 0 for unused ctrl registers to save resources - USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; - --set to 0 for each unused bit in a register - USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); - USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - CLOCK_FREQ : integer range 1 to 200 := 100 --MHz - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - - --Port to write Unique ID (-> 1-wire) - IDRAM_DATA_IN : in std_logic_vector(15 downto 0); - IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); - IDRAM_WR_IN : in std_logic; - - --Informations - MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - TRIGGER_MONITOR : in std_logic; - GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds - LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency - TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_US_TICK : out std_logic; --1 tick every microsecond - - --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); - --Custom Register in / out - REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); - --Internal Data Port - DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - DAT_READ_ENABLE_OUT : out std_logic; - DAT_WRITE_ENABLE_OUT: out std_logic; - DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - DAT_DATAREADY_IN : in std_logic; - DAT_NO_MORE_DATA_IN : in std_logic; - DAT_WRITE_ACK_IN : in std_logic; - DAT_UNKNOWN_ADDR_IN : in std_logic; - DAT_TIMEOUT_OUT : out std_logic; - - --Additional write access to ctrl registers - STAT : out std_logic_vector(31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) - ); - end component; - - component trb_net16_term_buf is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic - ); - end component; - - component trb_net_onewire is - generic( - USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; - CLK_PERIOD : integer := 10 --clk period in ns - ); - port( - CLK : in std_logic; - RESET : in std_logic; - --connection to 1-wire interface - ONEWIRE : inout std_logic; - MONITOR_OUT : out std_logic; - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - component trb_net_onewire_listener is - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - MONITOR_IN : in std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - end package trb_net16_hub_func; diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 76e3bbd..8fb5bdd 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -4,6 +4,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_hub_ipu_logic is @@ -53,80 +54,6 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is -- for whole architecture attribute HGROUP of trb_net16_hub_ipu_logic_arch : architecture is "HUBIPULOGIC_group"; - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - component trb_net_priority_arbiter is - generic ( - WIDTH : integer := POINT_NUMBER - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL : in STD_LOGIC_VECTOR (9 downto 0) - ); - end component; - - component ram_dp_rw - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); - end component; - - component wide_adder_17x16 is - generic( - SIZE : integer := 16; - WORDS: integer := 17 --fixed - ); - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); - START_IN : in std_logic; - VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); - RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); - OVERFLOW_OUT : out std_logic; - READY_OUT : out std_logic - ); - end component; - - --signals init_pool signal INIT_POOL_DATAREADY : std_logic; signal INIT_POOL_READ : std_logic; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 892c1b7..8d9e4c0 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -7,6 +7,117 @@ use work.trb_net_std.all; package trb_net_components is +--This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names + + + + + + component adc_ltc2308_readout is + generic( + CLOCK_FREQUENCY : integer := 100 --MHz + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + ADC_SCK : out std_logic; + ADC_SDI : out std_logic; + ADC_SDO : in std_logic; + ADC_CONVST : out std_logic; + + DAT_ADDR_IN : in std_logic_vector(5 downto 0); + DAT_READ_EN_IN : in std_logic; + DAT_WRITE_EN_IN : in std_logic; + DAT_DATA_OUT : out std_logic_vector(31 downto 0); + DAT_DATA_IN : in std_logic_vector(31 downto 0); + DAT_DATAREADY_OUT : out std_logic; + DAT_NO_MORE_DATA_OUT : out std_logic; + DAT_WRITE_ACK_OUT : out std_logic; + DAT_UNKNOWN_ADDR_OUT : out std_logic; + DAT_TIMEOUT_IN : in std_logic; + + STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_LENGTH_IN : in std_logic_vector (15 downto 0); + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + component trb_net16_dummy_fifo is port ( CLK : in std_logic; @@ -23,6 +134,137 @@ package trb_net_components is ); end component; + + + + + component trb_net16_endpoint_hades_full is + generic ( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + IBUF_DEPTH : channel_config_t := (1,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (1,1,1,1); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR + CLOCK_FREQUENCY : integer range 1 to 200 := 100 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + -- LVL1 trigger APL + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + + + --Data Port + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT: out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + REGIO_IDRAM_WR_IN : in std_logic := '0'; + REGIO_ONEWIRE_INOUT : inout std_logic; + REGIO_ONEWIRE_MONITOR_IN : in std_logic; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + + TRIGGER_MONITOR_IN : in std_logic; --strobe when timing trigger received + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond + + --Debugging & Status information + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + MED_STAT_OP : out std_logic_vector (15 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0) + ); + end component; + + + component trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; @@ -43,6 +285,411 @@ package trb_net_components is ); end component; + + + component trb_net16_hub_ipu_logic is + generic ( + POINT_NUMBER : integer range 2 to 32 := 3 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + --Internal interfaces to IOBufs + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + --Status ports + STAT_DEBUG : out std_logic_vector (31 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1') + ); + end component; + + + + component trb_net16_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to c_MAX_POINTS_PER_HUB := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_HEADER_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + STAT : out std_logic_vector (15 downto 0); + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) + ); + end component; + + + + + + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + -- Status and control port + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) + ); + end component; + + + + + component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in STD_LOGIC; + MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out STD_LOGIC; + MED_DATAREADY_OUT : out STD_LOGIC; + MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in STD_LOGIC; + -- Internal direction port + INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL : in STD_LOGIC_VECTOR (31 downto 0); + STAT : out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + + + + + component trb_net16_med_ecp_fot is + port( + CLK : in std_logic; + CLK_25 : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + --SFP Connection + TXP : out std_logic; + TXN : out std_logic; + RXP : in std_logic; + RXN : in std_logic; + SD : in std_logic; + + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); + end component; + + + + + component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + MONITOR_OUT : out std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component trb_net_onewire_listener is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + MONITOR_IN : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + component pll_in25_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; + + + + + + + component trb_net_priority_arbiter is + generic ( + WIDTH : integer := POINT_NUMBER + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + ENABLE : in std_logic; + CTRL : in STD_LOGIC_VECTOR (9 downto 0) + ); + end component; + + + + + + component ram_dp is + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + dout1 : out std_logic_vector(width-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); + end component; + + + + + component ram_dp_rw + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); + end component; + + + + + component trb_net16_regIO is + generic ( + NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQ : integer range 1 to 200 := 100 --MHz + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + + --Port to write Unique ID (-> 1-wire) + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + + --Informations + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + TRIGGER_MONITOR : in std_logic; + GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK : out std_logic; --1 tick every microsecond + + --Common Register in / out + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); + --Custom Register in / out + REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + --Internal Data Port + DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + DAT_NO_MORE_DATA_IN : in std_logic; + DAT_WRITE_ACK_IN : in std_logic; + DAT_UNKNOWN_ADDR_IN : in std_logic; + DAT_TIMEOUT_OUT : out std_logic; + + --Additional write access to ctrl registers + STAT : out std_logic_vector(31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) + ); + end component; + + + + + component trb_net16_sbuf is generic ( VERSION : integer := 0 @@ -68,6 +715,35 @@ package trb_net_components is ); end component; + + + + + component trb_net_sbuf is + generic ( + DATA_WIDTH : integer := 18; + VERSION: integer := std_SBUF_VERSION); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + + + + component trb_net16_term is generic ( USE_APL_PORT : integer range 0 to 1 := c_YES; @@ -81,41 +757,75 @@ package trb_net_components is CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - INT_DATAREADY_OUT : out std_logic; INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_IN : in std_logic; - INT_DATAREADY_IN : in std_logic; INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_READ_OUT : out std_logic; - + -- "mini" APL, just to see terminations coming in + APL_DTYPE_OUT : out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_GOT_TRM : out std_logic; + APL_RELEASE_TRM : in std_logic; APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) ); end component; - component trb_net_sbuf is - generic ( - DATA_WIDTH : integer := 18; - VERSION: integer := std_SBUF_VERSION); + + + + + component trb_net16_term_buf is port( -- Misc CLK : in std_logic; RESET : in std_logic; CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic ); end component; + + + + + + component wide_adder_17x16 is + generic( + SIZE : integer := 16; + WORDS: integer := 17 --fixed + ); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); + START_IN : in std_logic; + VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); + RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); + OVERFLOW_OUT : out std_logic; + READY_OUT : out std_logic + ); + end component; + + + + + end package; \ No newline at end of file -- 2.43.0