From 673e707b6969c539a262bc7ae5eb5507af269d64 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 15 Dec 2022 11:53:40 +0100 Subject: [PATCH] add bus master input to accel hub --- trb_net16_hub_streaming_port_sctrl_accel.vhd | 13 +++++-- trb_net_components.vhd | 40 ++++++++++++++++++++ 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/trb_net16_hub_streaming_port_sctrl_accel.vhd b/trb_net16_hub_streaming_port_sctrl_accel.vhd index b93a2cd..9f525eb 100644 --- a/trb_net16_hub_streaming_port_sctrl_accel.vhd +++ b/trb_net16_hub_streaming_port_sctrl_accel.vhd @@ -95,7 +95,10 @@ entity trb_net16_hub_streaming_port_sctrl_record is BUS_RX : out CTRLBUS_RX; BUS_TX : in CTRLBUS_TX; TIMER : out TIMERS; - + --Data port - external master (e.g. Flash or Debug) + BUS_MASTER_IN : out CTRLBUS_TX; + BUS_MASTER_OUT : in CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0'); + BUS_MASTER_ACTIVE : in std_logic := '0'; --Gbe Sctrl Input GSC_INIT_DATAREADY_IN : in std_logic; GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0); @@ -176,7 +179,7 @@ signal HUB_MED_CTRL_OP : std_logic_vector(mii*16-1 downto 0); signal reset_i_mux_io : std_logic; signal hub_make_network_reset : std_logic := '0'; -signal hub_got_network_reset : std_logic; +signal hub_got_network_reset : std_logic; signal timer_i : TIMERS; signal timer_ticks : std_logic_vector(1 downto 0); signal hub_ctrl_debug : std_logic_vector(31 downto 0); @@ -334,7 +337,9 @@ end generate; REGIO_WRITE_ACK_IN => wrack, REGIO_UNKNOWN_ADDR_IN => hubbus_tx.unknown, REGIO_TIMEOUT_OUT => hubbus_rx.timeout, - + BUS_MASTER_IN => BUS_MASTER_IN, + BUS_MASTER_OUT => BUS_MASTER_OUT, + BUS_MASTER_ACTIVE => BUS_MASTER_ACTIVE, TIMER_TICKS_OUT(0) => timer_i.tick_us, TIMER_TICKS_OUT(1) => timer_i.tick_ms, ONEWIRE => ONEWIRE, @@ -356,7 +361,7 @@ end generate; hub_ctrl_debug(2 downto 0) <= not io_error_in; hub_ctrl_debug(31 downto 3) <= (others => '0'); HUB_STAT_GEN <= buf_HUB_STAT_GEN; - timer_ticks <= timer_i.tick_ms & timer_i.tick_us; + timer_ticks <= timer_i.tick_ms & timer_i.tick_us; TIMER <= timer_i; --------------------------------------------------------------------- diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 113169a..ccd835e 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -3672,4 +3672,44 @@ end component; ); end component trb_net_xdna; +component i2c_slim2 is +port( + CLOCK : in std_logic; + RESET : in std_logic; + -- I2C command / setup + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + WORD_IN : in std_logic; -- '0' -> byte, '1' -> word + DIRECT_IN : in std_logic; -- '0' -> normal access, '1' -> direct read + I2C_SPEED_IN : in std_logic_vector(5 downto 0); -- speed adjustment (to be defined) + I2C_ADDR_IN : in std_logic_vector(7 downto 0); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector(7 downto 0); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector(15 downto 0); -- data word for write command + I2C_DR_OUT : out std_logic_vector(15 downto 0); -- data word from read command + STATUS_OUT : out std_logic_vector(7 downto 0); -- status and error bits + VALID_OUT : out std_logic; + I2C_BUSY_OUT : out std_logic; + I2C_DONE_OUT : out std_logic; + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Debug + BSM_OUT : out std_logic_vector(3 downto 0) +); +end component; + +component common_i2c is + port( + CLOCK : in std_logic; + RESET : in std_logic; + SDA : inout std_logic; + SCL : inout std_logic; + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end component; + + end package; -- 2.43.0