From 677c32443640f4607d32dff6ecb2ab827cf26b8c Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 11 May 2017 13:31:26 +0200 Subject: [PATCH] Update blank design with dummy data sender --- blank/config_compile_frankfurt.pl | 8 ++-- blank/trb3_periph_blank.vhd | 65 ++++++++++++++++++++++++++++--- 2 files changed, 64 insertions(+), 9 deletions(-) diff --git a/blank/config_compile_frankfurt.pl b/blank/config_compile_frankfurt.pl index 352158c..6d0c6cb 100644 --- a/blank/config_compile_frankfurt.pl +++ b/blank/config_compile_frankfurt.pl @@ -1,14 +1,14 @@ TOPNAME => "trb3_periph_blank", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.8_x64', -synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', +synplify_path => '/d/jspc29/lattice/synplify/M-2017.03/', #synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/bin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", -synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3/blank/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3_periph_blank.prj\" #", +#synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3/blank/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3_periph_blank.prj\" #", nodelist_file => 'nodes_frankfurt.txt', -pinout_file => 'trb3_periph_ada', +pinout_file => 'trb3_periph_gpin', #Include only necessary lpf files #pinout_file => '', #name of pin-out file, if not equal TOPNAME diff --git a/blank/trb3_periph_blank.vhd b/blank/trb3_periph_blank.vhd index 5820aaf..b0a0471 100644 --- a/blank/trb3_periph_blank.vhd +++ b/blank/trb3_periph_blank.vhd @@ -62,8 +62,7 @@ entity trb3_periph_blank is attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_useioff of TEST_LINE : signal is true; attribute syn_useioff of INP : signal is false; - - + end entity; @@ -111,6 +110,11 @@ architecture trb3_periph_blank_arch of trb3_periph_blank is attribute nopad : string; attribute nopad of serdes_i : signal is "true"; + type state_t is (IDLE, WRITE, FINISH, BUSYEND); + signal state : state_t; + signal data_counter, data_amount : unsigned(15 downto 0) := (others => '0'); + + begin --------------------------------------------------------------------------- -- Reset Generation @@ -377,9 +381,60 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record -- BUS_TX => busrdo_tx -- -- ); -readout_tx(0).data_finished <= '1'; -readout_tx(0).data_write <= '0'; -readout_tx(0).busy_release <= '1'; + +THE_RDO_STAT : process begin + wait until rising_edge(clk_100_i); + busrdo_tx.ack <= '0'; + busrdo_tx.nack <= '0'; + busrdo_tx.unknown <= '0'; + + if busrdo_rx.write = '1' then + if busrdo_rx.addr = x"0000" then + busrdo_tx.ack <= '1'; + data_amount <= unsigned(busrdo_rx.data(15 downto 0)); + else + busrdo_tx.unknown <= '1'; + end if; + elsif busrdo_rx.read = '1' then + if busrdo_rx.addr = x"0000" then + busrdo_tx.ack <= '1'; + busrdo_tx.data(15 downto 0) <= std_logic_vector(data_amount); + else + busrdo_tx.unknown <= '1'; + end if; + end if; +end process; + +THE_RDO : process begin + wait until rising_edge(clk_100_i); + readout_tx(0).busy_release <= '0'; + readout_tx(0).data_write <= '0'; + readout_tx(0).data_finished <= '0'; + + case state is + when IDLE => + if readout_rx.valid_timing_trg = '1' or readout_rx.valid_notiming_trg = '1' then + state <= WRITE; + end if; + if readout_rx.invalid_trg = '1' then + state <= FINISH; + end if; + data_counter <= 0; + when WRITE => + readout_tx(0).data <= timer.microsecond; + readout_tx(0).data_write <= '1'; + data_counter <= data_counter + 1; + if data_counter = data_amount then + state <= FINISH; + end if; + when FINISH => + state <= BUSYEND; + readout_tx(0).data_finished <= '1'; + when BUSYEND => + state <= IDLE; + readout_tx(0).busy_release <= '1'; + end case; +end process; end architecture; -- 2.43.0