From 67906ab466887859cd0b6e9ff01c2fc542847cd9 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 25 Apr 2017 21:30:34 +0200 Subject: [PATCH] uploaded extre files --- dirich/config.vhd | 14 ++++++++------ dirich/config_compile_gsi.pl | 2 +- dirich/dirich.prj | 2 ++ dirich/dirich.vhd | 8 +++----- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/dirich/config.vhd b/dirich/config.vhd index 222661e..30cc46c 100644 --- a/dirich/config.vhd +++ b/dirich/config.vhd @@ -10,20 +10,22 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ --TDC settings - constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + constant BOARD : string := "dirich"; -- Options: dirich, trb3 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, -- 3: same channel with stretcher - constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size -- mode: 0, 1, 2, 3, 7 -- size: 32, 64, 96, 128, dyn - constant TDC_DATA_FORMAT : integer range 0 to 3 := 15; --type of data format for the TDC + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC -- 0: Single fine time as the sum of the two transitions -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) -- 14: Debug - single fine time and the ROM addresses for the two transitions -- 15: Debug - complete carry chain dump diff --git a/dirich/config_compile_gsi.pl b/dirich/config_compile_gsi.pl index bbf3892..2125f1e 100644 --- a/dirich/config_compile_gsi.pl +++ b/dirich/config_compile_gsi.pl @@ -6,7 +6,7 @@ Speedgrade => '8', TOPNAME => "dirich", lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/opt/lattice/diamond/3.6_x64', +lattice_path => '/opt/lattice/diamond/3.8_x64', synplify_path => '/opt/synplicity/K-2015.09', #synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", diff --git a/dirich/dirich.prj b/dirich/dirich.prj index c943f56..5035fd1 100644 --- a/dirich/dirich.prj +++ b/dirich/dirich.prj @@ -205,6 +205,8 @@ add_file -vhdl -lib work "tdc_release/TDC_record.vhd" #add_file -vhdl -lib work "tdc_release/TDC.vhd" add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 06fe157..d4ff9fb 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -425,11 +425,9 @@ begin ); -- For single edge measurements - --gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - -- hit_in_i <= INPUT; - --end generate; - hit_in_i(1) <= INPUT(31); - hit_in_i(2) <= INPUT(32); + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INPUT; + end generate; -- For ToT Measurements gen_double : if DOUBLE_EDGE_TYPE = 2 generate -- 2.43.0