From 6837968cb66b1e1318beebfc5cd5c512943e29c1 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 26 May 2010 13:51:40 +0000 Subject: [PATCH] 26_05 --- gbe_ecp2m/tb_gbe_buf.vhd | 52 +++++-- gbe_ecp2m/trb_net16_gbe_buf.vhd | 21 ++- gbe_ecp2m/trb_net16_gbe_packet_constr.vhd | 4 +- gbe_ecp2m/trb_net16_gbe_setup.vhd | 5 +- gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd | 170 ++++++++++++++++----- 5 files changed, 189 insertions(+), 63 deletions(-) diff --git a/gbe_ecp2m/tb_gbe_buf.vhd b/gbe_ecp2m/tb_gbe_buf.vhd index a472efa..0516ce0 100755 --- a/gbe_ecp2m/tb_gbe_buf.vhd +++ b/gbe_ecp2m/tb_gbe_buf.vhd @@ -7,12 +7,16 @@ ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS - - COMPONENT trb_net16_gbe_buf - GENERIC( DO_SIMULATION : integer range 0 to 1 := 1 ); - PORT( - CLK : IN std_logic; - TEST_CLK : IN std_logic; + component buf_tester is --trb_net16_gbe_buf is + generic( + DO_SIMULATION : integer range 0 to 1 := 1; + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 + ); + port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode + CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode RESET : IN std_logic; GSR_N : IN std_logic; STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0); @@ -34,6 +38,17 @@ ARCHITECTURE behavior OF testbench IS SLV_ACK_OUT : out std_logic; SLV_DATA_IN : in std_logic_vector(31 downto 0); SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- gk 26.04.10 + -- registers setup interface + BUS_ADDR_IN : in std_logic_vector(7 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 + BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 + BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 + BUS_ACK_OUT : out std_logic; -- gk 26.04.10 + -- gk 23.04.10 + LED_PACKET_SENT_OUT : out std_logic; + LED_AN_DONE_N_OUT : out std_logic; ------------------------ CTS_NUMBER_IN : IN std_logic_vector(15 downto 0); CTS_CODE_IN : IN std_logic_vector(7 downto 0); @@ -276,10 +291,12 @@ ARCHITECTURE behavior OF testbench IS BEGIN -- Please check and add your generic clause manually - uut: trb_net16_gbe_buf - GENERIC MAP( DO_SIMULATION => 1 ) + uut: buf_tester --trb_net16_gbe_buf + GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 ) PORT MAP( CLK => CLK, + CLK_125_TX_IN => '0', + CLK_125_RX_IN => '0', TEST_CLK => TEST_CLK, RESET => RESET, GSR_N => GSR_N, @@ -302,6 +319,18 @@ BEGIN SLV_ACK_OUT => SLV_ACK_OUT, SLV_DATA_IN => SLV_DATA_IN, SLV_DATA_OUT => SLV_DATA_OUT, + -- gk 22.04.10 + -- registers setup interface + BUS_ADDR_IN => x"00", + BUS_DATA_IN => x"0000_0000", + BUS_DATA_OUT => open, + BUS_WRITE_EN_IN => '0', + BUS_READ_EN_IN => '0', + BUS_ACK_OUT => open, + -- gk 23.04.10 + LED_PACKET_SENT_OUT => open, + LED_AN_DONE_N_OUT => open, + -------------------------- CTS_NUMBER_IN => CTS_NUMBER_IN, CTS_CODE_IN => CTS_CODE_IN, CTS_INFORMATION_IN => CTS_INFORMATION_IN, @@ -448,6 +477,7 @@ variable cts_random_number : std_logic_vector(7 downto 0); variable stim : std_logic_vector(15 downto 0); + -- RND test --UNIFORM(seed1, seed2, rand); --int_rand := INTEGER(TRUNC(rand*65536.0)); @@ -509,6 +539,7 @@ begin wait for 500 ns; + ------------------------------------------------------------------------------- -- Loop the transmissions ------------------------------------------------------------------------------- @@ -541,8 +572,8 @@ begin UNIFORM(seed1, seed2, rand); test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1; - --test_data_len := 9685; - test_data_len := 200; + test_data_len := 9685; + --test_data_len := 400; -- calculate the needed variables test_loop_len := 2*(test_data_len - 1) + 1; @@ -638,6 +669,7 @@ begin else fee_dataready_in <= '1'; end if; + --fee_dataready_in <= '1'; end loop MY_DATA_LOOP; -- there must be padding words to get multiple of four LWs diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index 2f0a3e6..74ad3e3 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -248,7 +248,7 @@ port( DBG_SF_AEMPTY_OUT : out std_logic; DBG_SF_FULL_OUT : out std_logic; DBG_SF_AFULL_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end component; @@ -365,7 +365,8 @@ port ( PROTOCOL_IN : in std_logic_vector(7 downto 0); -- ports for packetTransmitter RD_CLK : in std_logic; - FT_DATA_OUT : out std_logic_vector(8 downto 0); + FT_DATA_OUT : out std_logic_vector(8 downto 0);-- gk 04.05.10 + --FT_EOD_OUT : out std_logic;-- gk 04.05.10 FT_TX_EMPTY_OUT : out std_logic; FT_TX_RD_EN_IN : in std_logic; FT_START_OF_PACKET_OUT : out std_logic; @@ -623,7 +624,7 @@ port( GBE_USE_MULTIEVENTS_OUT : out std_logic; GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10 GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 - GBE_DELAY_OUT : out std_logic_vector(31 downto 0) -- gk 28.04.10 + GBE_DELAY_OUT : out std_logic_vector(31 downto 0) ); end component; @@ -709,7 +710,7 @@ signal fc_protocol : std_logic_vector(7 downto 0); signal fc_bsm_constr : std_logic_vector(7 downto 0); signal fc_bsm_trans : std_logic_vector(3 downto 0); -signal ft_data : std_logic_vector(8 downto 0); +signal ft_data : std_logic_vector(8 downto 0);-- gk 04.05.10 signal ft_tx_empty : std_logic; signal ft_start_of_packet : std_logic; signal ft_bsm_init : std_logic_vector(3 downto 0); @@ -767,6 +768,8 @@ signal readout_ctr_valid : std_logic; signal gbe_trig_nr : std_logic_vector(31 downto 0); -- gk 28.04.10 signal pc_delay : std_logic_vector(31 downto 0); +-- gk 04.05.10 +signal ft_eod : std_logic; begin @@ -781,6 +784,7 @@ LED_AN_DONE_N_OUT <= not pcs_an_complete; --pc_decoding <= x"00020001"; -- !!!! swap it!!!! -- gk 22.04.10 --pc_event_id <= x"000000ca"; -- !!!! swap it!!!! -- gk 22.04.10 --pc_queue_dec <= x"00030062"; -- !!!! swap it!!!! -- gk 22.04.10 + -- FrameConstructor fixed magic values fc_type <= x"0008"; fc_ihl_version <= x"45"; @@ -816,7 +820,7 @@ port map( GBE_USE_MULTIEVENTS_OUT => use_multievents, GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10 GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10 - GBE_DELAY_OUT => pc_delay -- gk 28.04.10 + GBE_DELAY_OUT => pc_delay ); -- IP configurator: allows IP config to change for each event builder @@ -1016,6 +1020,7 @@ port map( -- ports for packetTransmitter RD_CLK => serdes_clk_125, FT_DATA_OUT => ft_data, + --FT_EOD_OUT => ft_eod, -- gk 04.05.10 FT_TX_EMPTY_OUT => ft_tx_empty, FT_TX_RD_EN_IN => mac_tx_read, FT_START_OF_PACKET_OUT => ft_start_of_packet, @@ -1033,7 +1038,7 @@ port map( TX_MAC_CLK => serdes_clk_125, TX_EMPTY_IN => ft_tx_empty, START_OF_PACKET_IN => ft_start_of_packet, - DATA_ENDFLAG_IN => ft_data(8), + DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10 -- MAC interface HADDR_OUT => mac_haddr, HDATA_OUT => mac_hdataout, @@ -1219,7 +1224,7 @@ imp_gen: if (DO_SIMULATION = 0) generate ); end generate serdes_extclk_gen; - stage_stat_regs(31 downto 28) <= x"d"; + stage_stat_regs(31 downto 28) <= x"e"; stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm stage_stat_regs(19 downto 18) <= (others => '0'); @@ -1389,7 +1394,7 @@ FC_BSM_CONSTR_TST <= fc_bsm_constr; FC_BSM_TRANS_TST <= fc_bsm_trans; -- FrameTransmitter signals FT_TX_EMPTY_TST <= ft_tx_empty; -FT_DATA_TST <= ft_data; +FT_DATA_TST <= ft_data; -- gk 04.05.10 FT_START_OF_PACKET_TST <= ft_start_of_packet; FT_BSM_INIT_TST <= ft_bsm_init; FT_BSM_MAC_TST <= ft_bsm_mac; diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd index 147b936..3fec624 100755 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -627,7 +627,9 @@ begin when CLEANUP => all_int_ctr <= 0; - when PREP_DATA => all_int_ctr <= 0; + when PREP_DATA => all_int_ctr <= 0; + + when DELAY => all_int_ctr <= 0; end case; end if; end process allIntCtrProc; diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd index 85d5e96..89917a2 100644 --- a/gbe_ecp2m/trb_net16_gbe_setup.vhd +++ b/gbe_ecp2m/trb_net16_gbe_setup.vhd @@ -38,7 +38,7 @@ port( GBE_USE_MULTIEVENTS_OUT : out std_logic; GBE_READOUT_CTR_OUT : out std_logic_vector(23 downto 0); -- gk 26.04.10 GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10 - GBE_DELAY_OUT : out std_logic_vector(31 downto 0) -- gk 28.04.10 + GBE_DELAY_OUT : out std_logic_vector(31 downto 0) ); end entity; @@ -104,7 +104,7 @@ begin subevent_id <= x"0000_00cf"; subevent_dec <= x"0002_0001"; queue_dec <= x"0003_0062"; - max_packet <= x"0000_fde8"; + max_packet <= x"0000_fd00"; --x"0000_fde8"; -- tester max_frame <= x"0578"; use_gbe <= '1'; use_trbnet <= '0'; @@ -113,6 +113,7 @@ begin readout_ctr <= x"00_0000"; -- gk 26.04.10 readout_ctr_valid <= '0'; -- gk 26.04.10 delay <= x"0000_0000"; -- gk 28.04.10 + elsif (BUS_WRITE_EN_IN = '1') then case BUS_ADDR_IN is diff --git a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd index e2eeff5..59eac52 100755 --- a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd +++ b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd @@ -8,12 +8,18 @@ use work.trb_net_std.all; use work.trb_net_components.all; entity trb_net16_med_ecp_sfp_gbe_8b is +-- gk 28.04.10 +generic ( + USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 +); port( RESET : in std_logic; GSR_N : in std_logic; CLK_125_OUT : out std_logic; CLK_RX_OUT : out std_logic; CLK_TX_OUT : out std_logic; + CLK_125_TX_IN : in std_logic; -- gk 28.04.10 used when intclk + CLK_125_RX_IN : in std_logic; -- gk 28.04.10 used when intclk --SGMII connection to frame transmitter (tsmac) FT_TX_CLK_EN_OUT : out std_logic; FT_RX_CLK_EN_OUT : out std_logic; @@ -98,6 +104,42 @@ port( refclkp : in std_logic; ); end component; +component serdes_gbe_0_intclock_8b is + GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b.txt"); + port ( + core_txrefclk : in std_logic; + core_rxrefclk : in std_logic; + hdinp0, hdinn0 : in std_logic; + hdoutp0, hdoutn0 : out std_logic; + ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic; + ff_txdata_ch0 : in std_logic_vector (7 downto 0); + ff_rxdata_ch0 : out std_logic_vector (7 downto 0); + ff_tx_k_cntrl_ch0 : in std_logic; + ff_rx_k_cntrl_ch0 : out std_logic; + ff_rxfullclk_ch0 : out std_logic; + ff_xmit_ch0 : in std_logic; + ff_correct_disp_ch0 : in std_logic; + ff_disp_err_ch0, ff_cv_ch0 : out std_logic; + ff_rx_even_ch0 : out std_logic; + ffc_rrst_ch0 : in std_logic; + ffc_lane_tx_rst_ch0 : in std_logic; + ffc_lane_rx_rst_ch0 : in std_logic; + ffc_txpwdnb_ch0 : in std_logic; + ffc_rxpwdnb_ch0 : in std_logic; + ffs_rlos_lo_ch0 : out std_logic; + ffs_ls_sync_status_ch0 : out std_logic; + ffs_rlol_ch0 : out std_logic; + oob_out_ch0 : out std_logic; + ffc_macro_rst : in std_logic; + ffc_quad_rst : in std_logic; + ffc_trst : in std_logic; + ff_txfullclk : out std_logic; + ff_txhalfclk : out std_logic; + refck2core : out std_logic; + ffs_plol : out std_logic); + +end component; + component sgmii_gbe_pcs32 port( rst_n : in std_logic; signal_detect : in std_logic; @@ -228,49 +270,93 @@ port map( SYSCLK => refclkcore, DEBUG_OUT => reset_debug ); +-- gk 28.04.10 -- SerDes for GbE -SERDES_GBE : serdes_gbe_0_extclock_8b -port map( -- SerDes connection to outside world - refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input - refclkn => SD_REFCLK_N_IN, - hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input - hdinn0 => SD_RXD_N_IN, - hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output - hdoutn0 => SD_TXD_N_OUT, - refck2core => refclkcore, -- reference clock from input - -- RX part - ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output - ff_rxiclk_ch0 => sd_rx_clk, - ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice - ff_rxdata_ch0 => sd_rx_data, -- RX data output - ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output - ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output) - ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error - ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error - -- TX part - ff_txfullclk => sd_tx_clk, -- TX full clock output - ff_txiclk_ch0 => sd_tx_clk, - ff_txhalfclk => open, - ff_txdata_ch0 => sd_tx_data, -- TX data input - ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input - ff_xmit_ch0 => '0', -- for autonegotiation (input) - ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input) - -- Resets and power down - ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high) - ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel - ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel - ffc_rrst_ch0 => '0', -- '0' for normal operation - ffc_macro_rst => '0', -- '0' for normal operation - ffc_trst => '0', -- '0' for normal operation - ffc_txpwdnb_ch0 => '1', -- must be '1' - ffc_rxpwdnb_ch0 => '1', -- must be '1' - -- Status outputs - ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas? - ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel - ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL - ffs_plol => sd_link_error(2), -- loss of lock in TX PLL - oob_out_ch0 => open -- not needed - ); +clk_int : if (USE_125MHZ_EXTCLK = 0) generate + SERDES_GBE : serdes_gbe_0_intclock_8b + port map( + core_txrefclk => CLK_125_TX_IN, + core_rxrefclk => CLK_125_RX_IN, + hdinp0 => SD_RXD_P_IN, + hdinn0 => SD_RXD_N_IN, + hdoutp0 => SD_TXD_P_OUT, + hdoutn0 => SD_TXD_N_OUT, + ff_rxiclk_ch0 => sd_rx_clk, + ff_txiclk_ch0 => sd_tx_clk, + ff_ebrd_clk_0 => sd_rx_clk, + ff_txdata_ch0 => sd_tx_data, + ff_rxdata_ch0 => sd_rx_data, + ff_tx_k_cntrl_ch0 => sd_tx_kcntl, + ff_rx_k_cntrl_ch0 => sd_rx_kcntl, + ff_rxfullclk_ch0 => sd_rx_clk, + ff_xmit_ch0 => '0', + ff_correct_disp_ch0 => sd_tx_correct_disp, + ff_disp_err_ch0 => sd_rx_disp_error, + ff_cv_ch0 => sd_rx_cv_error, + ff_rx_even_ch0 => sd_rx_even, + ffc_rrst_ch0 => '0', + ffc_lane_tx_rst_ch0 => lane_rst, + ffc_lane_rx_rst_ch0 => lane_rst, + ffc_txpwdnb_ch0 => '1', + ffc_rxpwdnb_ch0 => '1', + ffs_rlos_lo_ch0 => sd_link_error(0), + ffs_ls_sync_status_ch0 => sd_link_ok, + ffs_rlol_ch0 => sd_link_error(1), + oob_out_ch0 => open, + ffc_macro_rst => '0', + ffc_quad_rst => quad_rst, + ffc_trst => '0', + ff_txfullclk => sd_tx_clk, + ff_txhalfclk => open, + refck2core => refclkcore, + ffs_plol => sd_link_error(2) + ); +end generate clk_int; + +clk_ext : if (USE_125MHZ_EXTCLK = 1) generate + SERDES_GBE : serdes_gbe_0_extclock_8b + port map( -- SerDes connection to outside world + refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input + refclkn => SD_REFCLK_N_IN, + hdinp0 => SD_RXD_P_IN, -- SerDes RX diff. input + hdinn0 => SD_RXD_N_IN, + hdoutp0 => SD_TXD_P_OUT, -- SerDes TX diff. output + hdoutn0 => SD_TXD_N_OUT, + refck2core => refclkcore, -- reference clock from input + -- RX part + ff_rxfullclk_ch0 => sd_rx_clk, -- RX full clock output + ff_rxiclk_ch0 => sd_rx_clk, + ff_ebrd_clk_0 => sd_rx_clk, -- EB ist not used as recommended by Lattice + ff_rxdata_ch0 => sd_rx_data, -- RX data output + ff_rx_k_cntrl_ch0 => sd_rx_kcntl, -- RX komma output + ff_rx_even_ch0 => sd_rx_even, -- for autonegotiation (output) + ff_disp_err_ch0 => sd_rx_disp_error, -- RX disparity error + ff_cv_ch0 => sd_rx_cv_error, -- RX code violation error + -- TX part + ff_txfullclk => sd_tx_clk, -- TX full clock output + ff_txiclk_ch0 => sd_tx_clk, + ff_txhalfclk => open, + ff_txdata_ch0 => sd_tx_data, -- TX data input + ff_tx_k_cntrl_ch0 => sd_tx_kcntl, -- TX komma input + ff_xmit_ch0 => '0', -- for autonegotiation (input) + ff_correct_disp_ch0 => sd_tx_correct_disp, -- controls disparity at IPG start (input) + -- Resets and power down + ffc_quad_rst => quad_rst, -- async reset for whole QUAD (active high) + ffc_lane_tx_rst_ch0 => lane_rst, -- async reset for TX channel + ffc_lane_rx_rst_ch0 => lane_rst, -- async reset for RX channel + ffc_rrst_ch0 => '0', -- '0' for normal operation + ffc_macro_rst => '0', -- '0' for normal operation + ffc_trst => '0', -- '0' for normal operation + ffc_txpwdnb_ch0 => '1', -- must be '1' + ffc_rxpwdnb_ch0 => '1', -- must be '1' + -- Status outputs + ffs_ls_sync_status_ch0 => sd_link_ok, -- synced to kommas? + ffs_rlos_lo_ch0 => sd_link_error(0), -- loss of signal in RX channel + ffs_rlol_ch0 => sd_link_error(1), -- loss of lock in RX PLL + ffs_plol => sd_link_error(2), -- loss of lock in TX PLL + oob_out_ch0 => open -- not needed + ); +end generate clk_ext; SD_RX_DATA_PROC: process( sd_rx_clk ) begin -- 2.43.0