From 6891dc364a9986213e7d1a792cecb20bbf8a9fb9 Mon Sep 17 00:00:00 2001
From: Jan Michel <jan@mueschelsoft.de>
Date: Thu, 22 May 2014 13:59:04 +0200
Subject: [PATCH] update

---
 gbe2_ecp3/trb_net16_gbe_buf.vhd               | 755 ++++++++++--------
 gbe2_ecp3/trb_net16_gbe_event_constr.vhd      | 272 +++----
 gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd     | 341 +++++---
 gbe2_ecp3/trb_net16_gbe_main_control.vhd      |  54 +-
 gbe2_ecp3/trb_net16_gbe_packet_constr.vhd     |  39 +-
 gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd |  43 +-
 ...16_gbe_response_constructor_TrbNetData.vhd |  97 ++-
 gbe2_ecp3/trb_net16_gbe_setup.vhd             |  61 +-
 gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd |  10 +-
 gbe2_ecp3/trb_net_gbe_components.vhd          | 130 ++-
 gbe2_ecp3/trb_net_gbe_protocols.vhd           |  16 +-
 11 files changed, 1099 insertions(+), 719 deletions(-)

diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd
index ac48a20..b170c8f 100755
--- a/gbe2_ecp3/trb_net16_gbe_buf.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_buf.vhd
@@ -13,10 +13,18 @@ use work.trb_net_gbe_components.all;
 use work.trb_net_gbe_protocols.all;
 --use work.version.all;
 
+
 entity trb_net16_gbe_buf is
 generic( 
 	DO_SIMULATION		: integer range 0 to 1 := 1;
-	USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1
+	RX_PATH_ENABLE      : integer range 0 to 1 := 1;
+	USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
+	USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1;
+	
+		FIXED_SIZE_MODE : integer range 0 to 1 := 1;
+		FIXED_SIZE : integer range 0 to 65535 := 10;
+		FIXED_DELAY_MODE : integer range 0 to 1 := 1;
+		FIXED_DELAY : integer range 0 to 65535 := 4096
 );
 port(
 	CLK							: in	std_logic;
@@ -238,89 +246,15 @@ port (
 );
 end component;
 
-component fifo_4096x9 is
-port( 
-	Data    : in    std_logic_vector(8 downto 0);
-	WrClock : in    std_logic;
-	RdClock : in    std_logic;
-	WrEn    : in    std_logic;
-	RdEn    : in    std_logic;
-	Reset   : in    std_logic;
-	RPReset : in    std_logic;
-	Q       : out   std_logic_vector(8 downto 0);
-	Empty   : out   std_logic;
-	Full    : out   std_logic
-);
-end component;
-
-signal ig_bsm_save				: std_logic_vector(3 downto 0);
-signal ig_bsm_load				: std_logic_vector(3 downto 0);
-signal ig_cts_ctr				: std_logic_vector(2 downto 0);
-signal ig_rem_ctr				: std_logic_vector(3 downto 0);
-signal ig_debug					: std_logic_vector(31 downto 0);
-signal ig_data					: std_logic_vector(15 downto 0);
-signal ig_wcnt					: std_logic_vector(15 downto 0);
-signal ig_rcnt					: std_logic_vector(16 downto 0);
-signal ig_rd_en					: std_logic;
-signal ig_wr_en					: std_logic;
-signal ig_empty					: std_logic;
-signal ig_aempty				: std_logic;
-signal ig_full					: std_logic;
-signal ig_afull					: std_logic;
-
-signal pc_wr_en					: std_logic;
-signal pc_data					: std_logic_vector(7 downto 0);
-signal pc_eod					: std_logic;
-signal pc_sos					: std_logic;
-signal pc_ready					: std_logic;
-signal pc_padding				: std_logic;
 signal pc_decoding				: std_logic_vector(31 downto 0);
 signal pc_event_id				: std_logic_vector(31 downto 0);
 signal pc_queue_dec				: std_logic_vector(31 downto 0);
 signal pc_max_frame_size        : std_logic_vector(15 downto 0);
-signal pc_bsm_constr			: std_logic_vector(3 downto 0);
-signal pc_bsm_load				: std_logic_vector(3 downto 0);
-signal pc_bsm_save				: std_logic_vector(3 downto 0);
-signal pc_shf_empty				: std_logic;
-signal pc_shf_full				: std_logic;
-signal pc_shf_wr_en				: std_logic;
-signal pc_shf_rd_en				: std_logic;
-signal pc_shf_q					: std_logic_vector(7 downto 0);
-signal pc_df_empty				: std_logic;
-signal pc_df_full				: std_logic;
-signal pc_df_wr_en				: std_logic;
-signal pc_df_rd_en				: std_logic;
-signal pc_df_q					: std_logic_vector(7 downto 0);
-signal pc_all_ctr				: std_logic_vector(4 downto 0);
-signal pc_sub_ctr				: std_logic_vector(4 downto 0);
-signal pc_bytes_loaded			: std_logic_vector(15 downto 0);
-signal pc_size_left				: std_logic_vector(31 downto 0);
-signal pc_sub_size_to_save		: std_logic_vector(31 downto 0);
-signal pc_sub_size_loaded		: std_logic_vector(31 downto 0);
-signal pc_sub_bytes_loaded		: std_logic_vector(31 downto 0);
-signal pc_queue_size			: std_logic_vector(31 downto 0);
-signal pc_act_queue_size		: std_logic_vector(31 downto 0);
-
-signal fee_read					: std_logic;
 signal cts_readout_finished		: std_logic;
 signal cts_dataready			: std_logic;
 signal cts_length				: std_logic_vector(15 downto 0);
 signal cts_data					: std_logic_vector(31 downto 0); -- DHDR of rest packet
 signal cts_error_pattern		: std_logic_vector(31 downto 0);
-
-signal pc_sub_size				: std_logic_vector(31 downto 0);
-signal pc_trig_nr				: std_logic_vector(31 downto 0);
-
-signal tc_wr_en					: std_logic;
-signal tc_data					: std_logic_vector(7 downto 0);
-signal tc_ip_size				: std_logic_vector(15 downto 0);
-signal tc_udp_size				: std_logic_vector(15 downto 0);
-signal tc_ident					: std_logic_vector(15 downto 0);
-signal tc_flags_offset				: std_logic_vector(15 downto 0);
-signal tc_sod					: std_logic;
-signal tc_eod					: std_logic;
-signal tc_h_ready				: std_logic;
-signal tc_ready					: std_logic;
 signal fc_dest_mac				: std_logic_vector(47 downto 0);
 signal fc_dest_ip				: std_logic_vector(31 downto 0);
 signal fc_dest_udp				: std_logic_vector(15 downto 0);
@@ -332,8 +266,6 @@ signal fc_ihl_version			: std_logic_vector(7 downto 0);
 signal fc_tos					: std_logic_vector(7 downto 0);
 signal fc_ttl					: std_logic_vector(7 downto 0);
 signal fc_protocol				: std_logic_vector(7 downto 0);
-signal fc_bsm_constr			: std_logic_vector(7 downto 0);
-signal fc_bsm_trans				: std_logic_vector(3 downto 0);
 
 signal ft_data					: std_logic_vector(8 downto 0);-- gk 04.05.10
 signal ft_tx_empty				: std_logic;
@@ -371,55 +303,20 @@ signal pcs_stat_debug			: std_logic_vector(63 downto 0);
 
 signal stage_stat_regs			: std_logic_vector(31 downto 0);
 signal stage_ctrl_regs			: std_logic_vector(31 downto 0);
-
-signal analyzer_debug			: std_logic_vector(63 downto 0);
-
-signal ip_cfg_start			: std_logic;
-signal ip_cfg_bank			: std_logic_vector(3 downto 0);
-signal ip_cfg_done			: std_logic;
-
-signal ip_cfg_mem_addr			: std_logic_vector(7 downto 0);
-signal ip_cfg_mem_data			: std_logic_vector(31 downto 0);
-signal ip_cfg_mem_clk			: std_logic;
-
--- gk 22.04.10
-signal max_packet                    : std_logic_vector(31 downto 0);
-signal min_packet                    : std_logic_vector(31 downto 0);
 signal use_gbe                       : std_logic;
 signal use_trbnet                    : std_logic;
 signal use_multievents               : std_logic;
 -- gk 26.04.10
 signal readout_ctr                   : std_logic_vector(23 downto 0);
 signal readout_ctr_valid             : std_logic;
-signal gbe_trig_nr                   : std_logic_vector(31 downto 0);
--- gk 28.04.10
-signal pc_delay                      : std_logic_vector(31 downto 0);
--- gk 04.05.10
-signal ft_eod                        : std_logic;
--- gk 01.06.10
-signal dbg_ipu2gbe1                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe2                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe3                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe4                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe5                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe6                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe7                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe8                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe9                  : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe10                 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe11                 : std_logic_vector(31 downto 0);
-signal dbg_ipu2gbe12                 : std_logic_vector(31 downto 0);
 signal dbg_pc1                       : std_logic_vector(31 downto 0);
-signal dbg_pc2                       : std_logic_vector(31 downto 0);
 signal dbg_fc1                       : std_logic_vector(31 downto 0);
-signal dbg_fc2                       : std_logic_vector(31 downto 0);
 signal dbg_ft1                       : std_logic_vector(31 downto 0);
 -- gk 08.06.10
 signal mac_tx_staten                 : std_logic;
 signal mac_tx_statevec               : std_logic_vector(30 downto 0);
 signal mac_tx_discfrm                : std_logic;
 
-signal dbg_rd_en                     : std_logic;
 signal dbg_q                         : std_logic_vector(15 downto 0);
 
 -- gk 21.07.10
@@ -427,42 +324,13 @@ signal allow_large                   : std_logic;
 
 -- gk 28.07.10
 signal bytes_sent_ctr                : std_logic_vector(31 downto 0);
-signal monitor_sent                  : std_logic_vector(31 downto 0);
 signal monitor_dropped               : std_logic_vector(31 downto 0);
-signal monitor_sm                    : std_logic_vector(31 downto 0);
-signal monitor_lr                    : std_logic_vector(31 downto 0);
-signal monitor_hr                    : std_logic_vector(31 downto 0);
 signal monitor_fifos                 : std_logic_vector(31 downto 0);
 signal monitor_fifos_q               : std_logic_vector(31 downto 0);
-signal monitor_discfrm               : std_logic_vector(31 downto 0);
 
 -- gk 02.08.10
 signal discfrm_ctr                   : std_logic_vector(31 downto 0);
 
--- gk 28.09.10
-signal dbg_reset_fifo                : std_logic;
-
--- gk 30.09.10
-signal fc_rd_en                      : std_logic;
-signal link_ok                       : std_logic;
-signal link_ok_timeout_ctr           : std_logic_vector(15 downto 0);
-
-type linkStates     is  (ACTIVE, INACTIVE, TIMEOUT, FINALIZE);
-signal link_current_state, link_next_state : linkStates;
-
-signal link_down_ctr                 : std_logic_vector(15 downto 0);
-signal link_down_ctr_lock            : std_logic;
-
-signal link_state                    : std_logic_vector(3 downto 0);
-
-signal monitor_empty                 : std_logic_vector(31 downto 0);
-
--- gk 07.10.10
-signal pc_eos                        : std_logic;
-
--- gk 09.12.10
-signal frame_delay                   : std_logic_vector(31 downto 0);
-
 -- gk 13.02.11
 signal pcs_rxd                       : std_logic_vector(7 downto 0);
 signal pcs_rx_en                     : std_logic;
@@ -481,9 +349,6 @@ signal fr_frame_valid                : std_logic;
 signal rc_rd_en                      : std_logic;
 signal rc_q                          : std_logic_vector(8 downto 0);
 signal rc_frames_rec_ctr             : std_logic_vector(31 downto 0);
-signal tc_pc_ready                   : std_logic;
-signal tc_pc_h_ready                 : std_logic;
-signal mc_ctrl_frame_req             : std_logic;
 signal mc_data                       : std_logic_vector(8 downto 0);
 signal mc_wr_en                      : std_logic;
 signal fc_wr_en                      : std_logic;
@@ -501,32 +366,14 @@ signal allow_rx                      : std_logic;
 signal fr_frame_size                 : std_logic_vector(15 downto 0);
 signal rc_frame_size                 : std_logic_vector(15 downto 0);
 signal mc_frame_size                 : std_logic_vector(15 downto 0);
-signal ic_dest_mac			: std_logic_vector(47 downto 0);
-signal ic_dest_ip			: std_logic_vector(31 downto 0);
-signal ic_dest_udp			: std_logic_vector(15 downto 0);
-signal ic_src_mac			: std_logic_vector(47 downto 0);
-signal ic_src_ip			: std_logic_vector(31 downto 0);
-signal ic_src_udp			: std_logic_vector(15 downto 0);
-signal pc_transmit_on			: std_logic;
 signal rc_bytes_rec                  : std_logic_vector(31 downto 0);
 signal rc_debug                      : std_logic_vector(63 downto 0);
-signal mc_busy                       : std_logic;
 signal tsmac_gbit_en                 : std_logic;
 signal mc_transmit_ctrl              : std_logic;
-signal mc_transmit_data              : std_logic;
 signal rc_loading_done               : std_logic;
 signal fr_get_frame                  : std_logic;
 signal mc_transmit_done              : std_logic;
 
-signal dbg_fr                        : std_logic_vector(95 downto 0);
-signal dbg_rc                        : std_logic_vector(63 downto 0);
-signal dbg_mc                        : std_logic_vector(63 downto 0);
-signal dbg_tc                        : std_logic_vector(63 downto 0);
-
-signal fr_allowed_types              : std_logic_vector(31 downto 0);
-signal fr_allowed_ip                 : std_logic_vector(31 downto 0);
-signal fr_allowed_udp                : std_logic_vector(31 downto 0);
-
 signal fr_frame_proto                : std_logic_vector(15 downto 0);
 signal rc_frame_proto                : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
 
@@ -534,11 +381,12 @@ signal dbg_select_rec                : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1
 signal dbg_select_sent               : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 signal dbg_select_rec_bytes          : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 signal dbg_select_sent_bytes         : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+signal dbg_select_drop_in            : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+signal dbg_select_drop_out           : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 signal dbg_select_gen                : std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 signal serdes_rx_clk                 : std_logic;
 
-signal vlan_id                       : std_logic_vector(31 downto 0);
 signal mc_type                       : std_logic_vector(15 downto 0);
 signal fr_src_mac                : std_logic_vector(47 downto 0);
 signal fr_dest_mac               : std_logic_vector(47 downto 0);
@@ -571,39 +419,43 @@ attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_
 attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
 
 signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0);
-signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q : std_logic;
+signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q : std_logic;
 
 signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
-signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic;
-
-signal mc_ip_size, mc_udp_size, mc_flags : std_logic_vector(15 downto 0);
+signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq : std_logic;
 
 signal timeout_ctr : std_logic_vector(31 downto 0);
 signal timeout_noticed : std_Logic;
 attribute syn_keep of timeout_noticed : signal is true;
 attribute syn_preserve of timeout_noticed : signal is true;
 
-signal dummy_size : std_logic_vector(15 downto 0);
-signal dummy_pause : std_logic_vector(31 downto 0);
-
 signal make_reset    : std_logic;
 signal idle_too_long : std_logic;
-
-signal tc_data_not_valid : std_logic;
-
-signal mc_fc_h_ready, mc_fc_ready, mc_fc_wr_en : std_logic;
-signal mc_ident, mc_size_left : std_logic_vector(15 downto 0);
+signal mc_ident : std_logic_vector(15 downto 0);
 
 signal monitor_tx_packets : std_logic_vector(31 downto 0);
 signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0);
 signal insert_ttype, additional_hdr : std_logic;
-signal reset_dhcp : std_logic;
 signal dbg_hist, dbg_hist2 : hist_array;
-signal soft_gbe_reset, soft_rst, dhcp_done : std_logic;
-signal rst_ctr : std_logic_vector(24 downto 0);
 signal mac_reset : std_logic;
 signal global_reset, rst_n, ff : std_logic;
 
+  signal gbe_cts_number                   : std_logic_vector(15 downto 0);
+  signal gbe_cts_code                     : std_logic_vector(7 downto 0);
+  signal gbe_cts_information              : std_logic_vector(7 downto 0);
+  signal gbe_cts_start_readout            : std_logic;
+  signal gbe_cts_readout_type             : std_logic_vector(3 downto 0);
+  signal gbe_cts_readout_finished         : std_logic;
+  signal gbe_cts_status_bits              : std_logic_vector(31 downto 0);
+  signal gbe_fee_data                     : std_logic_vector(15 downto 0);
+  signal gbe_fee_dataready                : std_logic;
+  signal gbe_fee_read                     : std_logic;
+  signal gbe_fee_status_bits              : std_logic_vector(31 downto 0);
+  signal gbe_fee_busy                     : std_logic;
+  
+  signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0);
+  signal dhcp_done, link_ok, soft_rst : std_logic;
+
 begin
 
 stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
@@ -619,11 +471,11 @@ begin
 	end if;
 end process reset_sync;
 
-global_reset <= not rst_n;
+global_reset <= not rst_n or soft_rst;
 
 -- gk 23.04.10
 LED_PACKET_SENT_OUT <= '0'; --timeout_noticed; --pc_ready;
-LED_AN_DONE_N_OUT   <= '0'; --not link_ok; --not pcs_an_complete;
+LED_AN_DONE_N_OUT   <= dhcp_done; --not pcs_an_complete;
 
 fc_ihl_version      <= x"45";
 fc_tos              <= x"10";
@@ -633,7 +485,146 @@ fc_ttl              <= x"ff";
 
 --soft_gbe_reset <= '1' when soft_rst = '1' or (dhcp_done = '0' and rst_ctr(24) = '1') else '0';
 
-MAIN_CONTROL : trb_net16_gbe_main_control
+main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
+	MAIN_CONTROL : trb_net16_gbe_main_control
+		generic map(
+			RX_PATH_ENABLE => RX_PATH_ENABLE,
+			DO_SIMULATION  => DO_SIMULATION
+			)
+	  port map(
+		  CLK			=> CLK,
+		  CLK_125		=> serdes_clk_125,
+		  RESET			=> RESET,
+	
+		  MC_LINK_OK_OUT	=> link_ok,
+		  MC_RESET_LINK_IN	=> global_reset,
+		  MC_IDLE_TOO_LONG_OUT => idle_too_long,
+		  MC_DHCP_DONE_OUT => dhcp_done,
+	
+	  -- signals to/from receive controller
+		  RC_FRAME_WAITING_IN	=> rc_frame_ready,
+		  RC_LOADING_DONE_OUT	=> rc_loading_done,
+		  RC_DATA_IN		=> rc_q,
+		  RC_RD_EN_OUT		=> rc_rd_en,
+		  RC_FRAME_SIZE_IN	=> rc_frame_size,
+		  RC_FRAME_PROTO_IN	=> rc_frame_proto,
+	
+		  RC_SRC_MAC_ADDRESS_IN	=> rc_src_mac,
+		  RC_DEST_MAC_ADDRESS_IN  => rc_dest_mac,
+		  RC_SRC_IP_ADDRESS_IN	=> rc_src_ip,
+		  RC_DEST_IP_ADDRESS_IN	=> rc_dest_ip,
+		  RC_SRC_UDP_PORT_IN	=> rc_src_udp,
+		  RC_DEST_UDP_PORT_IN	=> rc_dest_udp,
+	
+	  -- signals to/from transmit controller
+		  TC_TRANSMIT_CTRL_OUT	=> mc_transmit_ctrl,
+		  TC_DATA_OUT		=> mc_data,
+		  TC_RD_EN_IN		=> mc_wr_en,
+		  --TC_DATA_NOT_VALID_OUT => tc_data_not_valid,
+		  TC_FRAME_SIZE_OUT	=> mc_frame_size,
+		  TC_FRAME_TYPE_OUT	=> mc_type,
+		  TC_IP_PROTOCOL_OUT	=> mc_ip_proto,
+		  TC_IDENT_OUT          => mc_ident,
+		  
+		  TC_DEST_MAC_OUT	=> mc_dest_mac,
+		  TC_DEST_IP_OUT	=> mc_dest_ip,
+		  TC_DEST_UDP_OUT	=> mc_dest_udp,
+		  TC_SRC_MAC_OUT	=> mc_src_mac,
+		  TC_SRC_IP_OUT		=> mc_src_ip,
+		  TC_SRC_UDP_OUT	=> mc_src_udp,
+		  TC_TRANSMIT_DONE_IN   => mc_transmit_done,
+	
+	  -- signals to/from sgmii/gbe pcs_an_complete
+		  PCS_AN_COMPLETE_IN	=> pcs_an_complete,
+	
+	  -- signals to/from hub
+		  MC_UNIQUE_ID_IN	=> MC_UNIQUE_ID_IN,
+		GSC_CLK_IN               => GSC_CLK_IN,
+		GSC_INIT_DATAREADY_OUT   => GSC_INIT_DATAREADY_OUT,
+		GSC_INIT_DATA_OUT        => GSC_INIT_DATA_OUT,
+		GSC_INIT_PACKET_NUM_OUT  => GSC_INIT_PACKET_NUM_OUT,
+		GSC_INIT_READ_IN         => GSC_INIT_READ_IN,
+		GSC_REPLY_DATAREADY_IN   => GSC_REPLY_DATAREADY_IN,
+		GSC_REPLY_DATA_IN        => GSC_REPLY_DATA_IN,
+		GSC_REPLY_PACKET_NUM_IN  => GSC_REPLY_PACKET_NUM_IN,
+		GSC_REPLY_READ_OUT       => GSC_REPLY_READ_OUT,
+		GSC_BUSY_IN              => GSC_BUSY_IN,
+	
+		MAKE_RESET_OUT           => make_reset, --MAKE_RESET_OUT,
+		
+			-- CTS interface
+		CTS_NUMBER_IN				=> CTS_NUMBER_IN,
+		CTS_CODE_IN					=> CTS_CODE_IN,
+		CTS_INFORMATION_IN			=> CTS_INFORMATION_IN,
+		CTS_READOUT_TYPE_IN			=> CTS_READOUT_TYPE_IN,
+		CTS_START_READOUT_IN		=> CTS_START_READOUT_IN,
+		CTS_DATA_OUT				=> CTS_DATA_OUT,
+		CTS_DATAREADY_OUT			=> CTS_DATAREADY_OUT,
+		CTS_READOUT_FINISHED_OUT	=> CTS_READOUT_FINISHED_OUT,
+		CTS_READ_IN					=> CTS_READ_IN,
+		CTS_LENGTH_OUT				=> CTS_LENGTH_OUT,
+		CTS_ERROR_PATTERN_OUT		=> CTS_ERROR_PATTERN_OUT,
+		-- Data payload interface
+		FEE_DATA_IN					=> FEE_DATA_IN,
+		FEE_DATAREADY_IN			=> FEE_DATAREADY_IN,
+		FEE_READ_OUT				=> FEE_READ_OUT,
+		FEE_STATUS_BITS_IN			=> FEE_STATUS_BITS_IN,
+		FEE_BUSY_IN					=> FEE_BUSY_IN, 
+		-- ip configurator
+		SLV_ADDR_IN                 => SLV_ADDR_IN,
+		SLV_READ_IN                 => SLV_READ_IN,
+		SLV_WRITE_IN                => SLV_WRITE_IN,
+		SLV_BUSY_OUT                => SLV_BUSY_OUT,
+		SLV_ACK_OUT                 => SLV_ACK_OUT,
+		SLV_DATA_IN                 => SLV_DATA_IN,
+		SLV_DATA_OUT                => SLV_DATA_OUT,
+		
+		CFG_GBE_ENABLE_IN           => use_gbe,
+		CFG_IPU_ENABLE_IN           => use_trbnet,
+		CFG_MULT_ENABLE_IN          => use_multievents,
+		CFG_SUBEVENT_ID_IN			=> pc_event_id,
+		CFG_SUBEVENT_DEC_IN         => pc_decoding,
+		CFG_QUEUE_DEC_IN            => pc_queue_dec,
+		CFG_READOUT_CTR_IN          => readout_ctr,
+		CFG_READOUT_CTR_VALID_IN    => readout_ctr_valid,
+		CFG_INSERT_TTYPE_IN         => insert_ttype,
+		CFG_MAX_SUB_IN              => max_sub,
+		CFG_MAX_QUEUE_IN            => max_queue,
+		CFG_MAX_SUBS_IN_QUEUE_IN    => max_subs_in_queue,
+		CFG_MAX_SINGLE_SUB_IN       => max_single_sub,
+		
+		CFG_ADDITIONAL_HDR_IN       => additional_hdr,
+	
+	  -- signal to/from Host interface of TriSpeed MAC
+		  TSM_HADDR_OUT		=> mac_haddr,
+		  TSM_HDATA_OUT		=> mac_hdataout,
+		  TSM_HCS_N_OUT		=> mac_hcs,
+		  TSM_HWRITE_N_OUT	=> mac_hwrite,
+		  TSM_HREAD_N_OUT	=> mac_hread,
+		  TSM_HREADY_N_IN	=> mac_hready,
+		  TSM_HDATA_EN_N_IN	=> mac_hdata_en,
+		  TSM_RX_STAT_VEC_IN  => mac_rx_stat_vec,
+		  TSM_RX_STAT_EN_IN   => mac_rx_stat_en,
+		  
+		  MONITOR_SELECT_REC_OUT		 => dbg_select_rec,
+		  MONITOR_SELECT_REC_BYTES_OUT   => dbg_select_rec_bytes,
+		  MONITOR_SELECT_SENT_BYTES_OUT  => dbg_select_sent_bytes,
+		  MONITOR_SELECT_SENT_OUT	     => dbg_select_sent,
+		  MONITOR_SELECT_DROP_IN_OUT     => dbg_select_drop_in,
+		  MONITOR_SELECT_DROP_OUT_OUT    => dbg_select_drop_out,
+		  MONITOR_SELECT_GEN_DBG_OUT     => dbg_select_gen,
+		
+			DATA_HIST_OUT => dbg_hist,
+			SCTRL_HIST_OUT => dbg_hist2
+	  );
+end generate main_gen;
+
+main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
+	MAIN_CONTROL : trb_net16_gbe_main_control
+	generic map(
+		RX_PATH_ENABLE => RX_PATH_ENABLE,
+		DO_SIMULATION  => DO_SIMULATION
+		)
   port map(
 	  CLK			=> CLK,
 	  CLK_125		=> serdes_clk_125,
@@ -681,7 +672,7 @@ MAIN_CONTROL : trb_net16_gbe_main_control
 	  PCS_AN_COMPLETE_IN	=> pcs_an_complete,
 
   -- signals to/from hub
-	  MC_UNIQUE_ID_IN	=> MC_UNIQUE_ID_IN,
+	  MC_UNIQUE_ID_IN	     => MC_UNIQUE_ID_IN,
 	GSC_CLK_IN               => GSC_CLK_IN,
 	GSC_INIT_DATAREADY_OUT   => GSC_INIT_DATAREADY_OUT,
 	GSC_INIT_DATA_OUT        => GSC_INIT_DATA_OUT,
@@ -696,23 +687,23 @@ MAIN_CONTROL : trb_net16_gbe_main_control
 	MAKE_RESET_OUT           => make_reset, --MAKE_RESET_OUT,
 	
 		-- CTS interface
-	CTS_NUMBER_IN				=> CTS_NUMBER_IN,
-	CTS_CODE_IN					=> CTS_CODE_IN,
-	CTS_INFORMATION_IN			=> CTS_INFORMATION_IN,
-	CTS_READOUT_TYPE_IN			=> CTS_READOUT_TYPE_IN,
-	CTS_START_READOUT_IN		=> CTS_START_READOUT_IN,
-	CTS_DATA_OUT				=> CTS_DATA_OUT,
-	CTS_DATAREADY_OUT			=> CTS_DATAREADY_OUT,
-	CTS_READOUT_FINISHED_OUT	=> CTS_READOUT_FINISHED_OUT,
-	CTS_READ_IN					=> CTS_READ_IN,
-	CTS_LENGTH_OUT				=> CTS_LENGTH_OUT,
-	CTS_ERROR_PATTERN_OUT		=> CTS_ERROR_PATTERN_OUT,
-	-- Data payload interface
-	FEE_DATA_IN					=> FEE_DATA_IN,
-	FEE_DATAREADY_IN			=> FEE_DATAREADY_IN,
-	FEE_READ_OUT				=> FEE_READ_OUT,
-	FEE_STATUS_BITS_IN			=> FEE_STATUS_BITS_IN,
-	FEE_BUSY_IN					=> FEE_BUSY_IN, 
+	CTS_NUMBER_IN               => gbe_cts_number,           
+	CTS_CODE_IN                 => gbe_cts_code,             
+	CTS_INFORMATION_IN          => gbe_cts_information,      
+	CTS_READOUT_TYPE_IN         => gbe_cts_readout_type,     
+	CTS_START_READOUT_IN        => gbe_cts_start_readout,    
+	CTS_DATA_OUT                => open,                     
+	CTS_DATAREADY_OUT           => open,                     
+	CTS_READOUT_FINISHED_OUT    => gbe_cts_readout_finished, 
+	CTS_READ_IN                 => '1',                      
+	CTS_LENGTH_OUT              => open,                     
+	CTS_ERROR_PATTERN_OUT       => gbe_cts_status_bits,      
+	--Data payload interface                                 
+	FEE_DATA_IN                 => gbe_fee_data,             
+	FEE_DATAREADY_IN            => gbe_fee_dataready,        
+	FEE_READ_OUT                => gbe_fee_read,             
+	FEE_STATUS_BITS_IN          => gbe_fee_status_bits,      
+	FEE_BUSY_IN                 => gbe_fee_busy,             
 	-- ip configurator
 	SLV_ADDR_IN                 => SLV_ADDR_IN,
 	SLV_READ_IN                 => SLV_READ_IN,
@@ -722,16 +713,21 @@ MAIN_CONTROL : trb_net16_gbe_main_control
 	SLV_DATA_IN                 => SLV_DATA_IN,
 	SLV_DATA_OUT                => SLV_DATA_OUT,
 	
-	CFG_GBE_ENABLE_IN           => use_gbe,
-	CFG_IPU_ENABLE_IN           => use_trbnet,
-	CFG_MULT_ENABLE_IN          => use_multievents,
-	CFG_SUBEVENT_ID_IN			=> pc_event_id,
-	CFG_SUBEVENT_DEC_IN         => pc_decoding,
-	CFG_QUEUE_DEC_IN            => pc_queue_dec,
-	CFG_READOUT_CTR_IN          => readout_ctr,
-	CFG_READOUT_CTR_VALID_IN    => readout_ctr_valid,
-	CFG_ADDITIONAL_HDR_IN       => additional_hdr,
-	CFG_INSERT_TTYPE_IN         => insert_ttype,
+	CFG_GBE_ENABLE_IN           => '1',
+	CFG_IPU_ENABLE_IN           => '0',
+	CFG_MULT_ENABLE_IN          => '0',
+	CFG_SUBEVENT_ID_IN			=> x"0000_00cf",
+	CFG_SUBEVENT_DEC_IN         => x"0002_0001",
+	CFG_QUEUE_DEC_IN            => x"0003_0062",
+	CFG_READOUT_CTR_IN          => x"00_0000",
+	CFG_READOUT_CTR_VALID_IN    => '0',
+	CFG_INSERT_TTYPE_IN         => '0',
+	CFG_MAX_SUB_IN              => x"e998",  -- 59800 
+	CFG_MAX_QUEUE_IN            => x"ea60",  -- 60000 
+	CFG_MAX_SUBS_IN_QUEUE_IN    => x"00c8",  -- 200
+	CFG_MAX_SINGLE_SUB_IN       => x"7d00",  -- 32000
+	
+	CFG_ADDITIONAL_HDR_IN       => '0',
 
   -- signal to/from Host interface of TriSpeed MAC
 	  TSM_HADDR_OUT		=> mac_haddr,
@@ -748,16 +744,100 @@ MAIN_CONTROL : trb_net16_gbe_main_control
 	  MONITOR_SELECT_REC_BYTES_OUT   => dbg_select_rec_bytes,
 	  MONITOR_SELECT_SENT_BYTES_OUT  => dbg_select_sent_bytes,
 	  MONITOR_SELECT_SENT_OUT	     => dbg_select_sent,
+	  MONITOR_SELECT_DROP_IN_OUT     => dbg_select_drop_in,
+	  MONITOR_SELECT_DROP_OUT_OUT    => dbg_select_drop_out,
 	  MONITOR_SELECT_GEN_DBG_OUT     => dbg_select_gen,
 	
 		DATA_HIST_OUT => dbg_hist,
 		SCTRL_HIST_OUT => dbg_hist2
   );
   
+  dummy : gbe_ipu_dummy
+	generic map(
+		DO_SIMULATION => DO_SIMULATION,
+		FIXED_SIZE_MODE => FIXED_SIZE_MODE,
+		FIXED_SIZE => FIXED_SIZE,
+		FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+		FIXED_DELAY => FIXED_DELAY
+	)
+	port map(
+		clk => CLK,
+		rst => global_reset,
+		GBE_READY_IN => dhcp_done,
+		                    
+		CTS_NUMBER_OUT		     =>gbe_cts_number,
+		CTS_CODE_OUT		     =>gbe_cts_code,
+		CTS_INFORMATION_OUT	     =>gbe_cts_information,
+		CTS_READOUT_TYPE_OUT     =>gbe_cts_readout_type,
+		CTS_START_READOUT_OUT    =>gbe_cts_start_readout,
+		CTS_DATA_IN				 =>(others => '0'),
+		CTS_DATAREADY_IN	     =>'0',
+		CTS_READOUT_FINISHED_IN	 =>gbe_cts_readout_finished,
+		CTS_READ_OUT		     =>open,
+		CTS_LENGTH_IN		     =>(others => '0'),
+		CTS_ERROR_PATTERN_IN     =>gbe_cts_status_bits,
+		-- Data payload interfac =>
+		FEE_DATA_OUT		     =>gbe_fee_data,
+		FEE_DATAREADY_OUT	     =>gbe_fee_dataready,
+		FEE_READ_IN				 =>gbe_fee_read,
+		FEE_STATUS_BITS_OUT	     =>gbe_fee_status_bits,
+		FEE_BUSY_OUT		     =>gbe_fee_busy
+	);                      
+ end generate main_with_dummy_gen;
+
   MAKE_RESET_OUT <= make_reset; -- or idle_too_long;
 
+transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate
+
+	TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
+	port map(
+		CLK			=> CLK,
+		RESET			=> global_reset, --RESET,
+	
+	-- signal to/from main controller
+		TC_DATAREADY_IN        => mc_transmit_ctrl,
+		TC_RD_EN_OUT		   => mc_wr_en,
+		TC_DATA_IN		       => mc_data(7 downto 0),
+		TC_FRAME_SIZE_IN	   => mc_frame_size,
+		TC_FRAME_TYPE_IN	   => mc_type,
+		TC_IP_PROTOCOL_IN	   => mc_ip_proto,	
+		TC_DEST_MAC_IN		   => mc_dest_mac,
+		TC_DEST_IP_IN		   => mc_dest_ip,
+		TC_DEST_UDP_IN		   => mc_dest_udp,
+		TC_SRC_MAC_IN		   => mc_src_mac,
+		TC_SRC_IP_IN		   => mc_src_ip,
+		TC_SRC_UDP_IN		   => mc_src_udp,
+		TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
+		TC_IDENT_IN            => mc_ident,
+		TC_MAX_FRAME_IN        => pc_max_frame_size,
+	
+	-- signal to/from frame constructor
+		FC_DATA_OUT		=> fc_data,
+		FC_WR_EN_OUT		=> fc_wr_en,
+		FC_READY_IN		=> fc_ready,
+		FC_H_READY_IN		=> fc_h_ready,
+		FC_FRAME_TYPE_OUT	=> fc_type,
+		FC_IP_SIZE_OUT		=> fc_ip_size,
+		FC_UDP_SIZE_OUT		=> fc_udp_size,
+		FC_IDENT_OUT		=> fc_ident,
+		FC_FLAGS_OFFSET_OUT	=> fc_flags_offset,
+		FC_SOD_OUT		=> fc_sod,
+		FC_EOD_OUT		=> fc_eod,
+		FC_IP_PROTOCOL_OUT	=> fc_protocol,
+	
+		DEST_MAC_ADDRESS_OUT    => fc_dest_mac,
+		DEST_IP_ADDRESS_OUT     => fc_dest_ip,
+		DEST_UDP_PORT_OUT       => fc_dest_udp,
+		SRC_MAC_ADDRESS_OUT     => fc_src_mac,
+		SRC_IP_ADDRESS_OUT      => fc_src_ip,
+		SRC_UDP_PORT_OUT        => fc_src_udp,
+	
+		MONITOR_TX_PACKETS_OUT  => monitor_tx_packets
+	);
+end generate transmit_gen;
 
-TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
+transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate
+	TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2
 port map(
 	CLK			=> CLK,
 	RESET			=> global_reset, --RESET,
@@ -777,7 +857,7 @@ port map(
 	TC_SRC_UDP_IN		   => mc_src_udp,
 	TC_TRANSMISSION_DONE_OUT => mc_transmit_done,
 	TC_IDENT_IN            => mc_ident,
-	TC_MAX_FRAME_IN        => pc_max_frame_size,
+	TC_MAX_FRAME_IN        => x"0578",
 
 -- signal to/from frame constructor
 	FC_DATA_OUT		=> fc_data,
@@ -802,6 +882,7 @@ port map(
 
 	MONITOR_TX_PACKETS_OUT  => monitor_tx_packets
 );
+end generate transmit_with_dummy_gen;
 
 
 setup_imp_gen : if (DO_SIMULATION = 0) generate
@@ -833,6 +914,11 @@ port map(
 	GBE_INSERT_TTYPE_OUT        => insert_ttype,
 	GBE_SOFT_RESET_OUT          => soft_rst,
 	
+	GBE_MAX_SUB_OUT             => max_sub,
+	GBE_MAX_QUEUE_OUT           => max_queue,
+	GBE_MAX_SUBS_IN_QUEUE_OUT   => max_subs_in_queue,
+	GBE_MAX_SINGLE_SUB_OUT      => max_single_sub,
+	
 	MONITOR_RX_BYTES_IN         => monitor_rx_bytes,
 	MONITOR_RX_FRAMES_IN        => monitor_rx_frames,
 	MONITOR_TX_BYTES_IN         => monitor_tx_bytes,
@@ -844,6 +930,8 @@ port map(
 	MONITOR_SELECT_REC_BYTES_IN   => dbg_select_rec_bytes,
 	MONITOR_SELECT_SENT_BYTES_IN  => dbg_select_sent_bytes,
 	MONITOR_SELECT_SENT_IN	      => dbg_select_sent,
+	MONITOR_SELECT_DROP_IN_IN     => dbg_select_drop_in,
+	MONITOR_SELECT_DROP_OUT_IN    => dbg_select_drop_out,
 	MONITOR_SELECT_GEN_DBG_IN     => dbg_select_gen,
 	
 	DATA_HIST_IN => dbg_hist,
@@ -900,50 +988,6 @@ port map(
 	MONITOR_TX_FRAMES_OUT   => monitor_tx_frames
 );
 
-
-RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
-port map(
-	CLK			=> CLK,
-	RESET			=> global_reset, --RESET,
-
--- signals to/from frame_receiver
-	RC_DATA_IN		=> fr_q,
-	FR_RD_EN_OUT		=> fr_rd_en,
-	FR_FRAME_VALID_IN	=> fr_frame_valid,
-	FR_GET_FRAME_OUT	=> fr_get_frame,
-	FR_FRAME_SIZE_IN	=> fr_frame_size,
-	FR_FRAME_PROTO_IN	=> fr_frame_proto,
-	FR_IP_PROTOCOL_IN	=> fr_ip_proto,
-	
-	FR_SRC_MAC_ADDRESS_IN	=> fr_src_mac,
-	FR_DEST_MAC_ADDRESS_IN  => fr_dest_mac,
-	FR_SRC_IP_ADDRESS_IN	=> fr_src_ip,
-	FR_DEST_IP_ADDRESS_IN	=> fr_dest_ip,
-	FR_SRC_UDP_PORT_IN	=> fr_src_udp,
-	FR_DEST_UDP_PORT_IN	=> fr_dest_udp,
-
--- signals to/from main controller
-	RC_RD_EN_IN		=> rc_rd_en,
-	RC_Q_OUT		=> rc_q,
-	RC_FRAME_WAITING_OUT	=> rc_frame_ready,
-	RC_LOADING_DONE_IN	=> rc_loading_done,
-	RC_FRAME_SIZE_OUT	=> rc_frame_size,
-	RC_FRAME_PROTO_OUT	=> rc_frame_proto,
-	
-	RC_SRC_MAC_ADDRESS_OUT	=> rc_src_mac,
-	RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
-	RC_SRC_IP_ADDRESS_OUT	=> rc_src_ip,
-	RC_DEST_IP_ADDRESS_OUT	=> rc_dest_ip,
-	RC_SRC_UDP_PORT_OUT	=> rc_src_udp,
-	RC_DEST_UDP_PORT_OUT	=> rc_dest_udp,
-
--- statistics
-	FRAMES_RECEIVED_OUT	=> rc_frames_rec_ctr,
-	BYTES_RECEIVED_OUT      => rc_bytes_rec,
-
-
-	DEBUG_OUT		=> rc_debug
-);
 dbg_q(15 downto 9) <= (others  => '0');
 
 FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
@@ -975,6 +1019,52 @@ port map(
 	--DEBUG_OUT(63 downto 32)		=> open
 );  
 
+rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
+
+	RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
+	port map(
+		CLK			=> CLK,
+		RESET			=> global_reset, --RESET,
+	
+	-- signals to/from frame_receiver
+		RC_DATA_IN		=> fr_q,
+		FR_RD_EN_OUT		=> fr_rd_en,
+		FR_FRAME_VALID_IN	=> fr_frame_valid,
+		FR_GET_FRAME_OUT	=> fr_get_frame,
+		FR_FRAME_SIZE_IN	=> fr_frame_size,
+		FR_FRAME_PROTO_IN	=> fr_frame_proto,
+		FR_IP_PROTOCOL_IN	=> fr_ip_proto,
+		
+		FR_SRC_MAC_ADDRESS_IN	=> fr_src_mac,
+		FR_DEST_MAC_ADDRESS_IN  => fr_dest_mac,
+		FR_SRC_IP_ADDRESS_IN	=> fr_src_ip,
+		FR_DEST_IP_ADDRESS_IN	=> fr_dest_ip,
+		FR_SRC_UDP_PORT_IN	=> fr_src_udp,
+		FR_DEST_UDP_PORT_IN	=> fr_dest_udp,
+	
+	-- signals to/from main controller
+		RC_RD_EN_IN		=> rc_rd_en,
+		RC_Q_OUT		=> rc_q,
+		RC_FRAME_WAITING_OUT	=> rc_frame_ready,
+		RC_LOADING_DONE_IN	=> rc_loading_done,
+		RC_FRAME_SIZE_OUT	=> rc_frame_size,
+		RC_FRAME_PROTO_OUT	=> rc_frame_proto,
+		
+		RC_SRC_MAC_ADDRESS_OUT	=> rc_src_mac,
+		RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
+		RC_SRC_IP_ADDRESS_OUT	=> rc_src_ip,
+		RC_DEST_IP_ADDRESS_OUT	=> rc_dest_ip,
+		RC_SRC_UDP_PORT_OUT	=> rc_src_udp,
+		RC_DEST_UDP_PORT_OUT	=> rc_dest_udp,
+	
+	-- statistics
+		FRAMES_RECEIVED_OUT	=> rc_frames_rec_ctr,
+		BYTES_RECEIVED_OUT      => rc_bytes_rec,
+	
+	
+		DEBUG_OUT		=> rc_debug
+	);
+
   FRAME_RECEIVER : trb_net16_gbe_frame_receiver
   port map(
 	  CLK			=> CLK,
@@ -1016,6 +1106,35 @@ port map(
 	  MONITOR_RX_FRAMES_OUT => monitor_rx_frames,
 	  MONITOR_DROPPED_OUT   => monitor_dropped
   );
+  
+end generate rx_enable_gen;
+
+rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
+	
+	
+		rc_q <= (others => '0');
+		rc_frame_ready <= '0';
+		rc_frame_size <= (others => '0');
+		rc_frame_proto <= (others => '0');
+		
+		rc_src_mac <= (others => '0');
+		rc_dest_mac <= (others => '0');
+		rc_src_ip <= (others => '0');
+		rc_dest_ip <= (others => '0');
+		rc_src_udp <= (others => '0');
+		rc_dest_udp <= (others => '0');
+	
+		rc_frames_rec_ctr <= (others => '0');
+		rc_bytes_rec <= (others => '0');
+		rc_debug <= (others => '0');
+		
+		monitor_rx_bytes <= (others => '0');
+	    monitor_rx_frames <= (others => '0');
+	    monitor_dropped <= (others => '0');
+	    
+	    mac_rx_fifo_full <= '0';
+	
+end generate rx_disable_gen;
 
 
 -- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in
@@ -1362,69 +1481,69 @@ end generate sim_gen;
 
 
 -- gk 04.08.10
-MON_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		monitor_fifos_q(3 downto 0)           <= monitor_fifos(3 downto 0);
-		if (dbg_pc1(28) = '1') then
-			monitor_fifos_q(5 downto 4)   <= b"11";
-		else 
-			monitor_fifos_q(5 downto 4)   <= b"00";
-		end if;
-		if (dbg_pc1(30) = '1') then
-			monitor_fifos_q(7 downto 6)   <= b"11";
-		else 
-			monitor_fifos_q(7 downto 6)   <= b"00";
-		end if;
-		if (dbg_fc1(28) = '1') then
-			monitor_fifos_q(11 downto 8)  <= b"1111";
-		else
-			monitor_fifos_q(11 downto 8)  <= b"0000";
-		end if;
-		if (pcs_an_complete = '0') then
-			monitor_fifos_q(15 downto 12) <= b"1111";
-		else
-			monitor_fifos_q(15 downto 12) <= b"0000";
-		end if;
-	end if;
-end process MON_PROC;
-
--- gk 28.07.10
-BYTES_SENT_CTR_PROC : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if (RESET = '1') then
-			bytes_sent_ctr <= (others => '0');
-		elsif (fc_wr_en = '1') then
-			bytes_sent_ctr <= bytes_sent_ctr + x"1";
-		end if;
-	end if;
-end process BYTES_SENT_CTR_PROC;
-
--- gk 02.08.10
-DISCFRM_PROC : process(serdes_clk_125)
-begin
-	if rising_edge(serdes_clk_125) then
-		if (RESET = '1') then
-			discfrm_ctr <= (others => '0');
-		elsif (mac_tx_discfrm = '1') then
-			discfrm_ctr <= discfrm_ctr + x"1";
-		end if;
-	end if;
-end process DISCFRM_PROC;
-
-discfrm_sync : signal_sync
-	generic map(
-	  DEPTH => 2,
-	  WIDTH => 32
-	  )
-	port map(
-	  RESET    => RESET,
-	  D_IN     => discfrm_ctr,
-	  CLK0     => serdes_clk_125,
-	  CLK1     => CLK,
-	  D_OUT    => monitor_discfrm
-	  );
+--MON_PROC : process(CLK)
+--begin
+--	if rising_edge(CLK) then
+--		monitor_fifos_q(3 downto 0)           <= monitor_fifos(3 downto 0);
+--		if (dbg_pc1(28) = '1') then
+--			monitor_fifos_q(5 downto 4)   <= b"11";
+--		else 
+--			monitor_fifos_q(5 downto 4)   <= b"00";
+--		end if;
+--		if (dbg_pc1(30) = '1') then
+--			monitor_fifos_q(7 downto 6)   <= b"11";
+--		else 
+--			monitor_fifos_q(7 downto 6)   <= b"00";
+--		end if;
+--		if (dbg_fc1(28) = '1') then
+--			monitor_fifos_q(11 downto 8)  <= b"1111";
+--		else
+--			monitor_fifos_q(11 downto 8)  <= b"0000";
+--		end if;
+--		if (pcs_an_complete = '0') then
+--			monitor_fifos_q(15 downto 12) <= b"1111";
+--		else
+--			monitor_fifos_q(15 downto 12) <= b"0000";
+--		end if;
+--	end if;
+--end process MON_PROC;
+
+---- gk 28.07.10
+--BYTES_SENT_CTR_PROC : process(CLK)
+--begin
+--	if rising_edge(CLK) then
+--		if (RESET = '1') then
+--			bytes_sent_ctr <= (others => '0');
+--		elsif (fc_wr_en = '1') then
+--			bytes_sent_ctr <= bytes_sent_ctr + x"1";
+--		end if;
+--	end if;
+--end process BYTES_SENT_CTR_PROC;
+--
+---- gk 02.08.10
+--DISCFRM_PROC : process(serdes_clk_125)
+--begin
+--	if rising_edge(serdes_clk_125) then
+--		if (RESET = '1') then
+--			discfrm_ctr <= (others => '0');
+--		elsif (mac_tx_discfrm = '1') then
+--			discfrm_ctr <= discfrm_ctr + x"1";
+--		end if;
+--	end if;
+--end process DISCFRM_PROC;
+--
+--discfrm_sync : signal_sync
+--	generic map(
+--	  DEPTH => 2,
+--	  WIDTH => 32
+--	  )
+--	port map(
+--	  RESET    => RESET,
+--	  D_IN     => discfrm_ctr,
+--	  CLK0     => serdes_clk_125,
+--	  CLK1     => CLK,
+--	  D_OUT    => monitor_discfrm
+--	  );
 
 
 ------------------------------------------------------------------------------------------------
diff --git a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd
index 214eab8..a93e6d9 100644
--- a/gbe2_ecp3/trb_net16_gbe_event_constr.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_event_constr.vhd
@@ -16,26 +16,20 @@ entity trb_net16_gbe_event_constr is
 port(
 	RESET                   : in    std_logic;
 	CLK                     : in    std_logic;
-	MULT_EVT_ENABLE_IN      : in    std_logic;  -- gk 06.10.10
 	-- ports for user logic
 	PC_WR_EN_IN             : in    std_logic; -- write into queueConstr from userLogic
 	PC_DATA_IN              : in    std_logic_vector(7 downto 0);
 	PC_READY_OUT            : out   std_logic;
 	PC_START_OF_SUB_IN      : in    std_logic;
 	PC_END_OF_SUB_IN        : in    std_logic;  -- gk 07.10.10
-	PC_END_OF_DATA_IN       : in    std_logic;
-	PC_TRANSMIT_ON_OUT	: out	std_logic;
+	PC_END_OF_QUEUE_IN      : in    std_logic;
 	-- queue and subevent layer headers
 	PC_SUB_SIZE_IN          : in    std_logic_vector(31 downto 0); -- store and swap
-	PC_PADDING_IN           : in    std_logic;  -- gk 29.03.10
 	PC_DECODING_IN          : in    std_logic_vector(31 downto 0); -- swap
 	PC_EVENT_ID_IN          : in    std_logic_vector(31 downto 0); -- swap
 	PC_TRIG_NR_IN           : in    std_logic_vector(31 downto 0); -- store and swap!
 	PC_TRIGGER_TYPE_IN      : in	std_logic_vector(3 downto 0);
 	PC_QUEUE_DEC_IN         : in    std_logic_vector(31 downto 0); -- swap
-	PC_MAX_FRAME_SIZE_IN    : in	std_logic_vector(15 downto 0); -- DO NOT SWAP
-	PC_MAX_QUEUE_SIZE_IN    : in    std_logic_vector(31 downto 0);
-	PC_DELAY_IN             : in	std_logic_vector(31 downto 0);  -- gk 28.04.10
 	PC_INSERT_TTYPE_IN      : in    std_logic;
 	-- FrameConstructor ports
 	TC_RD_EN_IN             : in    std_logic;
@@ -50,10 +44,6 @@ architecture RTL of trb_net16_gbe_event_constr is
 
 attribute syn_encoding	: string;
 
---type saveStates is (IDLE, SAVE_DATA, CLEANUP);
---signal save_current_state, save_next_state : saveStates;
---attribute syn_encoding of save_current_state : signal is "onehot";
-
 type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP);
 signal load_current_state, load_next_state : loadStates;
 attribute syn_encoding of load_current_state : signal is "onehot";
@@ -62,7 +52,7 @@ type saveSubHdrStates is (IDLE, SAVE_SIZE, SAVE_DECODING, SAVE_ID, SAVE_TRG_NR);
 signal save_sub_hdr_current_state, save_sub_hdr_next_state : saveSubHdrStates;
 attribute syn_encoding of save_sub_hdr_current_state : signal is "onehot";
 
-signal df_eod, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic;
+signal df_eos, df_wr_en, df_rd_en, df_empty, df_full, load_eod : std_logic;
 signal df_q, df_qq : std_logic_vector(7 downto 0);
 	
 signal header_ctr : integer range 0 to 31;
@@ -72,82 +62,45 @@ signal shf_wr_en, shf_rd_en, shf_empty, shf_full : std_logic;
 signal sub_int_ctr : integer range 0 to 3;
 signal sub_size_to_save : std_logic_vector(31 downto 0);
 
-signal fc_data : std_logic_vector(7 downto 0);
-
 signal qsf_data : std_logic_vector(31 downto 0);
-signal qsf_q, qsf_qq : std_logic_vector(7 downto 0);
+signal qsf_q : std_logic_vector(7 downto 0);
 signal qsf_wr, qsf_wr_en, qsf_wr_en_q, qsf_wr_en_qq, qsf_wr_en_qqq, qsf_rd_en, qsf_rd_en_q, qsf_empty : std_logic;
 
 signal queue_size : std_logic_vector(31 downto 0);
 
 signal termination : std_logic_vector(255 downto 0);
 signal term_ctr : integer range 0 to 33;
-signal size_for_padding : std_logic_vector(7 downto 0);
 
 signal actual_q_size : std_logic_vector(15 downto 0);
 signal tc_data : std_logic_vector(7 downto 0);
 signal df_data : std_logic_vector(7 downto 0);
-signal df_eod_q, df_eod_qq : std_logic;
+signal df_eos_q, df_eos_qq : std_logic;
 signal df_wr_en_q, df_wr_en_qq : std_logic;
-signal qsf_full, df_afull : std_logic;
+signal qsf_full : std_logic;
 
 signal padding_needed, insert_padding : std_logic;
 signal load_eod_q : std_logic;
+signal loaded_queue_bytes : std_logic_vector(15 downto 0);
+signal shf_padding : std_logic;
+signal block_shf_after_divide, previous_tc_rd : std_logic;
 
 begin
-
+	
 --*******
 -- SAVING PART
 --*******
 
---SAVE_MACHINE_PROC : process(CLK)
---begin
---	if rising_edge(CLK) then
---		if (RESET = '1') then
---			save_current_state <= IDLE;
---		else
---			save_current_state <= save_next_state;
---		end if;
---	end if;
---end process SAVE_MACHINE_PROC;
---
---SAVE_MACHINE : process(save_current_state, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN)
---begin
---	case (save_current_state) is
---
---		when IDLE =>
---			if (PC_START_OF_SUB_IN = '1') then
---				save_next_state <= SAVE_DATA;
---			else
---				save_next_state <= IDLE;
---			end if;
---		
---		when SAVE_DATA =>
---			if (PC_END_OF_DATA_IN = '1') then
---				save_next_state <= CLEANUP;
---			else
---				save_next_state <= SAVE_DATA;
---			end if;
---		
---		when CLEANUP =>
---			save_next_state <= IDLE;
---		
---		when others => save_next_state <= IDLE;
---
---	end case;
---end process SAVE_MACHINE;
-
 DF_EOD_PROC : process(CLK)
 begin
 	if rising_edge(CLK) then
-		if (PC_END_OF_DATA_IN = '1') then
-			df_eod <= '1';
+		if (PC_END_OF_SUB_IN = '1') then
+			df_eos <= '1';
 		else
-			df_eod <= '0';
+			df_eos <= '0';
 		end if;
 		
-		df_eod_q <= df_eod;
-		df_eod_qq <= df_eod_q;
+		df_eos_q <= df_eos;
+		df_eos_qq <= df_eos_q;
 	end if; 
 end process DF_EOD_PROC;
 
@@ -167,10 +120,10 @@ begin
 	end if;
 end process DF_WR_EN_PROC;
 
-DATA_FIFO : fifo_32kx9_flags --fifo_64kx9
+DATA_FIFO : fifo_64kx9
 port map(
-	Data(7 downto 0) =>  df_data, --PC_DATA_IN,
-	Data(8)          =>  df_eod_q,
+	Data(7 downto 0) =>  df_data,
+	Data(8)          =>  df_eos_q,
 	WrClock          =>  CLK,
 	RdClock          =>  CLK,
 	WrEn             =>  df_wr_en_qq,
@@ -180,8 +133,7 @@ port map(
 	Q(7 downto 0)    =>  df_q,
 	Q(8)             =>  load_eod,
 	Empty            =>  df_empty,
-	Full             =>  df_full,
-	AlmostFull            =>  df_afull
+	Full             =>  df_full
 );
 
 DF_QQ_PROC : process(CLK)
@@ -194,32 +146,27 @@ end process DF_QQ_PROC;
 READY_PROC : process(CLK)
 begin
 	if rising_edge(CLK) then
-		--if (save_current_state = IDLE and df_full = '0') then
---		if (df_full = '0') then
---			PC_READY_OUT <= '1';
---		else
---			PC_READY_OUT <= '0';
---		end if;
-		PC_READY_OUT <= not df_afull; --not qsf_full;
+		PC_READY_OUT <= not df_full;
 	end if;	
 end process READY_PROC;
 
 --*****
 -- subevent headers
-SUBEVENT_HEADERS_FIFO : fifo_4kx8_ecp3
+SUBEVENT_HEADERS_FIFO : fifo_4096x9 --fifo_4kx8_ecp3
 port map(
-	Data        =>  shf_data,
-	--Clock       => CLK,
-	WrClock       =>  CLK,
+	Data(7 downto 0) => shf_data,
+	Data(8)     => PC_SUB_SIZE_IN(2),
+	WrClock     => CLK,
 	RdClock		=> CLK,
-	WrEn        =>  shf_wr_en,
-	RdEn        =>  shf_rd_en,
-	Reset       =>  RESET,
+	WrEn        => shf_wr_en,
+	RdEn        => shf_rd_en,
+	Reset       => RESET,
 	RPReset		=> RESET,
-	Q           =>  shf_q,
-	Empty       =>  shf_empty,
-	Full        =>  shf_full
-);
+	Q(7 downto 0)    => shf_q,
+	Q(8)             => shf_padding,
+	Empty       => shf_empty,
+	Full        => shf_full
+);		
 
 SHF_WR_EN_PROC : process(CLK)
 begin
@@ -232,23 +179,19 @@ begin
 	end if;
 end process SHF_WR_EN_PROC;
 
-SHF_Q_PROC : process(CLK)
+VARIOUS_SYNC : process(CLK)
 begin
 	if rising_edge(CLK) then
 		shf_qq <= shf_q;
 	end if;
-end process SHF_Q_PROC;
+end process VARIOUS_SYNC;
 
 SAVE_SUB_HDR_MACHINE_PROC : process(RESET, CLK)
 begin
 	if RESET = '1' then
 		save_sub_hdr_current_state <= IDLE;
 	elsif rising_edge(CLK) then
---		if (RESET = '1') then
---			save_sub_hdr_current_state <= IDLE;
---		else
-			save_sub_hdr_current_state <= save_sub_hdr_next_state;
---		end if;
+		save_sub_hdr_current_state <= save_sub_hdr_next_state;
 	end if;
 end process SAVE_SUB_HDR_MACHINE_PROC;
 
@@ -310,15 +253,11 @@ begin
 		end if;
 	end if;
 end process SUB_INT_CTR_PROC;
-
+  
 SUB_SIZE_TO_SAVE_PROC : process (CLK)
 begin
 	if rising_edge(CLK) then
-		if (PC_PADDING_IN = '0') then
-			sub_size_to_save <= PC_SUB_SIZE_IN + x"10";
-		else
-			sub_size_to_save <= PC_SUB_SIZE_IN + x"c";
-		end if;
+		sub_size_to_save <= PC_SUB_SIZE_IN + x"10" + x"8"; -- addition for subevent headers and subsubevent
 	end if;
 end process SUB_SIZE_TO_SAVE_PROC;
 
@@ -374,7 +313,7 @@ port map(
 	Full        =>  qsf_full
 );
 
-qsf_wr <= qsf_wr_en_qqq or qsf_wr_en_q or qsf_wr_en_qq;
+qsf_wr <= qsf_wr_en_qqq or qsf_wr_en_qq or qsf_wr_en_q;
 
 QSF_DATA_PROC : process(CLK)
 begin
@@ -404,59 +343,29 @@ end process QSF_DATA_PROC;
 QSF_WR_PROC : process(CLK)
 begin
 	if rising_edge(CLK) then
-	
 		qsf_wr_en_q   <= qsf_wr_en;
 		qsf_wr_en_qq  <= qsf_wr_en_q;
 		qsf_wr_en_qqq <= qsf_wr_en_qq;
-	
-		if (MULT_EVT_ENABLE_IN = '1') then
-			if (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
-				if (queue_size + x"10" + PC_SUB_SIZE_IN > PC_MAX_QUEUE_SIZE_IN) then
-					qsf_wr_en <= '1';
-				else
-					qsf_wr_en <= '0';
-				end if;
-			else
-				qsf_wr_en <= '0';
-			end if;
-		else
-			if (PC_END_OF_DATA_IN = '1') then
-				qsf_wr_en <= '1';
-			else
-				qsf_wr_en <= '0';
-			end if; 
-		end if;
+		
+		qsf_wr_en <= PC_END_OF_QUEUE_IN;
 	end if;
 end process QSF_WR_PROC;
 
-QUEUE_SIZE_PROC : process(CLK)
+QUEUE_SIZE_PROC : process(RESET, CLK)
 begin
-	if rising_edge(CLK) then
-		if (MULT_EVT_ENABLE_IN = '1') then
-			if (save_sub_hdr_next_state = SAVE_DECODING and sub_int_ctr = 3) then
-				queue_size <= x"0000_0000"; --queue_size <= x"0000_0028";
-			elsif (save_sub_hdr_current_state = SAVE_DECODING and sub_int_ctr = 2) then
-				if (PC_SUB_SIZE_IN(2) = '1') then
-					queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"4" + x"8";
-				else
-					queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"8";
-				end if;
+	if RESET = '1' then
+		queue_size <= x"0000_0008"; -- queue headers
+	elsif rising_edge(CLK) then
+		if (qsf_wr_en_qqq = '1') then
+			queue_size <= x"0000_0008";
+		elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
+			if (PC_SUB_SIZE_IN(2) = '1') then
+				queue_size <= queue_size + PC_SUB_SIZE_IN + x"4" + x"10" + x"8";  -- subevent data size + padding + subevent headers + subsubevent 
 			else
-				queue_size <= queue_size;
+				queue_size <= queue_size + PC_SUB_SIZE_IN + x"10" + x"8";  -- subevent data size + subevent headers + subsubevent
 			end if;
 		else
-			--if (save_current_state = IDLE) then
-			if (PC_START_OF_SUB_IN = '1') then
-				queue_size <= x"0000_0000"; --queue_size <= x"0000_0028";
-			elsif (save_sub_hdr_current_state = SAVE_SIZE and sub_int_ctr = 0) then
-				if (PC_SUB_SIZE_IN(2) = '1') then
-					queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"4" + x"8";
-				else
-					queue_size <= queue_size + x"10" + PC_SUB_SIZE_IN + x"8";
-				end if;
-			else
-				queue_size <= queue_size;
-			end if;			
+			queue_size <= queue_size;
 		end if;
 	end if;
 end process QUEUE_SIZE_PROC;
@@ -487,15 +396,11 @@ begin
 	if RESET = '1' then
 		load_current_state <= IDLE;
 	elsif rising_edge(CLK) then
---		if (RESET = '1') then
---			load_current_state <= IDLE;
---		else
-			load_current_state <= load_next_state;
---		end if;
+		load_current_state <= load_next_state;
 	end if;
 end process LOAD_MACHINE_PROC;
 
-LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod_q, term_ctr, insert_padding)
+LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod_q, term_ctr, insert_padding, loaded_queue_bytes, actual_q_size)
 begin
 	case (load_current_state) is
 	
@@ -521,7 +426,7 @@ begin
 				load_next_state <= LOAD_SUB;
 			else
 				load_next_state <= LOAD_Q_HEADERS;
-			end if;
+			end if;			
 			
 		when LOAD_SUB =>
 			if (header_ctr = 0) then
@@ -532,11 +437,14 @@ begin
 			
 		when LOAD_DATA =>
 			if (load_eod_q = '1' and term_ctr = 33) then
-				--if (size_for_padding(2) = '0') then
 				if (insert_padding = '1') then
 					load_next_state <= LOAD_PADDING;
 				else
-					load_next_state <= LOAD_TERM;
+					if (loaded_queue_bytes = actual_q_size) then
+						load_next_state <= LOAD_TERM;
+					else
+						load_next_state <= LOAD_SUB;
+					end if;
 				end if;
 			else
 				load_next_state <= LOAD_DATA;
@@ -544,7 +452,11 @@ begin
 			
 		when LOAD_PADDING =>
 			if (header_ctr = 0) then
-				load_next_state <= LOAD_TERM;
+				if (loaded_queue_bytes = actual_q_size) then
+					load_next_state <= LOAD_TERM;
+				else
+					load_next_state <= LOAD_SUB;
+				end if;
 			else
 				load_next_state <= LOAD_PADDING;
 			end if;			
@@ -585,11 +497,23 @@ begin
 				header_ctr <= 31;
 			end if;
 		elsif (load_current_state = LOAD_PADDING and header_ctr = 0) then
+			if (loaded_queue_bytes = actual_q_size) then
+				header_ctr <= 31;
+			else
+				header_ctr <= 15;
+			end if;
+		elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes = actual_q_size and insert_padding = '0') then
 			header_ctr <= 31;
+		elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '0') then
+			header_ctr <= 15;	
+		elsif (load_current_state = LOAD_DATA and load_eod_q = '1' and term_ctr = 33 and loaded_queue_bytes /= actual_q_size and insert_padding = '1') then
+			header_ctr <= 3;	
 		elsif (load_current_state = LOAD_TERM and header_ctr = 0) then
 			header_ctr <= 3;
 		elsif (TC_RD_EN_IN = '1') then
-			if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_SUB or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then
+			if (load_current_state = LOAD_Q_HEADERS or load_current_state = LOAD_TERM or load_current_state = LOAD_PADDING) then
+				header_ctr <= header_ctr - 1;
+			elsif (load_current_state = LOAD_SUB and block_shf_after_divide = '0') then
 				header_ctr <= header_ctr - 1;
 			else
 				header_ctr <= header_ctr;
@@ -603,17 +527,12 @@ begin
 end process HEADER_CTR_PROC;
 
 SIZE_FOR_PADDING_PROC : process(CLK)
-begin
+begin	
 	if rising_edge(CLK) then
---		if (load_current_state = START_TRANSFER) then
---			size_for_padding <= qsf_q;
---		else
---			size_for_padding <= size_for_padding;
---		end if;
 		if (load_current_state = IDLE) then
 			insert_padding <= '0';
-		elsif (load_current_state = GET_Q_SIZE and header_ctr = 2) then
-			insert_padding <= qsf_q(7);
+		elsif (load_current_state = LOAD_SUB and header_ctr = 12) then
+			insert_padding <= shf_padding;
 		else
 			insert_padding <= insert_padding;
 		end if;
@@ -631,18 +550,41 @@ begin
 	end if;
 end process TC_SOD_PROC;
 
+process(CLK)
+begin
+	if rising_edge(CLK) then
+		if (load_current_state = IDLE) then
+			loaded_queue_bytes <= (others => '0');
+		elsif (TC_RD_EN_IN = '1') then
+			loaded_queue_bytes <= loaded_queue_bytes + x"1";
+		else
+			loaded_queue_bytes <= loaded_queue_bytes;
+		end if;
+	end if;
+end process;
+
 --*****
 -- read from fifos
 
 df_rd_en <= '1' when (load_current_state = LOAD_DATA and TC_RD_EN_IN = '1' and load_eod_q = '0') or 
 					(load_current_state = LOAD_SUB and header_ctr = 0 and TC_RD_EN_IN = '1')
-					--(load_current_state = LOAD_SUB and header_ctr = 1 and TC_RD_EN_IN = '1')
 					else '0';
 
-shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1' and header_ctr /= 0) or
-					(load_current_state = LOAD_Q_HEADERS and header_ctr = 0 and TC_RD_EN_IN = '1')
+shf_rd_en <= '1' when (load_current_state = LOAD_SUB and TC_RD_EN_IN = '1' and header_ctr /= 0 and block_shf_after_divide = '0') or
+					(load_current_state = LOAD_Q_HEADERS and header_ctr = 0 and TC_RD_EN_IN = '1') or
+					(load_current_state = LOAD_DATA and load_eod_q = '1' and (loaded_queue_bytes /= actual_q_size) and (loaded_queue_bytes + x"4" /= actual_q_size))
 					else '0';
 
+
+-- nasty workaround for the case when the packet is divided on LOAD_SUB state
+process(CLK)
+begin
+	if rising_edge(CLK) then
+		previous_tc_rd <= TC_RD_EN_IN;
+	end if;
+end process;
+block_shf_after_divide <= '1' when previous_tc_rd = '0' and TC_RD_EN_IN = '1' and header_ctr = 15 else '0';
+
 QUEUE_FIFO_RD_PROC : process(CLK)
 begin
 	if rising_edge(CLK) then
@@ -650,8 +592,6 @@ begin
 			qsf_rd_en_q <= '1';
 		elsif (load_current_state = IDLE and qsf_empty = '0') then
 			qsf_rd_en_q <= '1';
---		elsif (load_current_state = LOAD_Q_HEADERS and TC_RD_EN_IN = '1' and header_ctr /= 0) then
---			qsf_rd_en <= '1';
 		else 
 			qsf_rd_en_q <= '0';
 		end if;
@@ -671,7 +611,7 @@ begin
 	end if;
 end process ACTUAL_Q_SIZE_PROC;
 
-TC_EVENT_SIZE_OUT <= actual_q_size;
+TC_EVENT_SIZE_OUT <= actual_q_size;  -- queue size without termination
 
 TERMINATION_PROC : process(CLK)
 begin
diff --git a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
index 4211f26..78ba39d 100644
--- a/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd
@@ -13,8 +13,9 @@ use work.trb_net16_hub_func.all;
 use work.trb_net_gbe_components.all;
 use work.trb_net_gbe_protocols.all;
 
+
 entity trb_net16_gbe_ipu_interface is
-	port (
+port (
 	CLK_IPU                     : in    std_logic;
 	CLK_GBE                     : in	std_logic;
 	RESET                       : in    std_logic;
@@ -43,21 +44,21 @@ entity trb_net16_gbe_ipu_interface is
 	DATA_GBE_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to GbE
 	DATA_IPU_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to CTS / TRBnet
 	MULT_EVT_ENABLE_IN			: in    std_logic;
-	MAX_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue  -- gk 08.04.10
-	MIN_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- gk 20.07.10
+	MAX_SUBEVENT_SIZE_IN		: in	std_logic_vector(15 downto 0);
+	MAX_QUEUE_SIZE_IN           : in    std_logic_vector(15 downto 0);
+	MAX_SUBS_IN_QUEUE_IN        : in    std_logic_vector(15 downto 0);
+	MAX_SINGLE_SUB_SIZE_IN      : in    std_logic_vector(15 downto 0);
 	READOUT_CTR_IN				: in	std_logic_vector(23 downto 0); -- gk 26.04.10
-	READOUT_CTR_VALID_IN			: in	std_logic; -- gk 26.04.10
+	READOUT_CTR_VALID_IN		: in	std_logic; -- gk 26.04.10
 	-- PacketConstructor interface
-	ALLOW_LARGE_IN				: in	std_logic;  -- gk 21.07.10
 	PC_WR_EN_OUT                : out   std_logic;
 	PC_DATA_OUT                 : out   std_logic_vector (7 downto 0);
 	PC_READY_IN                 : in    std_logic;
 	PC_SOS_OUT                  : out   std_logic;
-	PC_EOS_OUT                  : out   std_logic; -- gk 07.10.10
-	PC_EOD_OUT                  : out   std_logic;
+	PC_EOS_OUT                  : out   std_logic;
+	PC_EOQ_OUT                  : out   std_logic;
 	PC_SUB_SIZE_OUT             : out   std_logic_vector(31 downto 0);
 	PC_TRIG_NR_OUT              : out   std_logic_vector(31 downto 0);
-	PC_PADDING_OUT              : out   std_logic;
 	PC_TRIGGER_TYPE_OUT         : out	std_logic_vector(3 downto 0);
 	MONITOR_OUT                 : out   std_logic_vector(223 downto 0);
 	DEBUG_OUT                   : out   std_logic_vector(383 downto 0)
@@ -68,16 +69,16 @@ architecture RTL of trb_net16_gbe_ipu_interface is
 
 attribute syn_encoding : string;
 
-type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, CLEANUP);
+type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, FINISH_4_WORDS, CLEANUP);
 signal save_current_state, save_next_state : saveStates;
 attribute syn_encoding of save_current_state : signal is "onehot";
 
-type loadStates is (IDLE, REMOVE, WAIT_ONE, DECIDE, WAIT_FOR_LOAD, LOAD, CLOSE);
+type loadStates is (IDLE, WAIT_FOR_SUBS, REMOVE, WAIT_ONE, WAIT_TWO, DECIDE, PREPARE_TO_LOAD_SUB, WAIT_FOR_LOAD, LOAD, CLOSE_PACKET, CLOSE_SUB, CLOSE_QUEUE, CLOSE_QUEUE_IMMEDIATELY);
 signal load_current_state, load_next_state : loadStates;
 attribute syn_encoding of load_current_state : signal is "onehot";
 
 signal sf_data : std_Logic_vector(15 downto 0);
-signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eod, sf_eod_q, sf_eod_qq : std_logic;
+signal save_eod, sf_wr_en, sf_rd_en, sf_reset, sf_empty, sf_full, sf_afull, sf_eos : std_logic;
 signal sf_q, pc_data : std_logic_vector(7 downto 0);
 
 signal cts_rnd, cts_trg : std_logic_vector(15 downto 0);
@@ -97,6 +98,14 @@ signal pc_ready_q : std_logic;
 signal sf_afull_q : std_logic;
 signal sf_aempty : std_logic;
 signal rec_state, load_state : std_logic_vector(3 downto 0);
+signal queue_size : std_logic_vector(17 downto 0);
+signal number_of_subs : std_logic_vector(15 downto 0);
+signal size_check_ctr : integer range 0 to 7;
+signal sf_data_q, sf_data_qq, sf_data_qqq, sf_data_qqqq, sf_data_qqqqq : std_logic_vector(15 downto 0);
+signal sf_wr_q, sf_wr_lock : std_logic;
+signal save_eod_q, save_eod_qq, save_eod_qqq, save_eod_qqqq, save_eod_qqqqq : std_logic;
+signal too_large_dropped : std_logic_vector(31 downto 0);
+signal previous_ttype, previous_bank : std_logic_vector(3 downto 0);
 
 begin
 
@@ -107,17 +116,13 @@ begin
 SAVE_MACHINE_PROC : process(RESET, CLK_IPU)
 begin
 	if RESET = '1' then
-			save_current_state <= IDLE;
+		save_current_state <= IDLE;
 	elsif rising_edge(CLK_IPU) then
---		if (RESET = '1') then
---			save_current_state <= IDLE;
---		else
-			save_current_state <= save_next_state;
---		end if;
+		save_current_state <= save_next_state;
 	end if;
 end process SAVE_MACHINE_PROC;
 
-SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
+SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, size_check_ctr)
 begin
 	case (save_current_state) is
 	
@@ -179,10 +184,18 @@ begin
 			
 		when ADD_SUBSUB4 =>
 			rec_state <= x"a";
-			save_next_state <= CLEANUP;
+			save_next_state <= FINISH_4_WORDS;
 			
-		when CLEANUP =>
+		when FINISH_4_WORDS =>
 			rec_state <= x"b";
+			if (size_check_ctr = 1) then
+				save_next_state <= CLEANUP;
+			else
+				save_next_state <= FINISH_4_WORDS;
+			end if;
+			
+		when CLEANUP =>
+			rec_state <= x"c";
 			save_next_state <= IDLE;
 		 
 	end case;
@@ -199,23 +212,11 @@ begin
 			sf_wr_en <= '1';
 		elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then
 			sf_wr_en <= '1';
+		elsif (save_current_state = FINISH_4_WORDS) then
+			sf_wr_en <= '1';
 		else
 			sf_wr_en <= '0';
 		end if;
-		
---		if (sf_afull_q = '0') then
---			if (save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then
---				sf_wr_en <= '1';
---			elsif (save_current_state = SAVE_EVT_ADDR) then
---				sf_wr_en <= '1';
---			elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then
---				sf_wr_en <= '1';
---			else
---				sf_wr_en <= '0';
---			end if;
---		else
---			sf_wr_en <= '0';
---		end if;
 	end if;
 end process SF_WR_EN_PROC;
 
@@ -256,12 +257,84 @@ begin
 	end if;
 end process SF_DATA_EOD_PROC;
 
+process(CLK_IPU)
+begin
+	if rising_edge(CLK_IPU) then
+		if (sf_wr_en = '1') then
+			sf_data_q    <= sf_data;
+			sf_data_qq   <= sf_data_q;
+			sf_data_qqq  <= sf_data_qq;
+			sf_data_qqqq <= sf_data_qqq;
+			sf_data_qqqqq <= sf_data_qqqq;
+			
+			save_eod_q     <= save_eod;
+			save_eod_qq    <= save_eod_q;
+			save_eod_qqq   <= save_eod_qq;
+			save_eod_qqqq  <= save_eod_qqq;
+			save_eod_qqqqq  <= save_eod_qqqq;
+		else
+			sf_data_q    <= sf_data_q;
+			sf_data_qq   <= sf_data_qq;
+			sf_data_qqq  <= sf_data_qqq;
+			sf_data_qqqq <= sf_data_qqqq;
+			sf_data_qqqqq <= sf_data_qqqqq;
+			
+			save_eod_q     <= save_eod_q;
+			save_eod_qq    <= save_eod_qq;
+			save_eod_qqq   <= save_eod_qqq;
+			save_eod_qqqq  <= save_eod_qqqq;
+			save_eod_qqqqq  <= save_eod_qqqq;
+		end if;
+		
+sf_wr_q <= sf_wr_en and not sf_wr_lock;
+
+	end if;
+end process;
+
+process(CLK_IPU)
+begin
+	if rising_edge(CLK_IPU) then
+		if (save_current_state = IDLE) then
+			size_check_ctr <= 0;
+		elsif (save_current_state = SAVE_DATA and sf_wr_en = '1' and size_check_ctr /= 4) then
+			size_check_ctr <= size_check_ctr + 1;
+		elsif (save_current_state = FINISH_4_WORDS and size_check_ctr /= 0) then
+			size_check_ctr <= size_check_ctr - 1;
+		else
+			size_check_ctr <= size_check_ctr;
+		end if;
+		
+		if (save_current_state = IDLE) then
+			sf_wr_lock <= '1';
+		elsif (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then  -- condition to ALLOW an event to be passed forward
+			sf_wr_lock <= '0';
+		else
+			sf_wr_lock <= sf_wr_lock;
+		end if;
+
+	end if;
+end process;
+
+process(RESET, CLK_IPU)
+begin
+	if (RESET = '1') then
+		too_large_dropped <= (others => '0');
+	elsif rising_edge(CLK_IPU) then
+		if (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") >= ("00" & MAX_SUBEVENT_SIZE_IN)) then
+			too_large_dropped <= too_large_dropped + x"1";
+		else
+			too_large_dropped <= too_large_dropped;
+		end if;
+	end if;
+end process;
+		
+
 SAVED_EVENTS_CTR_PROC : process(RESET, CLK_IPU)
 begin
 	if (RESET = '1') then
 		saved_events_ctr <= (others => '0');
 	elsif rising_edge(CLK_IPU) then
-		if (save_current_state = ADD_SUBSUB4) then
+		if (save_current_state = ADD_SUBSUB4 and sf_wr_lock = '0') then
 			saved_events_ctr <= saved_events_ctr + x"1";
 		else
 			saved_events_ctr <= saved_events_ctr;
@@ -351,20 +424,20 @@ end process FEE_READ_PROC;
 THE_SPLIT_FIFO: fifo_32kx16x8_mb2 --fifo_16kx18x9
 port map( 
 	-- Byte swapping for correct byte order on readout side of FIFO
-	Data(7 downto 0)  => sf_data(15 downto 8),
+	Data(7 downto 0)  => sf_data_qqqqq(15 downto 8),
 	Data(8)           => '0',
-	Data(16 downto 9) => sf_data(7 downto 0),
-	Data(17)          => save_eod,
+	Data(16 downto 9) => sf_data_qqqqq(7 downto 0),
+	Data(17)          => save_eod_qqqqq,
 	WrClock           => CLK_IPU,
 	RdClock           => CLK_GBE,
-	WrEn              => sf_wr_en,
+	WrEn              => sf_wr_q,  -- sf_wr_en
 	RdEn              => sf_rd_en,
 	Reset             => sf_reset,
 	RPReset           => sf_reset,
 	AmEmptyThresh     => b"0000_0000_0000_0010", --b"0000_0000_0000_0010", -- one byte ahead
-	AmFullThresh      => b"001_0011_1000_1000", --b"111_1111_1110_1111", -- 0x7fef = 32751
+	AmFullThresh      => b"111_1111_1110_1111", -- 0x7fef = 32751 -- b"001_0011_1000_1000"
 	Q(7 downto 0)     => sf_q,
-	Q(8)              => sf_eod,
+	Q(8)              => sf_eos,
 	--WCNT              => open,
 	--RCNT              => open,
 	Empty             => sf_empty,
@@ -375,19 +448,6 @@ port map(
 
 sf_reset <= RESET;
 
---SF_RESET_PROC : process(CLK_IPU)
---begin
---	if rising_edge(CLK_IPU) then
---		if (RESET = '1') then
---			sf_reset <= '1';
---		elsif (save_current_state = DROP_SUBEVENT) then
---			sf_reset <= '1';
---		else
---			sf_reset <= '0';
---		end if;
---	end if;
---end process SF_RESET_PROC;
-
 --*********
 -- LOADING PART
 --*********
@@ -404,28 +464,31 @@ begin
 	if RESET = '1' then
 		load_current_state <= IDLE;
 	elsif rising_edge(CLK_GBE) then
---		if (RESET = '1') then
---			load_current_state <= IDLE;
---		else
-			load_current_state <= load_next_state;
---		end if;
+		load_current_state <= load_next_state;
 	end if;
 end process LOAD_MACHINE_PROC;
 
-LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eod)
+LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eos, queue_size, number_of_subs, 
+						subevent_size, MAX_QUEUE_SIZE_IN, MAX_SUBS_IN_QUEUE_IN, MAX_SINGLE_SUB_SIZE_IN, previous_bank, previous_ttype, trigger_type, 
+						bank_select, MULT_EVT_ENABLE_IN
+)
 begin
 	case (load_current_state) is
 
 		when IDLE =>
 			load_state <= x"1";
+			load_next_state <= WAIT_FOR_SUBS;
+			
+		when WAIT_FOR_SUBS =>
+			load_state <= x"2";
 			if (saved_events_ctr_gbe /= loaded_events_ctr) then
 				load_next_state <= REMOVE;
 			else
-				load_next_state <= IDLE;
+				load_next_state <= WAIT_FOR_SUBS;
 			end if;
 		
 		when REMOVE =>
-			load_state <= x"2";
+			load_state <= x"3";
 			if (loaded_bytes_ctr = x"0008") then
 				load_next_state <= WAIT_ONE;
 			else
@@ -433,15 +496,36 @@ begin
 			end if;
 			
 		when WAIT_ONE =>
-			load_state <= x"3";
+			load_state <= x"4";
+			load_next_state <= WAIT_TWO;
+			
+		when WAIT_TWO =>
+			load_state <= x"4";
 			load_next_state <= DECIDE;
 		
+		--TODO: all queue split conditions here and also in the size process
 		when DECIDE =>
-			load_state <= x"4";
+			load_state <= x"5";
+			if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then  -- max udp packet exceeded
+				load_next_state <= CLOSE_QUEUE;
+			elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
+				load_next_state <= CLOSE_QUEUE;
+			elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then
+				load_next_state <= CLOSE_QUEUE;
+			elsif (trigger_type /= previous_ttype and previous_ttype /= x"0") then
+				load_next_state <= CLOSE_QUEUE;
+			elsif (bank_select /= previous_bank and previous_ttype /= x"0") then
+				load_next_state <= CLOSE_QUEUE;
+			else
+				load_next_state <= PREPARE_TO_LOAD_SUB;
+			end if;
+		
+		when PREPARE_TO_LOAD_SUB =>
+			load_state <= x"6";
 			load_next_state <= WAIT_FOR_LOAD;
 			
 		when WAIT_FOR_LOAD =>
-			load_state <= x"5";
+			load_state <= x"7";
 			if (PC_READY_IN = '1') then
 				load_next_state <= LOAD;
 			else
@@ -449,16 +533,29 @@ begin
 			end if;
 		
 		when LOAD =>
-			load_state <= x"6";
-			if (sf_eod = '1') then
-				load_next_state <= CLOSE;
+			load_state <= x"8";
+			if (sf_eos = '1') then
+				load_next_state <= CLOSE_SUB;
 			else
 				load_next_state <= LOAD;
 			end if;
 		
-		when CLOSE =>
-			load_state <= x"7";
-			load_next_state <= IDLE;
+		when CLOSE_SUB =>
+			load_state <= x"9";
+			if (subevent_size > ("00" & MAX_SINGLE_SUB_SIZE_IN) and queue_size = (subevent_size + x"10" + x"8" + x"4")) then
+				load_next_state <= CLOSE_QUEUE_IMMEDIATELY;
+			else
+				load_next_state <= WAIT_FOR_SUBS;
+			end if;
+			
+		when CLOSE_QUEUE =>
+			load_state <= x"a";
+			load_next_state <= PREPARE_TO_LOAD_SUB;
+			
+		when CLOSE_QUEUE_IMMEDIATELY =>
+			load_state <= x"b";
+			load_next_state <= WAIT_FOR_SUBS;
+			
 		
 		when others => load_next_state <= IDLE;
 
@@ -479,7 +576,54 @@ port map(
 );
 
 
---TODO: create a proper read signal here
+--TODO: all queue split conditions here 
+-- the queue size counter used only for closing current queue
+-- sums up all subevent sizes with their headers and stuff
+process(CLK_GBE)
+begin
+	if rising_edge(CLK_GBE) then
+		if (load_current_state = IDLE) then
+			queue_size <= (others => '0');
+		elsif (load_current_state = CLOSE_QUEUE_IMMEDIATELY) then
+			queue_size <= (others => '0');
+		elsif (load_current_state = WAIT_TWO) then
+			queue_size <= queue_size + subevent_size + x"10" + x"8" + x"4";
+		elsif (load_current_state = DECIDE) then
+			if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then
+				queue_size <= subevent_size + x"10" + x"8" + x"4";
+--			elsif (number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
+--				queue_size <= subevent_size + x"10" + x"8" + x"4";
+			elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then
+				queue_size <= subevent_size + x"10" + x"8" + x"4";
+			elsif (MULT_EVT_ENABLE_IN = '0' and number_of_subs = 1) then
+				queue_size <= subevent_size + x"10" + x"8" + x"4";
+			elsif (trigger_type /= previous_ttype and previous_ttype /= x"0") then
+				queue_size <= subevent_size + x"10" + x"8" + x"4";
+			elsif (bank_select /= previous_bank and previous_ttype /= x"0") then
+				queue_size <= subevent_size + x"10" + x"8" + x"4";
+			else
+				queue_size <= queue_size;
+			end if;
+		else
+			queue_size <= queue_size;
+		end if;
+	end if;
+end process;
+
+process(CLK_GBE)
+begin
+	if rising_edge(CLK_GBE) then
+		if (load_current_state = IDLE or load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then
+			number_of_subs <= (others => '0');
+		elsif (load_current_state = PREPARE_TO_LOAD_SUB) then
+			number_of_subs <= number_of_subs + x"1";
+		else
+			number_of_subs <= number_of_subs;
+		end if;
+	end if;
+end process;
+
+
 SF_RD_EN_PROC : process(CLK_GBE)
 begin
 	if rising_edge(CLK_GBE) then
@@ -500,6 +644,22 @@ end process SF_RD_EN_PROC;
 --*****
 -- information extraction
 
+process(CLK_GBE)
+begin
+	if rising_edge(CLK_GBE) then
+		if (load_current_state = IDLE) then
+			previous_bank  <= x"0";
+			previous_ttype <= x"0";
+		elsif (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY or load_current_state = CLOSE_SUB) then
+			previous_bank  <= bank_select;
+			previous_ttype <= trigger_type;
+		else
+			previous_bank  <= previous_bank;
+			previous_ttype <= previous_ttype;
+		end if;
+	end if;
+end process;
+
 TRIGGER_RANDOM_PROC : process(CLK_GBE)
 begin
 	if rising_edge(CLK_GBE) then
@@ -537,8 +697,6 @@ begin
 			subevent_size(9 downto 2) <= pc_data; 
 		elsif (load_current_state = REMOVE and sf_rd_en = '1' and loaded_bytes_ctr = x"0008") then
 			subevent_size(17 downto 10) <= pc_data;
-		elsif (load_current_state = DECIDE) then
-			subevent_size <= subevent_size + x"8";
 		else
 			subevent_size <= subevent_size;
 		end if;
@@ -563,13 +721,13 @@ end process TRIGGER_TYPE_PROC;
 
 --*****
 -- counters
-
+	
 LOADED_EVENTS_CTR_PROC : process(RESET, CLK_GBE)
 begin
 	if (RESET = '1') then
 		loaded_events_ctr <= (others => '0');
 	elsif rising_edge(CLK_GBE) then
-		if (load_current_state = CLOSE) then
+		if (load_current_state = CLOSE_SUB) then
 			loaded_events_ctr <= loaded_events_ctr + x"1";
 		else
 			loaded_events_ctr <= loaded_events_ctr;
@@ -580,10 +738,10 @@ end process LOADED_EVENTS_CTR_PROC;
 LOADED_BYTES_CTR_PROC : process(CLK_GBE)
 begin
 	if rising_edge(CLK_GBE) then
-		if (load_current_state = IDLE or load_current_state = DECIDE) then
+		if (load_current_state = WAIT_FOR_SUBS) then
 			loaded_bytes_ctr <= (others => '0');
 		elsif (sf_rd_en = '1') then
-			if (load_current_state = REMOVE or load_current_state = LOAD) then
+			if (load_current_state = REMOVE) then
 				loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
 			else
 				loaded_bytes_ctr <= loaded_bytes_ctr;
@@ -666,7 +824,7 @@ end process PC_WR_EN_PROC;
 PC_SOS_PROC : process(CLK_GBE)
 begin
 	if rising_edge(CLK_GBE) then
-		if (load_current_state = DECIDE) then
+		if (load_current_state = PREPARE_TO_LOAD_SUB) then
 			PC_SOS_OUT <= '1';
 		else
 			PC_SOS_OUT <= '0';
@@ -677,24 +835,20 @@ end process PC_SOS_PROC;
 PC_EOD_PROC : process(CLK_GBE)
 begin
 	if rising_edge(CLK_GBE) then
-		if (sf_eod = '1') then
-			sf_eod_q <= '1';
-		else
-			sf_eod_q <= '0';
-		end if;
-		
-		--sf_eod_qq <= sf_eod_q;
-		--PC_EOD_OUT <= sf_eod_qq;
-		PC_EOD_OUT <= sf_eod; --_q;
+		PC_EOS_OUT <= sf_eos;
 	end if;
 end process PC_EOD_PROC;
 
-PC_EOS_PROC : process(CLK_GBE)
+PC_EOQ_PROC : process(CLK_GBE)
 begin
 	if rising_edge(CLK_GBE) then
-		PC_EOS_OUT <= '0';
+		if (load_current_state = CLOSE_QUEUE or load_current_state = CLOSE_QUEUE_IMMEDIATELY) then
+			PC_EOQ_OUT <= '1';
+		else
+			PC_EOQ_OUT <= '0';
+		end if;
 	end if;
-end process PC_EOS_PROC;
+end process PC_EOQ_PROC;
 
 --*******
 -- outputs
@@ -707,8 +861,6 @@ PC_TRIG_NR_OUT <= readout_ctr(23 downto 16) & trigger_number & trigger_random;
 
 PC_TRIGGER_TYPE_OUT <= trigger_type;
 
-PC_PADDING_OUT <= '0'; --padding_needed; not used anymore
-
 
 process(CLK_GBE)
 begin
@@ -723,6 +875,7 @@ begin
 end process;
 
 DEBUG_OUT(383 downto 12) <= (others => '0');
-MONITOR_OUT <= (others => '0');
+MONITOR_OUT(31 downto 0) <= too_large_dropped;
+MONITOR_OUT(223 downto 32) <= (others => '0');
 
 end architecture RTL;
diff --git a/gbe2_ecp3/trb_net16_gbe_main_control.vhd b/gbe2_ecp3/trb_net16_gbe_main_control.vhd
index ed5e291..933ec78 100644
--- a/gbe2_ecp3/trb_net16_gbe_main_control.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_main_control.vhd
@@ -19,6 +19,10 @@ use work.trb_net_gbe_protocols.all;
 
 
 entity trb_net16_gbe_main_control is
+	generic(
+		RX_PATH_ENABLE : integer range 0 to 1 := 1;
+		DO_SIMULATION  : integer range 0 to 1 := 0
+	);
 port (
 	CLK			: in	std_logic;  -- system clock
 	CLK_125			: in	std_logic;
@@ -106,16 +110,21 @@ port (
 	SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
 	SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
 	
-	CFG_GBE_ENABLE_IN            : in std_logic;
-	CFG_IPU_ENABLE_IN            : in std_logic;
-	CFG_MULT_ENABLE_IN           : in std_logic;
-	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0); 
-	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0); 
-	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0); 
-	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0); 
-	CFG_READOUT_CTR_VALID_IN     : in std_logic;  
-	CFG_ADDITIONAL_HDR_IN        : in std_logic;
+	CFG_GBE_ENABLE_IN            : in std_logic;                    
+	CFG_IPU_ENABLE_IN            : in std_logic;                    
+	CFG_MULT_ENABLE_IN           : in std_logic;                    
+	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);
+	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);
+	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);
+	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
+	CFG_READOUT_CTR_VALID_IN     : in std_logic;
 	CFG_INSERT_TTYPE_IN          : in std_logic;
+	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
+	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
+	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
+	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
+	  
+	CFG_ADDITIONAL_HDR_IN        : in std_logic;   
 	
 	MAKE_RESET_OUT           : out std_logic;
 	
@@ -135,6 +144,8 @@ port (
 	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_IN_OUT    : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_OUT_OUT   : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_GEN_DBG_OUT    : out	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 	DATA_HIST_OUT : out hist_array;
@@ -239,6 +250,10 @@ begin
 unique_id <= MC_UNIQUE_ID_IN;
 
 protocol_selector : trb_net16_gbe_protocol_selector
+generic map(
+		RX_PATH_ENABLE => RX_PATH_ENABLE,
+		DO_SIMULATION  => DO_SIMULATION
+		)
 port map(
 	CLK			=> CLK,
 	RESET		=> RESET,
@@ -323,9 +338,14 @@ port map(
 	CFG_SUBEVENT_DEC_IN         => CFG_SUBEVENT_DEC_IN,      
 	CFG_QUEUE_DEC_IN            => CFG_QUEUE_DEC_IN,         
 	CFG_READOUT_CTR_IN          => CFG_READOUT_CTR_IN,       
-	CFG_READOUT_CTR_VALID_IN    => CFG_READOUT_CTR_VALID_IN,  
-	CFG_ADDITIONAL_HDR_IN       => CFG_ADDITIONAL_HDR_IN,
+	CFG_READOUT_CTR_VALID_IN    => CFG_READOUT_CTR_VALID_IN,
 	CFG_INSERT_TTYPE_IN         => CFG_INSERT_TTYPE_IN,
+	CFG_MAX_SUB_IN              => CFG_MAX_SUB_IN,
+	CFG_MAX_QUEUE_IN            => CFG_MAX_QUEUE_IN,
+	CFG_MAX_SUBS_IN_QUEUE_IN    => CFG_MAX_SUBS_IN_QUEUE_IN,
+	CFG_MAX_SINGLE_SUB_IN       => CFG_MAX_SINGLE_SUB_IN,
+	  
+	CFG_ADDITIONAL_HDR_IN       => CFG_ADDITIONAL_HDR_IN,  
 	
 	-- input for statistics from outside
 	STAT_DATA_IN       => stat_data,
@@ -337,6 +357,8 @@ port map(
 	MONITOR_SELECT_REC_BYTES_OUT  => MONITOR_SELECT_REC_BYTES_OUT,  
 	MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT, 
 	MONITOR_SELECT_SENT_OUT	      => MONITOR_SELECT_SENT_OUT,
+	MONITOR_SELECT_DROP_OUT_OUT   => MONITOR_SELECT_DROP_OUT_OUT,
+	MONITOR_SELECT_DROP_IN_OUT    => MONITOR_SELECT_DROP_IN_OUT,
 	MONITOR_SELECT_GEN_DBG_OUT    => MONITOR_SELECT_GEN_DBG_OUT,
 	
 	DATA_HIST_OUT => DATA_HIST_OUT,
@@ -385,7 +407,11 @@ begin
 --		if (RESET = '1') then
 --			redirect_current_state <= IDLE;
 --		else
+		if RX_PATH_ENABLE = 1 then
 			redirect_current_state <= redirect_next_state;
+		else
+			redirect_current_state <= IDLE;
+		end if;
 --		end if;
 	end if;
 end process REDIRECT_MACHINE_PROC;
@@ -594,7 +620,13 @@ begin
 --				link_current_state <= FINALIZE; --ACTIVE; --GET_ADDRESS; --ACTIVE;
 --			end if;
 --		else
+		if RX_PATH_ENABLE = 1 and DO_SIMULATION = 0 then
 			link_current_state <= link_next_state;
+		elsif DO_SIMULATION = 1 then
+			link_current_state <= ACTIVE;
+		else
+			link_current_state <= ACTIVE;
+		end if;
 --		end if;
 	end if;
 end process;
diff --git a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
index 46380e1..5e68bad 100755
--- a/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd
@@ -233,7 +233,7 @@ begin
 end process dfQProc;
 
 -- Construction state machine
-constructMachineProc : process(CLK)
+constructMachineProc : process(RESET, CLK)
 begin
 	if RESET = '1' then
 		constructCurrentState <= CIDLE;
@@ -246,7 +246,7 @@ begin
 	end if;
 end process constructMachineProc;
 
-constructMachine : process(constructCurrentState, PC_START_OF_SUB_IN, PC_WR_EN_IN, PC_END_OF_DATA_IN, loadCurrentState, saveSubCurrentState, sub_int_ctr)
+constructMachine : process(constructCurrentState, df_empty, PC_START_OF_SUB_IN, PC_END_OF_DATA_IN, loadCurrentState)
 begin
 	case constructCurrentState is
 		when CIDLE =>
@@ -290,7 +290,7 @@ sub_size_to_save <= (x"10" + pc_sub_size) when (PC_PADDING_IN = '0')
 
 -- BUG HERE BUG HERE BUG HERE BUG HERE
 -- gk 29.03.10 no changes here because the queue size should contain the padding bytes of subevents
-queueSizeProc : process(CLK)
+queueSizeProc : process(RESET, CLK)
 begin
 	if (RESET = '1') then
 		queue_size <= x"00000028";  -- + 8B for queue headers and 32B for termination
@@ -311,7 +311,7 @@ end process queueSizeProc;
 --      LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION
 --***********************
 
-loadMachineProc : process(CLK)
+loadMachineProc : process(RESET, CLK)
 begin
 	if RESET = '1' then
 			loadCurrentState <= LIDLE;
@@ -325,7 +325,7 @@ begin
 end process loadMachineProc;
 
 loadMachine : process(loadCurrentState, constructCurrentState, all_int_ctr, df_empty,
-					sub_bytes_loaded, sub_size_loaded, size_left, TC_H_READY_IN,
+					size_left, TC_H_READY_IN,
 					max_frame_size, bytes_loaded, divide_position, PC_DELAY_IN,
 					delay_ctr, load_eod_q, MULT_EVT_ENABLE_IN)
 begin
@@ -451,7 +451,7 @@ begin
 end process loadMachine;
 
 -- gk 04.12.10
-firstSubInMultiProc : process(CLK)
+firstSubInMultiProc : process(RESET, CLK)
 begin
 	if (RESET = '1') then
 		first_sub_in_multi <= '1';
@@ -467,7 +467,7 @@ begin
 end process;
 
 -- gk 04.12.10
-fromDivideStateProc : process(CLK)
+fromDivideStateProc : process(RESET, CLK)
 begin
 	if (RESET = '1') then
 		from_divide_state <= '0';
@@ -483,7 +483,7 @@ begin
 end process fromDivideStateProc;
 
 
-dividePositionProc : process(CLK)
+dividePositionProc : process(RESET, CLK)
 begin
 	if (RESET = '1') then
 		divide_position <= "00";
@@ -539,9 +539,7 @@ end process dividePositionProc;
 
 allIntCtrProc : process(CLK)
 begin
-	if (RESET = '1') then  -- gk 31.05.10
-		all_int_ctr <= 0;
-	elsif rising_edge(CLK) then
+	if rising_edge(CLK) then
 			case loadCurrentState is
 	
 				when LIDLE => all_int_ctr <= 0;
@@ -589,8 +587,7 @@ begin
 	end if;
 end process allIntCtrProc;
 
-dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, 
-					 sub_size_loaded, all_int_ctr, RESET, size_left, load_eod_q)
+dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, all_int_ctr, load_eod_q)
 begin
 	if (loadCurrentState = LOAD_DATA) then
 -- 		if (bytes_loaded = max_frame_size - x"1") then
@@ -625,7 +622,7 @@ begin
 	end if;
 end process dfRdEnProc;
 
-shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)
+shfRdEnProc : process(loadCurrentState, all_int_ctr)
 begin
 	if (loadCurrentState = LOAD_SUB) then
 		shf_rd_en <= '1';
@@ -639,7 +636,7 @@ begin
 end process shfRdEnProc;
 
 
-fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)
+fcWrEnProc : process(loadCurrentState, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)
 begin
 	if (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
 		fc_wr_en <= '1';
@@ -794,9 +791,7 @@ end process actualPacketProc;
 
 actualQueueSizeProc : process(CLK)
 begin
-	if RESET = '1' then
-		actual_queue_size <= (others => '0');
-	elsif rising_edge(CLK) then
+	if rising_edge(CLK) then
 		if (loadCurrentState = CLEANUP) then
 			actual_queue_size <= (others => '0');
 		elsif (loadCurrentState = LIDLE) then
@@ -810,9 +805,7 @@ end process actualQueueSizeProc;
 -- amount of bytes left to send in current packet
 sizeLeftProc : process(CLK)
 begin
-	if (RESET = '1') then 
-		size_left <= (others => '0');
-	elsif rising_edge(CLK) then
+	if rising_edge(CLK) then
 		if (loadCurrentState = CLEANUP) then
 			size_left <= (others => '0');
 		elsif (loadCurrentState = LIDLE) then
@@ -827,7 +820,7 @@ end process sizeLeftProc;
 
 -- HOT FIX: don't rely on CTS information, count the packets on your own.
 -- In this case, we increment the fragmented packet ID with EOD from ipu2gbe.
-THE_FC_IDENT_COUNTER_PROC: process(CLK)
+THE_FC_IDENT_COUNTER_PROC: process(RESET, CLK)
 begin
 	if (RESET = '1') then
 		fc_ident <= (others => '0');
@@ -966,7 +959,7 @@ begin
 	end case;
 end process shfDataProc;
 
-saveSubMachineProc : process(CLK)
+saveSubMachineProc : process(RESET, CLK)
 begin
 	if RESET = '1' then
 		saveSubCurrentState <= SIDLE;
diff --git a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
index a5b71b0..a6122ba 100644
--- a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
@@ -18,6 +18,10 @@ use work.trb_net_gbe_protocols.all;
 
 
 entity trb_net16_gbe_protocol_selector is
+	generic(
+		RX_PATH_ENABLE : integer range 0 to 1 := 1;
+		DO_SIMULATION  : integer range 0 to 1 := 0
+	);
 port (
 	CLK			: in	std_logic;  -- system clock
 	RESET			: in	std_logic;
@@ -99,16 +103,21 @@ port (
 	SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
 	SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
 	
-	CFG_GBE_ENABLE_IN            : in std_logic;                      
-	CFG_IPU_ENABLE_IN            : in std_logic;                      
-	CFG_MULT_ENABLE_IN           : in std_logic;                      
-	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);  
-	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);  
-	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);  
-	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);  
-	CFG_READOUT_CTR_VALID_IN     : in std_logic;           
-	CFG_ADDITIONAL_HDR_IN        : in std_logic;
-	CFG_INSERT_TTYPE_IN          : in std_logic;            
+	CFG_GBE_ENABLE_IN            : in std_logic;                    
+	CFG_IPU_ENABLE_IN            : in std_logic;                    
+	CFG_MULT_ENABLE_IN           : in std_logic;                    
+	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);
+	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);
+	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);
+	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
+	CFG_READOUT_CTR_VALID_IN     : in std_logic;
+	CFG_INSERT_TTYPE_IN          : in std_logic;
+	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
+	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
+	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
+	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
+	  
+	CFG_ADDITIONAL_HDR_IN        : in std_logic;   
 	
 	-- input for statistics from outside	
 	STAT_DATA_IN             : in std_logic_vector(31 downto 0);
@@ -120,6 +129,8 @@ port (
 	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_IN_OUT    : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_OUT_OUT   : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_GEN_DBG_OUT    : out	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 	DATA_HIST_OUT : out hist_array;
@@ -396,6 +407,10 @@ port map (
 );
 
 TrbNetData : trb_net16_gbe_response_constructor_TrbNetData
+generic map(
+		RX_PATH_ENABLE => RX_PATH_ENABLE,
+		DO_SIMULATION  => DO_SIMULATION
+		)
 port map (
 	CLK							=> CLK,
 	RESET						=> RESET,
@@ -437,8 +452,6 @@ port map (
 	DEBUG_OUT				=> MONITOR_SELECT_GEN_DBG_OUT(4 * 64 - 1 downto 3 * 64),
 -- END OF INTERFACE
 
-	TRANSMITTER_BUSY_IN         => '0',
-
 	-- CTS interface
 	CTS_NUMBER_IN				=> CTS_NUMBER_IN,
 	CTS_CODE_IN					=> CTS_CODE_IN,
@@ -475,11 +488,17 @@ port map (
 	CFG_READOUT_CTR_IN          => CFG_READOUT_CTR_IN,      
 	CFG_READOUT_CTR_VALID_IN    => CFG_READOUT_CTR_VALID_IN,
 	CFG_INSERT_TTYPE_IN         => CFG_INSERT_TTYPE_IN,
+	CFG_MAX_SUB_IN              => CFG_MAX_SUB_IN, 
+	CFG_MAX_QUEUE_IN            => CFG_MAX_QUEUE_IN,
+	CFG_MAX_SUBS_IN_QUEUE_IN    => CFG_MAX_SUBS_IN_QUEUE_IN,
+	CFG_MAX_SINGLE_SUB_IN       => CFG_MAX_SINGLE_SUB_IN,
 
 	MONITOR_SELECT_REC_OUT	      => MONITOR_SELECT_REC_OUT(4 * 32 - 1 downto 3 * 32),
 	MONITOR_SELECT_REC_BYTES_OUT  => MONITOR_SELECT_REC_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
 	MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT(4 * 32 - 1 downto 3 * 32),
 	MONITOR_SELECT_SENT_OUT	      => MONITOR_SELECT_SENT_OUT(4 * 32 - 1 downto 3 * 32),
+	MONITOR_SELECT_DROP_OUT_OUT   => MONITOR_SELECT_DROP_OUT_OUT(4 * 32 - 1 downto 3 * 32),
+	MONITOR_SELECT_DROP_IN_OUT    => open,
 	
 	DATA_HIST_OUT => DATA_HIST_OUT
 );
diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
index 3fec48d..e9dcbdf 100644
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd
@@ -12,6 +12,10 @@ use work.trb_net_gbe_components.all;
 use work.trb_net_gbe_protocols.all;
 
 entity trb_net16_gbe_response_constructor_TrbNetData is
+generic (
+	RX_PATH_ENABLE : integer range 0 to 1 := 1;
+	DO_SIMULATION  : integer range 0 to 1 := 0
+	);
 port (
 	CLK			: in	std_logic;  -- system clock
 	RESET			: in	std_logic;
@@ -51,8 +55,6 @@ port (
 	DEBUG_OUT		  : out std_logic_vector(63 downto 0);
 -- END OF INTERFACE
 
-	TRANSMITTER_BUSY_IN         : in    std_logic;
-
 	-- CTS interface
 	CTS_NUMBER_IN				: in	std_logic_vector (15 downto 0);
 	CTS_CODE_IN					: in	std_logic_vector (7  downto 0);
@@ -89,11 +91,17 @@ port (
 	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
 	CFG_READOUT_CTR_VALID_IN     : in std_logic;
 	CFG_INSERT_TTYPE_IN          : in std_logic;
+	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
+	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
+	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
+	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
 
 	MONITOR_SELECT_REC_OUT	      : out	std_logic_vector(31 downto 0);
 	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(31 downto 0);
 	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(31 downto 0);
 	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(31 downto 0);
+	MONITOR_SELECT_DROP_IN_OUT    : out std_logic_vector(31 downto 0);
+	MONITOR_SELECT_DROP_OUT_OUT   : out std_logic_vector(31 downto 0);
 	
 	DATA_HIST_OUT : out hist_array
 );
@@ -120,15 +128,12 @@ signal ic_src_udp				: std_logic_vector(15 downto 0);
 
 signal pc_wr_en					: std_logic;
 signal pc_data					: std_logic_vector(7 downto 0);
-signal pc_eod					: std_logic;
+signal pc_eoq					: std_logic;
 signal pc_sos					: std_logic;
 signal pc_ready					: std_logic;
-signal pc_padding				: std_logic;
-signal pc_event_id				: std_logic_vector(31 downto 0);
 signal pc_sub_size				: std_logic_vector(31 downto 0);
 signal pc_trig_nr				: std_logic_vector(31 downto 0);
 signal pc_eos                   : std_logic;
-signal pc_transmit_on           : std_logic;
 
 signal tc_rd_en					: std_logic;
 signal tc_data					: std_logic_vector(8 downto 0);
@@ -151,6 +156,7 @@ signal constr_dbg : std_logic_vector(63 downto 0);
 signal hist_inst : hist_array;
 signal tc_sod_flag : std_logic;
 signal reset_all_hist : std_logic_vector(31 downto 0);
+signal ipu_monitor : std_logic_vector(223 downto 0);
 
 begin
 
@@ -230,50 +236,45 @@ port map(
 	CONFIG_DONE_IN			 => ip_cfg_done,
 	DATA_GBE_ENABLE_IN		 => CFG_GBE_ENABLE_IN,
 	DATA_IPU_ENABLE_IN		 => CFG_IPU_ENABLE_IN,
-	MULT_EVT_ENABLE_IN		 => '0', --CFG_MULT_ENABLE_IN,
-	MAX_MESSAGE_SIZE_IN		 => x"0000_0fd0",
-	MIN_MESSAGE_SIZE_IN		 => x"0000_0007",
-	READOUT_CTR_IN			 => CFG_READOUT_CTR_IN, --x"00_0000",
-	READOUT_CTR_VALID_IN	 => CFG_READOUT_CTR_VALID_IN, --'0',
-	ALLOW_LARGE_IN			 => '0',
+	MULT_EVT_ENABLE_IN		 => CFG_MULT_ENABLE_IN,
+	MAX_SUBEVENT_SIZE_IN     => CFG_MAX_SUB_IN,
+	MAX_QUEUE_SIZE_IN        => CFG_MAX_QUEUE_IN,
+	MAX_SUBS_IN_QUEUE_IN     => CFG_MAX_SUBS_IN_QUEUE_IN,
+	MAX_SINGLE_SUB_SIZE_IN   => CFG_MAX_SINGLE_SUB_IN,
+	READOUT_CTR_IN			 => CFG_READOUT_CTR_IN,
+	READOUT_CTR_VALID_IN	 => CFG_READOUT_CTR_VALID_IN,
 	-- PacketConstructor interface
 	PC_WR_EN_OUT			 => pc_wr_en,
 	PC_DATA_OUT				 => pc_data,
 	PC_READY_IN				 => pc_ready,
 	PC_SOS_OUT				 => pc_sos,
 	PC_EOS_OUT				 => pc_eos,
-	PC_EOD_OUT				 => pc_eod,
+	PC_EOQ_OUT				 => pc_eoq,
 	PC_SUB_SIZE_OUT			 => pc_sub_size,
 	PC_TRIG_NR_OUT			 => pc_trig_nr,
 	PC_TRIGGER_TYPE_OUT      => pc_trig_type,
-	PC_PADDING_OUT			 => pc_padding,
-	MONITOR_OUT              => open,
+	MONITOR_OUT              => ipu_monitor,
 	DEBUG_OUT                => ipu_dbg
 );
 
---TODO: add missing values from setup
-PACKET_CONSTRUCTOR : trb_net16_gbe_event_constr --trb_net16_gbe_packet_constr
+MONITOR_SELECT_DROP_OUT_OUT <= ipu_monitor(31 downto 0);
+
+PACKET_CONSTRUCTOR : trb_net16_gbe_event_constr
 port map(
 	CLK						=> CLK,
 	RESET					=> RESET,
-	MULT_EVT_ENABLE_IN		=> '0', --CFG_MULT_ENABLE_IN
 	PC_WR_EN_IN				=> pc_wr_en,
 	PC_DATA_IN				=> pc_data,
 	PC_READY_OUT			=> pc_ready,
 	PC_START_OF_SUB_IN		=> pc_sos,
 	PC_END_OF_SUB_IN		=> pc_eos,
-	PC_END_OF_DATA_IN		=> pc_eod,
-	PC_TRANSMIT_ON_OUT		=> pc_transmit_on,
+	PC_END_OF_QUEUE_IN		=> pc_eoq,
 	PC_SUB_SIZE_IN			=> pc_sub_size,
-	PC_PADDING_IN			=> pc_padding,
-	PC_DECODING_IN			=> CFG_SUBEVENT_DEC_IN, --x"0002_0001", --pc_decoding,
-	PC_EVENT_ID_IN			=> CFG_SUBEVENT_ID_IN, --x"0000_8000", --pc_event_id,
+	PC_DECODING_IN			=> CFG_SUBEVENT_DEC_IN,
+	PC_EVENT_ID_IN			=> CFG_SUBEVENT_ID_IN,
 	PC_TRIG_NR_IN			=> pc_trig_nr,
 	PC_TRIGGER_TYPE_IN      => pc_trig_type,
-	PC_QUEUE_DEC_IN			=> CFG_QUEUE_DEC_IN, --x"0003_0062", --pc_queue_dec,
-	PC_MAX_FRAME_SIZE_IN    => (others => '0'), -- not used anymore
-	PC_MAX_QUEUE_SIZE_IN    => x"0000_0fd0",  -- not used for the moment
-	PC_DELAY_IN             => (others => '0'),
+	PC_QUEUE_DEC_IN			=> CFG_QUEUE_DEC_IN,
 	PC_INSERT_TTYPE_IN      => CFG_INSERT_TTYPE_IN,
 	TC_RD_EN_IN				=> tc_rd_en,
 	TC_DATA_OUT				=> tc_data,
@@ -284,16 +285,12 @@ port map(
 
 tc_rd_en <= '1' when PS_SELECTED_IN = '1' and TC_RD_EN_IN = '1' else '0'; 
 
-DISSECT_MACHINE_PROC : process(CLK)
+DISSECT_MACHINE_PROC : process(RESET, CLK)
 begin
 	if RESET = '1' then
 		dissect_current_state <= IDLE;
 	elsif rising_edge(CLK) then
---		if (RESET = '1') then
---			dissect_current_state <= IDLE;
---		else
-			dissect_current_state <= dissect_next_state;
---		end if;
+		dissect_current_state <= dissect_next_state;
 	end if;
 end process DISSECT_MACHINE_PROC;
 
@@ -332,16 +329,6 @@ PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1';
 PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) or (dissect_current_state = WAIT_FOR_LOAD) else '0';
 
 TC_DATA_OUT <= tc_data;
---TC_DATA_EOD_PROC : process (clk) is
---begin
---	if rising_edge(clk) then
---		if (dissect_current_state = LOAD and event_bytes = loaded_bytes - x"2") then
---			TC_DATA_OUT(8) <= '1';
---		else
---			TC_DATA_OUT(8) <= '0';
---		end if;
---	end if;
---end process TC_DATA_EOD_PROC;
 
 EVENT_BYTES_PROC : process (clk) is
 begin
@@ -369,11 +356,21 @@ end process LOADED_BYTES_PROC;
 
 TC_FRAME_SIZE_OUT 	  <= event_bytes;
 TC_FRAME_TYPE_OUT     <= x"0008";
-TC_DEST_MAC_OUT       <= ic_dest_mac;
-TC_DEST_IP_OUT        <= ic_dest_ip;
-TC_DEST_UDP_OUT       <= ic_dest_udp;
-TC_SRC_MAC_OUT        <= g_MY_MAC;
-TC_SRC_IP_OUT         <= g_MY_IP;
+TC_DEST_MAC_OUT       <= ic_dest_mac; --x"c4e870211b00"; --ic_dest_mac;
+TC_DEST_IP_OUT        <= ic_dest_ip; --x"0300a8c0"; --ic_dest_ip;
+TC_DEST_UDP_OUT       <= ic_dest_udp; --x"c35c"; --ic_dest_udp;
+
+
+rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
+	TC_SRC_MAC_OUT        <= g_MY_MAC;
+	TC_SRC_IP_OUT         <= g_MY_IP;
+end generate rx_enable_gen;
+
+rx_disable_gen : if (RX_PATH_ENABLE = 0) generate
+	TC_SRC_MAC_OUT        <= g_MY_MAC;
+	TC_SRC_IP_OUT         <= ic_src_ip;
+end generate rx_disable_gen;
+
 TC_SRC_UDP_OUT        <= ic_src_udp;
 TC_IP_PROTOCOL_OUT    <= x"11";
 TC_IDENT_OUT          <= x"4" & sent_packets(11 downto 0);
@@ -469,9 +466,11 @@ MONITOR_SELECT_SENT_BYTES_OUT <= mon_sent_bytes;
 MONITOR_SELECT_REC_BYTES_OUT  <= (others => '0');
 MONITOR_SELECT_REC_OUT        <= (others => '0');
 
-DEBUG_OUT(31 downto 0) <= ipu_dbg(31 downto 0);
+DEBUG_OUT(31 downto 0)  <= ipu_dbg(31 downto 0);
 DEBUG_OUT(63 downto 32) <= constr_dbg(31 downto 0);
 
+	
+
 end trb_net16_gbe_response_constructor_TrbNetData;
 
 
diff --git a/gbe2_ecp3/trb_net16_gbe_setup.vhd b/gbe2_ecp3/trb_net16_gbe_setup.vhd
index ac94e5c..71192af 100644
--- a/gbe2_ecp3/trb_net16_gbe_setup.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_setup.vhd
@@ -40,6 +40,11 @@ port(
 	GBE_INSERT_TTYPE_OUT      : out std_logic;
 	GBE_SOFT_RESET_OUT        : out std_logic;
 	
+	GBE_MAX_SUB_OUT           : out std_logic_vector(15 downto 0);
+	GBE_MAX_QUEUE_OUT         : out std_logic_vector(15 downto 0);
+	GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0);
+	GBE_MAX_SINGLE_SUB_OUT    : out std_logic_vector(15 downto 0);
+	
 	MONITOR_RX_BYTES_IN       : in std_logic_vector(31 downto 0);
 	MONITOR_RX_FRAMES_IN      : in std_logic_vector(31 downto 0);
 	MONITOR_TX_BYTES_IN       : in std_logic_vector(31 downto 0);
@@ -51,6 +56,8 @@ port(
 	MONITOR_SELECT_REC_BYTES_IN   : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_BYTES_IN  : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_IN	      : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_IN_IN	  : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_OUT_IN	  : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_GEN_DBG_IN     : in	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 	DATA_HIST_IN : in hist_array;
@@ -76,6 +83,7 @@ signal data_out          : std_logic_vector(31 downto 0);
 signal allow_rx          : std_logic;
 signal additional_hdr    : std_logic;
 signal insert_ttype      : std_logic;
+  signal max_sub, max_queue, max_subs_in_queue, max_single_sub : std_logic_vector(15 downto 0);
 
 begin
 
@@ -97,6 +105,10 @@ begin
 		GBE_ALLOW_RX_OUT          <= '1'; --allow_rx;
 		GBE_INSERT_TTYPE_OUT      <= insert_ttype;
 		GBE_ADDITIONAL_HDR_OUT    <= additional_hdr;
+		GBE_MAX_SUB_OUT           <= max_sub;
+		GBE_MAX_QUEUE_OUT         <= max_queue;
+		GBE_MAX_SUBS_IN_QUEUE_OUT <= max_subs_in_queue;
+		GBE_MAX_SINGLE_SUB_OUT    <= max_single_sub;
 	end if;
 end process OUT_PROC;
 
@@ -131,6 +143,10 @@ begin
 			insert_ttype      <= '0';
 			additional_hdr    <= '1';	
 			GBE_SOFT_RESET_OUT <= '0';
+			max_sub           <= x"e998";  --  59800  
+			max_queue         <= x"ea60";  -- 60000   
+			max_subs_in_queue <= x"00c8";  -- 200     
+			max_single_sub    <= x"7d00";  -- 32000   
 
 		elsif (BUS_WRITE_EN_IN = '1') then
 		
@@ -183,6 +199,19 @@ begin
 					
 				when x"0b" =>
 					insert_ttype     <= BUS_DATA_IN(0);
+					
+				when x"0c" =>
+					max_sub          <= BUS_DATA_IN(15 downto 0);
+					
+				when x"0d" =>
+					max_queue        <= BUS_DATA_IN(15 downto 0);
+					
+				when x"0e" =>
+					max_subs_in_queue <= BUS_DATA_IN(15 downto 0);
+					
+				when x"0f" =>
+					max_single_sub   <= BUS_DATA_IN(15 downto 0);
+					
 
 				when x"ff" =>
 					if (BUS_DATA_IN = x"ffff_ffff") then
@@ -207,6 +236,10 @@ begin
 					allow_rx           <= allow_rx;
 					additional_hdr     <= additional_hdr;
 					insert_ttype       <= insert_ttype;
+					max_sub            <= max_sub;          
+					max_queue          <= max_queue;        
+					max_subs_in_queue  <= max_subs_in_queue;
+					max_single_sub     <= max_single_sub;			
 			end case;
 		else
 			reset_values      <= '0';
@@ -217,7 +250,7 @@ begin
 end process WRITE_PROC;
 
 READ_PROC : process(CLK)
-	variable address : integer;
+	variable address : integer range 0 to 255;
 begin
 	if rising_edge(CLK) then
 		if (RESET = '1') then
@@ -274,6 +307,22 @@ begin
 					data_out(0) <= insert_ttype;
 					data_out(31 downto 1) <= (others => '0');
 					
+				when 12 =>
+					data_out(15 downto 0) <= max_sub;
+					data_out(31 downto 16) <= (others => '0');
+					
+				when 13 =>
+					data_out(15 downto 0) <= max_queue;
+					data_out(31 downto 16) <= (others => '0');
+					
+				when 14 =>
+					data_out(15 downto 0) <= max_subs_in_queue;
+					data_out(31 downto 16) <= (others => '0');
+					
+				when 15 =>
+					data_out(15 downto 0) <= max_single_sub;
+					data_out(31 downto 16) <= (others => '0');
+					
 				-- Histogram of sctrl data sizes
 				when 96 to 127 =>
 					data_out <= SCTRL_HIST_IN(address - 96);
@@ -314,7 +363,11 @@ begin
 					data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 - 32 downto 2 * 64);
 				when 165 =>
 					data_out <= MONITOR_SELECT_GEN_DBG_IN(3 * 64 - 1 downto 2 * 64 + 32);
-						
+				when 166 =>
+					data_out <= MONITOR_SELECT_DROP_IN_IN(3 * 32 - 1 downto 2 * 32);
+				when 167 =>
+					data_out <= MONITOR_SELECT_DROP_OUT_IN(3 * 32 - 1 downto 2 * 32);
+							
 				-- TrbnetData
 				when 176 =>
 					data_out <= MONITOR_SELECT_REC_IN(4 * 32 - 1 downto 3 * 32);
@@ -328,6 +381,10 @@ begin
 					data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 - 32 downto 3 * 64);
 				when 181 =>
 					data_out <= MONITOR_SELECT_GEN_DBG_IN(4 * 64 - 1 downto 3 * 64 + 32);
+				when 182 =>
+					data_out <= MONITOR_SELECT_DROP_IN_IN(4 * 32 - 1 downto 3 * 32);
+				when 183 =>
+					data_out <= MONITOR_SELECT_DROP_OUT_IN(4 * 32 - 1 downto 3 * 32);
 				
 				-- for older network monitors	
 				when 243 =>
diff --git a/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd b/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd
index aca1526..d2a4963 100644
--- a/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd
@@ -84,11 +84,7 @@ begin
 	if RESET = '1' then
 		transmit_current_state <= IDLE;
 	elsif rising_edge(CLK) then
---		if (RESET = '1') then
---			transmit_current_state <= IDLE;
---		else
-			transmit_current_state <= transmit_next_state;
---		end if;
+		transmit_current_state <= transmit_next_state;
 	end if;
 end process TRANSMIT_MACHINE_PROC;
 
@@ -98,7 +94,7 @@ begin
 	
 		when IDLE =>
 			if (TC_DATAREADY_IN = '1') then
-				transmit_next_state <= PREPARE_HEADERS; --WAIT_FOR_H;
+				transmit_next_state <= PREPARE_HEADERS;
 			else
 				transmit_next_state <= IDLE;
 			end if;
@@ -145,7 +141,7 @@ begin
 			end if;
 		
 		when DIVIDE =>
-			transmit_next_state <= PREPARE_HEADERS; --WAIT_FOR_H;
+			transmit_next_state <= PREPARE_HEADERS;
 			
 		when CLEANUP =>
 			transmit_next_state <= IDLE;
diff --git a/gbe2_ecp3/trb_net_gbe_components.vhd b/gbe2_ecp3/trb_net_gbe_components.vhd
index 0f5c968..3b600fd 100644
--- a/gbe2_ecp3/trb_net_gbe_components.vhd
+++ b/gbe2_ecp3/trb_net_gbe_components.vhd
@@ -10,6 +10,7 @@ use work.trb_net_gbe_protocols.all;
 package trb_net_gbe_components is
 
 
+
 component trb_net16_gbe_transmit_control2 is
 port (
 	CLK			         : in	std_logic;
@@ -61,26 +62,20 @@ component trb_net16_gbe_event_constr is
 port(
 	RESET                   : in    std_logic;
 	CLK                     : in    std_logic;
-	MULT_EVT_ENABLE_IN      : in    std_logic;  -- gk 06.10.10
 	-- ports for user logic
 	PC_WR_EN_IN             : in    std_logic; -- write into queueConstr from userLogic
 	PC_DATA_IN              : in    std_logic_vector(7 downto 0);
 	PC_READY_OUT            : out   std_logic;
 	PC_START_OF_SUB_IN      : in    std_logic;
 	PC_END_OF_SUB_IN        : in    std_logic;  -- gk 07.10.10
-	PC_END_OF_DATA_IN       : in    std_logic;
-	PC_TRANSMIT_ON_OUT	: out	std_logic;
+	PC_END_OF_QUEUE_IN      : in    std_logic;
 	-- queue and subevent layer headers
 	PC_SUB_SIZE_IN          : in    std_logic_vector(31 downto 0); -- store and swap
-	PC_PADDING_IN           : in    std_logic;  -- gk 29.03.10
 	PC_DECODING_IN          : in    std_logic_vector(31 downto 0); -- swap
 	PC_EVENT_ID_IN          : in    std_logic_vector(31 downto 0); -- swap
 	PC_TRIG_NR_IN           : in    std_logic_vector(31 downto 0); -- store and swap!
 	PC_TRIGGER_TYPE_IN      : in	std_logic_vector(3 downto 0);
 	PC_QUEUE_DEC_IN         : in    std_logic_vector(31 downto 0); -- swap
-	PC_MAX_FRAME_SIZE_IN    : in	std_logic_vector(15 downto 0); -- DO NOT SWAP
-	PC_MAX_QUEUE_SIZE_IN    : in    std_logic_vector(31 downto 0);
-	PC_DELAY_IN             : in	std_logic_vector(31 downto 0);  -- gk 28.04.10
 	PC_INSERT_TTYPE_IN      : in    std_logic;
 	-- FrameConstructor ports
 	TC_RD_EN_IN             : in    std_logic;
@@ -121,31 +116,71 @@ component trb_net16_gbe_ipu_interface is
 	DATA_GBE_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to GbE
 	DATA_IPU_ENABLE_IN			: in	std_logic; -- IPU data is forwarded to CTS / TRBnet
 	MULT_EVT_ENABLE_IN			: in    std_logic;
-	MAX_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- the maximum size of one HadesQueue  -- gk 08.04.10
-	MIN_MESSAGE_SIZE_IN			: in	std_logic_vector(31 downto 0); -- gk 20.07.10
+	MAX_SUBEVENT_SIZE_IN		: in	std_logic_vector(15 downto 0);
+	MAX_QUEUE_SIZE_IN           : in    std_logic_vector(15 downto 0);
+	MAX_SUBS_IN_QUEUE_IN        : in    std_logic_vector(15 downto 0);
+	MAX_SINGLE_SUB_SIZE_IN      : in    std_logic_vector(15 downto 0);
 	READOUT_CTR_IN				: in	std_logic_vector(23 downto 0); -- gk 26.04.10
-	READOUT_CTR_VALID_IN			: in	std_logic; -- gk 26.04.10
+	READOUT_CTR_VALID_IN		: in	std_logic; -- gk 26.04.10
 	-- PacketConstructor interface
-	ALLOW_LARGE_IN				: in	std_logic;  -- gk 21.07.10
 	PC_WR_EN_OUT                : out   std_logic;
 	PC_DATA_OUT                 : out   std_logic_vector (7 downto 0);
 	PC_READY_IN                 : in    std_logic;
 	PC_SOS_OUT                  : out   std_logic;
-	PC_EOS_OUT                  : out   std_logic; -- gk 07.10.10
-	PC_EOD_OUT                  : out   std_logic;
+	PC_EOS_OUT                  : out   std_logic;
+	PC_EOQ_OUT                  : out   std_logic;
 	PC_SUB_SIZE_OUT             : out   std_logic_vector(31 downto 0);
 	PC_TRIG_NR_OUT              : out   std_logic_vector(31 downto 0);
-	PC_PADDING_OUT              : out   std_logic;
 	PC_TRIGGER_TYPE_OUT         : out	std_logic_vector(3 downto 0);
 	MONITOR_OUT                 : out   std_logic_vector(223 downto 0);
 	DEBUG_OUT                   : out   std_logic_vector(383 downto 0)
 	);
 end component;
 
+component gbe_ipu_dummy is
+	generic (
+		DO_SIMULATION : integer range 0 to 1 := 0;
+		FIXED_SIZE_MODE : integer range 0 to 1 := 1;
+		FIXED_SIZE : integer range 0 to 65535 := 10;
+		FIXED_DELAY_MODE : integer range 0 to 1 := 1;
+		FIXED_DELAY : integer range 0 to 65535 := 4096
+		);
+	port (
+		clk : in std_logic;
+		rst : in std_logic;
+		GBE_READY_IN : in std_logic;
+		
+		CTS_NUMBER_OUT				: out	std_logic_vector (15 downto 0);
+		CTS_CODE_OUT					: out	std_logic_vector (7  downto 0);
+		CTS_INFORMATION_OUT			: out	std_logic_vector (7  downto 0);
+		CTS_READOUT_TYPE_OUT			: out	std_logic_vector (3  downto 0);
+		CTS_START_READOUT_OUT		: out	std_logic;
+		CTS_DATA_IN				: in	std_logic_vector (31 downto 0);
+		CTS_DATAREADY_IN			: in	std_logic;
+		CTS_READOUT_FINISHED_IN	: in	std_logic;
+		CTS_READ_OUT					: out	std_logic;
+		CTS_LENGTH_IN				: in	std_logic_vector (15 downto 0);
+		CTS_ERROR_PATTERN_IN		: in	std_logic_vector (31 downto 0);
+		-- Data payload interface
+		FEE_DATA_OUT					: out	std_logic_vector (15 downto 0);
+		FEE_DATAREADY_OUT			: out	std_logic;
+		FEE_READ_IN				: in	std_logic;
+		FEE_STATUS_BITS_OUT			: out	std_logic_vector (31 downto 0);
+		FEE_BUSY_OUT					: out	std_logic
+	);
+end component;
+
 component trb_net16_gbe_buf is
 generic( 
 	DO_SIMULATION		: integer range 0 to 1 := 1;
-	USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1
+	RX_PATH_ENABLE      : integer range 0 to 1 := 1;
+	USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1 := 0;
+	USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1;
+		
+		FIXED_SIZE_MODE : integer range 0 to 1 := 1;
+		FIXED_SIZE : integer range 0 to 65535 := 10;
+		FIXED_DELAY_MODE : integer range 0 to 1 := 1;
+		FIXED_DELAY : integer range 0 to 65535 := 4096
 );
 port(
 	CLK							: in	std_logic;
@@ -276,6 +311,10 @@ port (
 end component;
 
 component trb_net16_gbe_protocol_selector is
+generic(
+		RX_PATH_ENABLE : integer range 0 to 1 := 1;
+		DO_SIMULATION  : integer range 0 to 1 := 0
+	);
 port (
 	CLK			: in	std_logic;  -- system clock
 	RESET			: in	std_logic;
@@ -356,16 +395,21 @@ port (
 	SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
 	SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
 	
-	CFG_GBE_ENABLE_IN            : in std_logic;                      
-	CFG_IPU_ENABLE_IN            : in std_logic;                      
-	CFG_MULT_ENABLE_IN           : in std_logic;                      
-	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);  
-	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);  
-	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);  
-	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);  
-	CFG_READOUT_CTR_VALID_IN     : in std_logic;  
-	CFG_ADDITIONAL_HDR_IN        : in std_logic;
+	CFG_GBE_ENABLE_IN            : in std_logic;                    
+	CFG_IPU_ENABLE_IN            : in std_logic;                    
+	CFG_MULT_ENABLE_IN           : in std_logic;                    
+	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);
+	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);
+	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);
+	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
+	CFG_READOUT_CTR_VALID_IN     : in std_logic;
 	CFG_INSERT_TTYPE_IN          : in std_logic;
+	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
+	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
+	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
+	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
+	  
+	CFG_ADDITIONAL_HDR_IN        : in std_logic;  
 	
 	-- input for statistics from outside	
 	STAT_DATA_IN             : in std_logic_vector(31 downto 0);
@@ -377,6 +421,8 @@ port (
 	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_IN_OUT    : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_OUT_OUT   : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_GEN_DBG_OUT    : out	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 	DATA_HIST_OUT : out hist_array;
@@ -411,6 +457,10 @@ port (
 end component;
 
 component trb_net16_gbe_main_control is
+generic(
+		RX_PATH_ENABLE : integer range 0 to 1 := 1;
+		DO_SIMULATION  : integer range 0 to 1 := 0
+	);
 port (
 	CLK			: in	std_logic;  -- system clock
 	CLK_125			: in	std_logic;
@@ -497,16 +547,21 @@ port (
 	SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
 	SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
 	
-	CFG_GBE_ENABLE_IN            : in std_logic;
-	CFG_IPU_ENABLE_IN            : in std_logic;
-	CFG_MULT_ENABLE_IN           : in std_logic;
-	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0); 
-	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0); 
-	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0); 
-	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0); 
-	CFG_READOUT_CTR_VALID_IN     : in std_logic; 
-	CFG_ADDITIONAL_HDR_IN        : in std_logic;
+	CFG_GBE_ENABLE_IN            : in std_logic;                    
+	CFG_IPU_ENABLE_IN            : in std_logic;                    
+	CFG_MULT_ENABLE_IN           : in std_logic;                    
+	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);
+	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);
+	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);
+	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
+	CFG_READOUT_CTR_VALID_IN     : in std_logic;
 	CFG_INSERT_TTYPE_IN          : in std_logic;
+	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
+	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
+	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
+	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
+	  
+	CFG_ADDITIONAL_HDR_IN        : in std_logic;   
 	
 	MAKE_RESET_OUT           : out std_logic;
 	
@@ -526,6 +581,8 @@ port (
 	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_IN_OUT    : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_OUT_OUT   : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_GEN_DBG_OUT    : out	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 	DATA_HIST_OUT : out hist_array;
@@ -927,6 +984,11 @@ port(
 	GBE_INSERT_TTYPE_OUT      : out std_logic;
 	GBE_SOFT_RESET_OUT        : out std_logic;
 	
+	GBE_MAX_SUB_OUT           : out std_logic_vector(15 downto 0);
+	GBE_MAX_QUEUE_OUT         : out std_logic_vector(15 downto 0);
+	GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0);
+	GBE_MAX_SINGLE_SUB_OUT    : out std_logic_vector(15 downto 0);
+	
 	MONITOR_RX_BYTES_IN       : in std_logic_vector(31 downto 0);
 	MONITOR_RX_FRAMES_IN      : in std_logic_vector(31 downto 0);
 	MONITOR_TX_BYTES_IN       : in std_logic_vector(31 downto 0);
@@ -938,6 +1000,8 @@ port(
 	MONITOR_SELECT_REC_BYTES_IN   : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_BYTES_IN  : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_SENT_IN	      : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_IN_IN	  : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
+	MONITOR_SELECT_DROP_OUT_IN	  : in	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	MONITOR_SELECT_GEN_DBG_IN     : in	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
 	
 	DATA_HIST_IN : in hist_array;
diff --git a/gbe2_ecp3/trb_net_gbe_protocols.vhd b/gbe2_ecp3/trb_net_gbe_protocols.vhd
index fe87182..8d0dc4c 100644
--- a/gbe2_ecp3/trb_net_gbe_protocols.vhd
+++ b/gbe2_ecp3/trb_net_gbe_protocols.vhd
@@ -528,6 +528,10 @@ port (
 end component;
 
 component trb_net16_gbe_response_constructor_TrbNetData is
+generic (
+		RX_PATH_ENABLE : integer range 0 to 1 := 1;
+		DO_SIMULATION  : integer range 0 to 1 := 0
+		);
 port (
 	CLK			: in	std_logic;  -- system clock
 	RESET			: in	std_logic;
@@ -568,8 +572,6 @@ port (
 	
 -- END OF INTERFACE
 
-	TRANSMITTER_BUSY_IN         : in    std_logic;
-
 	-- CTS interface
 	CTS_NUMBER_IN				: in	std_logic_vector (15 downto 0);
 	CTS_CODE_IN					: in	std_logic_vector (7  downto 0);
@@ -604,15 +606,21 @@ port (
 	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);
 	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);
 	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
-	CFG_READOUT_CTR_VALID_IN     : in std_logic;  
+	CFG_READOUT_CTR_VALID_IN     : in std_logic;
 	CFG_INSERT_TTYPE_IN          : in std_logic;
+	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
+	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
+	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
+	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
 
 	MONITOR_SELECT_REC_OUT	      : out	std_logic_vector(31 downto 0);
 	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(31 downto 0);
 	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(31 downto 0);
 	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(31 downto 0);
+	MONITOR_SELECT_DROP_IN_OUT    : out std_logic_vector(31 downto 0);
+	MONITOR_SELECT_DROP_OUT_OUT   : out std_logic_vector(31 downto 0);
 	
-	DATA_HIST_OUT : out hist_array 
+	DATA_HIST_OUT : out hist_array
 );
 end component;
 
-- 
2.43.0