From 698fce930a1863921efd03264d29a4231823212c Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 20 Jan 2012 13:48:34 +0000 Subject: [PATCH] *** empty log message *** --- compile_frankfurt.pl | 8 +- constraints.lpf | 2 +- design2/data_handler.vhd | 9 +- design2/mdc_control.vhd | 219 +++++++++++++++++++++++++---- design2/mdc_data_statistics.vhd | 114 +++++++++++++++ design2/mdc_oepb_pack.vhd | 37 ++++- design2/tdc_readout.vhd | 2 +- design2/trigger_handler.vhd | 3 + mdc_oepb.p2t | 2 +- mdc_oepb.prj | 2 +- mdc_oepb.vhd | 240 +++++++++++++++++++------------- 11 files changed, 503 insertions(+), 135 deletions(-) create mode 100644 design2/mdc_data_statistics.vhd diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index 47d0638..1dc1a9b 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -13,9 +13,9 @@ use warnings; use strict; #my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/'; -my $lattice_path = '/d/sugar/lattice/diamond/1.1'; +my $lattice_path = '/d/jspc29/lattice/diamond/1.4'; #my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; -my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; +my $synplify_path = '/d/jspc29/lattice/synplify/D-2010.03/'; #my $synplify_path = '/d/sugar/lattice/synplify/fpga_e201009sp2/'; use FileHandle; @@ -116,8 +116,8 @@ $c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME. execute($c); # # IOR IO Timing Report -# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -# execute($c); + $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); # TWR Timing Report #$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|; diff --git a/constraints.lpf b/constraints.lpf index b7f6217..975eb7a 100644 --- a/constraints.lpf +++ b/constraints.lpf @@ -19,5 +19,5 @@ GSR_NET NET "gsr_n"; GSR_NET NET "pll_locked"; # MULTICYCLE FROM CELL reset 2.0 x; - + MULTICYCLE FROM CELL THE_MED_INTERFACE/THE_SFP_LSM/reset_me 20 ns; SYSCONFIG MCCLK_FREQ = 20; \ No newline at end of file diff --git a/design2/data_handler.vhd b/design2/data_handler.vhd index 7000016..dec5263 100644 --- a/design2/data_handler.vhd +++ b/design2/data_handler.vhd @@ -9,7 +9,7 @@ use work.trb_net_components.all; entity data_handler is generic( - NUMBER_OF_STAT_WORDS : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(21,5)) + NUMBER_OF_STAT_WORDS : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(22,5)) ); port( CLK : in std_logic; @@ -114,6 +114,7 @@ architecture arch of data_handler is signal statram_din : std_logic_vector(23 downto 0); signal statram_write : std_logic; + signal timer : unsigned(31 downto 0); begin @@ -124,8 +125,8 @@ begin --Status word type 0x01: Debug word word_debug(31 downto 29) <= "010"; word_debug(28 downto 24) <= "11111"; - word_debug(23 downto 16) <= (others => '0'); - word_debug(15 downto 0) <= LVL1_TRG_NUMBER_IN; +-- word_debug(23 downto 16) <= (others => '0'); + word_debug(23 downto 0) <= std_logic_vector(timer(27 downto 4)); --Status word type 0x00: Dummy Data word_dummy(31 downto 29) <= "010"; @@ -209,6 +210,7 @@ begin inc_discarded_hit1_ctr <= '0'; inc_single_hit0_ctr <= '0'; inc_single_hit1_ctr <= '0'; + timer <= timer + to_unsigned(1,1); case current_state is when IDLE => @@ -235,6 +237,7 @@ begin end if; when WRITE_DEBUG_WORD => + timer <= (others => '0'); data_i <= word_debug; data_write_buf := '1'; if SEND_DUMMY_DATA_IN = '1' then diff --git a/design2/mdc_control.vhd b/design2/mdc_control.vhd index 5601668..b66d283 100644 --- a/design2/mdc_control.vhd +++ b/design2/mdc_control.vhd @@ -62,17 +62,36 @@ entity mdc_control is STATISTIC_DATA_OUT : out std_logic_vector(31 downto 0); STATISTIC_READ_IN : in std_logic; STATISTIC_READY_OUT : out std_logic; + + STAT_RAM_ADDR_IN : in std_logic_vector(7 downto 0); + STAT_RAM_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_RAM_READ_IN : in std_logic; + STAT_RAM_WRITE_IN : in std_logic; + STAT_RAM_READY_OUT : out std_logic; RB_DATA_OUT : out std_logic_vector(31 downto 0); --Readback fifo RB_READ_ENABLE_IN : in std_logic; RB_READY_OUT : out std_logic; RB_EMPTY_OUT : out std_logic; + IO_ADDR_IN : in std_logic_vector(1 downto 0); + IO_DATA_RX : in std_logic_vector(31 downto 0); + IO_DATA_TX : out std_logic_vector(31 downto 0); + IO_READ_IN : in std_logic; + IO_WRITE_IN : in std_logic; + IO_WRITE_ACK_OUT : out std_logic; + IO_READY_OUT : out std_logic; + + JTAG_TDO : in std_logic; + JTAG_TDI : out std_logic; + JTAG_TCK : out std_logic; + JTAG_TMS : out std_logic; + COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0); COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0); STAT_REG_OUT : out std_logic_vector(63 downto 0); CTRL_REG_IN : in std_logic_vector(127 downto 0); - STAT_TRIGGER_IN : in std_logic_vector(63 downto 0); + STAT_TRIGGER_IN : in std_logic_vector(79 downto 0); TIMER_TICKS_IN : in std_logic_vector(1 downto 0); DEBUG_OUT : out std_logic_vector(31 downto 0) @@ -95,6 +114,7 @@ architecture arch of mdc_control is signal reg_timing_trigger : std_logic; signal trigger_begin_run : std_logic; signal reset_mbo_i : std_logic; + signal cms_enable_i : std_logic; signal reset_trigger_logic_i : std_logic; signal reset_mbo_logic_i : std_logic; @@ -137,6 +157,7 @@ architecture arch of mdc_control is signal ram_ready_out_del : std_logic; signal last_rb_read_enable_in : std_logic; signal readback_mem_write : std_logic; + signal readback_mem_write_temp : std_logic; signal readback_mem_full : std_logic; signal switch_polarity : std_logic; signal trigger_input_corr : std_logic; @@ -164,6 +185,7 @@ architecture arch of mdc_control is signal counter_retransmit_sent_i : unsigned(11 downto 0); signal counter_hits_i : unsigned(31 downto 0); + signal inc_reinit_counter : std_logic; signal inc_calib_counter : std_logic; signal inc_trigger_counter : std_logic; @@ -179,8 +201,29 @@ architecture arch of mdc_control is signal data_handler_stat_data_i: std_logic_vector(23 downto 0); signal trigger_handler_times_i : std_logic_vector(5*32-1 downto 0); signal force_reinit_i : std_logic; - - + signal buf_FEE_DATA_OUT : std_logic_vector(31 downto 0); + signal buf_FEE_DATA_WRITE_OUT : std_logic; + + signal buf_A_RDO : std_logic; + signal buf_A_GDE : std_logic; + signal buf_A_MOD : std_logic; + signal buf_A_RDM : std_logic; + signal buf_A_RES : std_logic; + signal buf_A_TOK : std_logic; + signal buf_A_WRM : std_logic; + signal shift_RDO : std_logic_vector(3 downto 0); + signal mbo_lines : std_logic_vector(31 downto 0); + + signal io_override : std_logic_vector(2 downto 0); + signal io_set_adbus : std_logic_vector(31 downto 0); + signal io_set_outputs : std_logic_vector(31 downto 0); + signal A_ADD_final : std_logic_vector(8 downto 0); + signal A_AOD_final : std_logic; + signal A_DST_final : std_logic; + signal reg_JTAG_TDO : std_logic; + signal doing_readout : std_logic; + signal readback_mode : std_logic; + begin ------------------------------------------------------------------------------- @@ -241,6 +284,7 @@ begin FINISHED_READOUT_OUT => finished_readout_i, FINISHED_CYCLE_OUT => finished_cycle_i, RESET_MBO_OUT => reset_mbo_i, + CMS_ENABLE_OUT => cms_enable_i, --FSM status FINISHED_BEGRUN_IN => finished_begrun_i, CAL1_LOADED_IN => cal1_loaded_i, @@ -289,8 +333,8 @@ begin DATA_BUS_IN => data_bus_i, DATA_VALID_IN => data_bus_valid_i, --Data Output to Endpoint - FEE_DATA_OUT => FEE_DATA_OUT, - FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, + FEE_DATA_OUT => buf_FEE_DATA_OUT, + FEE_DATA_WRITE_OUT => buf_FEE_DATA_WRITE_OUT, FEE_DATA_FINISHED_OUT => fee_data_finished_i, --Statistics INC_DISCARDED_HIT0_OUT => inc_discarded_hit0_ctr, @@ -306,6 +350,10 @@ begin DEBUG_REGISTER => debug_data_handler_i ); + FEE_DATA_OUT <= buf_FEE_DATA_OUT; + FEE_DATA_WRITE_OUT <= buf_FEE_DATA_WRITE_OUT; + + ------------------------------------------------------------------------------- -- TDC Readout ------------------------------------------------------------------------------- @@ -320,7 +368,7 @@ begin A_RESERV_IN => rsv_in_i, --Control START_READOUT_IN => start_readout_i, - TOKEN_IN => A_RDO, + TOKEN_IN => buf_A_RDO, FINISHED_IN => finished_cycle_i, FLAG_EVENT_COUNTER_IN => LVL1_INT_TRG_NUMBER_IN(3 downto 0), --Data @@ -341,13 +389,13 @@ begin A_ADD => add_out_i, A_AOD => aod_out_i, A_DST => dst_out_i, - A_RDM => A_RDM, - A_GDE => A_GDE, - A_RDO => A_RDO, - A_MOD => A_MOD, - A_RES => A_RES, - A_TOK => A_TOK, - A_WRM => A_WRM, + A_RDM => buf_A_RDM, + A_GDE => buf_A_GDE, + A_RDO => buf_A_RDO, + A_MOD => buf_A_MOD, + A_RES => buf_A_RES, + A_TOK => buf_A_TOK, + A_WRM => buf_A_WRM, OUTPUT_ENABLE => databus_output_enable, --FSM control START_CALIB_IN => start_calib_i, @@ -384,6 +432,24 @@ begin end if; end process; + + + +THE_DATA_STATISTICS : mdc_data_statistics + port map( + CLK => CLK, + DATA_IN => buf_FEE_DATA_OUT(31 downto 0), + UPDATE_IN => buf_FEE_DATA_WRITE_OUT, + TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + + RAM_DATA_OUT => STAT_RAM_DATA_OUT, + RAM_ADDR_IN => STAT_RAM_ADDR_IN, + RAM_READ_IN => STAT_RAM_READ_IN, + RAM_WRITE_IN => STAT_RAM_WRITE_IN, + RAM_READY_OUT => STAT_RAM_READY_OUT + ); + + ------------------------------------------------------------------------------- -- Debug Registers ------------------------------------------------------------------------------- @@ -419,7 +485,7 @@ begin if STATISTIC_READ_IN = '1' then tmp := to_integer(unsigned(STATISTIC_ADDR_IN)); case tmp is - when 0 => STATISTIC_DATA_OUT <= x"0000" & std_logic_vector(counter_reinit_i); + when 0 => STATISTIC_DATA_OUT <= x"00" & "00000" & cms_active_i & motherboard_type_i(1 downto 0) & LVL1_INT_TRG_NUMBER_IN; when 1 => STATISTIC_DATA_OUT <= x"0000" & std_logic_vector(counter_reinit_i); when 2 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_trigger_i); when 3 => STATISTIC_DATA_OUT <= x"0000" & std_logic_vector(counter_calib_i); @@ -441,6 +507,7 @@ begin when 18 => STATISTIC_DATA_OUT <= trigger_handler_times_i(95 downto 64); when 19 => STATISTIC_DATA_OUT <= trigger_handler_times_i(127 downto 96); when 20 => STATISTIC_DATA_OUT <= trigger_handler_times_i(159 downto 128); + when 21 => STATISTIC_DATA_OUT <= x"0000" & STAT_TRIGGER_IN(79 downto 64); when others => STATISTIC_DATA_OUT <= (others => '0'); end case; @@ -476,6 +543,7 @@ begin when 18 => data_handler_stat_data_i <= trigger_handler_times_i(87 downto 64); when 19 => data_handler_stat_data_i <= trigger_handler_times_i(119 downto 96); when 20 => data_handler_stat_data_i <= trigger_handler_times_i(151 downto 128); + when 21 => data_handler_stat_data_i <= x"00" & STAT_TRIGGER_IN(79 downto 64); when others => data_handler_stat_data_i <= (others => '0'); end case; @@ -492,7 +560,9 @@ counter_retransmit_sent_i <= (others => '0'); port map ( Data(7 downto 0) => add_in_i(8 downto 1), Data(8) => add_in_i(0), - Data(15 downto 9) => (others => '0'), + Data(13 downto 9) => (others => '0'), + Data(14) => io_override(2), + Data(15) => databus_output_enable, Data(16) => dst_in_i, Data(17) => aod_in_i, Clock => CLK, @@ -510,14 +580,22 @@ counter_retransmit_sent_i <= (others => '0'); CLOCK => CLK, en_clk => '1', signal_in => dst_in_i, - PULSE => readback_mem_write + PULSE => readback_mem_write_temp ); - + readback_mem_write <= readback_mem_write_temp and readback_mode; + + + -- RB_EMPTY_OUT <= '0'; process(CLK) begin if rising_edge(CLK) then + if start_readback_i = '1' then + readback_mode <= '1'; + elsif finished_begrun_i = '1' or RESET = '1' then + readback_mode <= '0'; + end if; last_rb_read_enable_in <= RB_READ_ENABLE_IN; RB_READY_OUT <= last_rb_read_enable_in; end if; @@ -546,7 +624,7 @@ counter_retransmit_sent_i <= (others => '0'); data_dummy_i <= COMMON_CTRL_REG_IN(85); switch_polarity <= COMMON_CTRL_REG_IN(93); data_debug_i <= COMMON_CTRL_REG_IN(94); - cms_active_i <= COMMON_CTRL_REG_IN(95); + cms_active_i <= COMMON_CTRL_REG_IN(95) and cms_enable_i; end if; end process; @@ -612,8 +690,8 @@ counter_retransmit_sent_i <= (others => '0'); if inc_single_hit1_ctr = '1' then counter_single_hit1_i <= counter_single_hit1_i + to_unsigned(1,1); end if; - if inc_hit_counter = '1' then - counter_hits_i <= counter_hits_i + to_unsigned(1,1); + if inc_hit_counter = '1' and LVL1_TRG_TYPE_IN = x"1" then + counter_hits_i <= counter_hits_i + to_unsigned(2,2); end if; end if; end if; @@ -621,6 +699,9 @@ counter_retransmit_sent_i <= (others => '0'); + + + ------------------------------------------------------------------------------- -- I/O ------------------------------------------------------------------------------- @@ -629,10 +710,10 @@ counter_retransmit_sent_i <= (others => '0'); PROC_OUTPUT_SYNC : process(CLK) begin if rising_edge(CLK) then - if databus_output_enable = '1' then - A_AOD <= aod_out_i; - A_DST <= dst_out_i; - A_ADD <= add_out_i; + if databus_output_enable = '1' or (io_override(2) = '1' and io_set_adbus(20) = '1') then + A_AOD <= A_AOD_final; --aod_out_i; -- + A_DST <= A_DST_final; --dst_out_i; -- + A_ADD <= A_ADD_final; --add_out_i; -- else A_AOD <= 'Z'; A_DST <= 'Z'; @@ -641,6 +722,10 @@ counter_retransmit_sent_i <= (others => '0'); end if; end process; + A_ADD_final <= io_set_adbus(8 downto 0) when io_override(2) = '1' else add_out_i; + A_AOD_final <= io_set_adbus(12) when io_override(2) = '1' else aod_out_i; + A_DST_final <= io_set_adbus(16) when io_override(2) = '1' else dst_out_i; + PROC_INPUT_SYNC : process(CLK) begin @@ -651,9 +736,35 @@ counter_retransmit_sent_i <= (others => '0'); rsv_in_i <= A_RESERVE; end if; end process; - + + PROC_RDO_SYNC : process + begin + wait until rising_edge(CLK); + shift_RDO <= shift_RDO(2 downto 0) & A_RDO; + buf_A_RDO <= shift_RDO(3) and shift_RDO(2) and shift_RDO(1); + end process; + + REG_OUTPUTS : process begin + wait until rising_edge(CLK); + if io_override(1) = '1' then + A_GDE <= io_set_outputs(16); + A_MOD <= io_set_outputs(17); + A_RDM <= io_set_outputs(18); + A_RES <= io_set_outputs(19); + A_TOK <= io_set_outputs(20); + A_WRM <= io_set_outputs(21); + else + A_GDE <= buf_A_GDE; + A_MOD <= buf_A_MOD; + A_RDM <= buf_A_RDM; + A_RES <= buf_A_RES; + A_TOK <= buf_A_TOK; + A_WRM <= buf_A_WRM; + end if; + end process; +-- ------------------------------------------------------------------------------- --- I/O +-- status registers ------------------------------------------------------------------------------- DEBUG_OUT <= debug_control_i; FEE_DATA_FINISHED_OUT <= fee_data_finished_i; @@ -667,7 +778,7 @@ counter_retransmit_sent_i <= (others => '0'); process(CLK) begin if rising_edge(CLK) then - token_missing_reg_i <= (token_missing_i or token_missing_reg_i) and not reset_statistics_i; + token_missing_reg_i <= (token_missing_i or token_missing_reg_i) and not COMMON_CTRL_REG_IN(4); COMMON_STAT_REG_OUT <= (others => '0'); COMMON_STAT_REG_OUT(6) <= not debug_ctrl_line_handle_i(8); @@ -675,6 +786,60 @@ counter_retransmit_sent_i <= (others => '0'); end if; end process; +------------------------------------------------------------------------------- +-- I/O Override +------------------------------------------------------------------------------- + PROC_IO_READ_MUX : process begin + wait until rising_edge(CLK); + IO_DATA_TX <= (others => '0'); + case IO_ADDR_IN is + when "00" => IO_DATA_TX <= (others => '0'); + when "01" => IO_DATA_TX(2 downto 0) <= io_override; + when "10" => IO_DATA_TX <= x"00" & "00" & buf_A_WRM & buf_A_TOK & buf_A_RES & buf_A_RDM & buf_A_MOD & buf_A_GDE & x"000" & io_set_outputs(3 downto 1) & reg_JTAG_TDO; +-- when "10" => IO_DATA_TX <= x"00" & x"00" & x"000" & io_set_outputs(3 downto 1) & reg_JTAG_TDO; + when "11" => IO_DATA_TX <= doing_readout & "00" & rsv_in_i & "000" & databus_output_enable & "000" & io_set_adbus(20) & "000" & dst_in_i & "000" & aod_in_i & "000" & add_in_i; + end case; + end process; + + PROC_IO_RW_SIGNALS : process begin + wait until rising_edge(CLK); + IO_READY_OUT <= IO_READ_IN; + IO_WRITE_ACK_OUT <= IO_WRITE_IN; + end process; + + PROC_IO_WRITE : process begin + wait until rising_edge(CLK); + if IO_WRITE_IN = '1' then + case IO_ADDR_IN is + when "00" => null; + when "01" => io_override <= IO_DATA_RX(2 downto 0); + when "10" => io_set_outputs <= IO_DATA_RX; + when "11" => io_set_adbus <= IO_DATA_RX; + end case; + end if; + if RESET = '1' then + io_override <= (others => '0'); + end if; + end process; + +process begin + wait until rising_edge(CLK); + if start_readout_i = '1' then + doing_readout <= '1'; + elsif finished_readout_i = '1' then + doing_readout <= '0'; + end if; +end process; + +--------------------------------------------------------------------- +-- JTAG +--------------------------------------------------------------------- + JTAG_TDI <= io_set_outputs(1) when io_override(0) = '1' else '0'; + JTAG_TMS <= io_set_outputs(2) when io_override(0) = '1' else '0'; + JTAG_TCK <= io_set_outputs(3) when io_override(0) = '1' else '0'; + reg_JTAG_TDO <= JTAG_TDO when rising_edge(CLK); + + --------------------------------------------------------------------- -- Status Register diff --git a/design2/mdc_data_statistics.vhd b/design2/mdc_data_statistics.vhd new file mode 100644 index 0000000..8036e9f --- /dev/null +++ b/design2/mdc_data_statistics.vhd @@ -0,0 +1,114 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + + +entity mdc_data_statistics is + port( + CLK : in std_logic; + DATA_IN : in std_logic_vector(31 downto 0); + UPDATE_IN : in std_logic; + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + + RAM_DATA_OUT : out std_logic_vector(31 downto 0); + RAM_ADDR_IN : in std_logic_vector(7 downto 0); + RAM_READ_IN : in std_logic; + RAM_WRITE_IN : in std_logic; + RAM_READY_OUT : out std_logic + ); +end entity; + + +architecture mdc_data_statistics_arch of mdc_data_statistics is + +type fsm_states is (IDLE, READ, ADD, READ_DAT, ADD_DAT, RESET); +signal state : fsm_states; + +type ram_t is array (0 to 255) of std_logic_vector(31 downto 0); +signal ram: ram_t; + + +signal data_reg : std_logic_vector(31 downto 0); +signal update_reg : std_logic; +signal ram_wr : std_logic; +signal ram_addr : integer range 0 to 255; +signal ram_dout_i : std_logic_vector(31 downto 0); +signal ram_din : std_logic_vector(31 downto 0); + +signal ram_ready_i: std_logic; +signal is_calib : std_logic; + +signal counter : integer range 0 to 255; + +begin + +THE_RAM: process + begin + wait until rising_edge(CLK); + RAM_DATA_OUT <= ram(to_integer(unsigned(RAM_ADDR_IN))); + ram_dout_i <= ram(ram_addr); + if ram_wr = '1' then + ram(ram_addr) <= ram_din; + end if; + ram_ready_i <= RAM_READ_IN; + RAM_READY_OUT <= ram_ready_i; + end process; + + +data_reg <= DATA_IN when rising_edge(CLK); +update_reg <= UPDATE_IN when rising_edge(CLK); + + +THE_FSM: process + begin + wait until rising_edge(CLK); + ram_wr <= '0'; + + case state is + when IDLE => + if UPDATE_IN = '1' and DATA_IN(31 downto 29) = "100" then + ram_addr <= to_integer(unsigned(DATA_IN(28 downto 22))); + state <= READ; + is_calib <= TRG_TYPE_IN(3); + end if; + when READ => + state <= ADD; + when ADD => + ram_din <= std_logic_vector(unsigned(ram_dout_i) + to_unsigned(1,32)); + ram_wr <= '1'; + if is_calib = '1' then + state <= IDLE; + else + state <= READ_DAT; + ram_addr <= to_integer(unsigned(DATA_IN(28 downto 22))) + 128; + end if; + when READ_DAT => + state <= ADD_DAT; + when ADD_DAT => + ram_din <= std_logic_vector(unsigned(ram_dout_i) + to_unsigned(1,32)); + ram_wr <= '1'; + state <= IDLE; + when RESET => + counter <= counter + 1; + ram_addr <= counter; + ram_wr <= '1'; + ram_din <= (others => '0'); + if counter = 255 then + state <= IDLE; + end if; + end case; + + if RAM_WRITE_IN = '1' then + state <= RESET; + counter <= 0; + end if; + + end process; + + +end architecture; \ No newline at end of file diff --git a/design2/mdc_oepb_pack.vhd b/design2/mdc_oepb_pack.vhd index ef6fd66..75b341c 100644 --- a/design2/mdc_oepb_pack.vhd +++ b/design2/mdc_oepb_pack.vhd @@ -104,6 +104,21 @@ package mdc_oepb_pack is end component; +component mdc_data_statistics + port( + CLK : in std_logic; + DATA_IN : in std_logic_vector(31 downto 0); + UPDATE_IN : in std_logic; + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + + RAM_DATA_OUT : out std_logic_vector(31 downto 0); + RAM_ADDR_IN : in std_logic_vector(7 downto 0); + RAM_READ_IN : in std_logic; + RAM_WRITE_IN : in std_logic; + RAM_READY_OUT : out std_logic + ); +end component; + component edge_to_pulse is port ( clock : in std_logic; @@ -186,16 +201,35 @@ package mdc_oepb_pack is STATISTIC_READ_IN : in std_logic; STATISTIC_READY_OUT : out std_logic; + STAT_RAM_ADDR_IN : in std_logic_vector(7 downto 0); + STAT_RAM_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_RAM_READ_IN : in std_logic; + STAT_RAM_WRITE_IN : in std_logic; + STAT_RAM_READY_OUT : out std_logic; + RB_DATA_OUT : out std_logic_vector(31 downto 0); --Readback fifo RB_READ_ENABLE_IN : in std_logic; RB_READY_OUT : out std_logic; RB_EMPTY_OUT : out std_logic; + IO_ADDR_IN : in std_logic_vector(1 downto 0); + IO_DATA_RX : in std_logic_vector(31 downto 0); + IO_DATA_TX : out std_logic_vector(31 downto 0); + IO_READ_IN : in std_logic; + IO_WRITE_IN : in std_logic; + IO_WRITE_ACK_OUT : out std_logic; + IO_READY_OUT : out std_logic; + + JTAG_TDO : in std_logic; + JTAG_TDI : out std_logic; + JTAG_TCK : out std_logic; + JTAG_TMS : out std_logic; + COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0); COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0); STAT_REG_OUT : out std_logic_vector(63 downto 0); CTRL_REG_IN : in std_logic_vector(127 downto 0); - STAT_TRIGGER_IN : in std_logic_vector(63 downto 0); + STAT_TRIGGER_IN : in std_logic_vector(79 downto 0); TIMER_TICKS_IN : in std_logic_vector(1 downto 0); DEBUG_OUT : out std_logic_vector(31 downto 0) @@ -390,6 +424,7 @@ package mdc_oepb_pack is FINISHED_READOUT_OUT : out std_logic; --Readout if finished FINISHED_CYCLE_OUT : out std_logic; --All entities back to idle RESET_MBO_OUT : out std_logic; + CMS_ENABLE_OUT : out std_logic; --FSM status FINISHED_BEGRUN_IN : in std_logic; --loading settings finished diff --git a/design2/tdc_readout.vhd b/design2/tdc_readout.vhd index 6f87209..984b11d 100644 --- a/design2/tdc_readout.vhd +++ b/design2/tdc_readout.vhd @@ -65,7 +65,7 @@ begin end process; - PROC_FSM_COMB : process(current_state, TOKEN_IN, START_READOUT_IN, A_DST_IN, A_AOD_IN, TOKEN_IN) + PROC_FSM_COMB : process(current_state, TOKEN_IN, START_READOUT_IN, A_DST_IN, A_AOD_IN) begin next_state <= current_state; diff --git a/design2/trigger_handler.vhd b/design2/trigger_handler.vhd index 7f8ce80..2649aae 100644 --- a/design2/trigger_handler.vhd +++ b/design2/trigger_handler.vhd @@ -38,6 +38,7 @@ entity trigger_handler is FINISHED_READOUT_OUT : out std_logic; --readout is finished FINISHED_CYCLE_OUT : out std_logic; --All entities back to idle RESET_MBO_OUT : out std_logic; + CMS_ENABLE_OUT : out std_logic; --FSM status FINISHED_BEGRUN_IN : in std_logic; --loading settings finished @@ -305,6 +306,8 @@ begin INC_CALIB_OUT <= inc_calib_counter; INC_TRIGGER_OUT <= inc_trigger_counter; + CMS_ENABLE_OUT <= '1' when (current_state = IDLE or current_state = TIMING_TRIGGER) and mbo_configured_i = '1' else '0'; + proc_statusbits : process(CLK) begin if rising_edge(CLK) then diff --git a/mdc_oepb.p2t b/mdc_oepb.p2t index d5dc65d..82c5dca 100644 --- a/mdc_oepb.p2t +++ b/mdc_oepb.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 1 +-t 3 #-s 12 -c 1 -e 2 diff --git a/mdc_oepb.prj b/mdc_oepb.prj index ba46a66..22668c0 100644 --- a/mdc_oepb.prj +++ b/mdc_oepb.prj @@ -101,7 +101,7 @@ add_file -vhdl -lib work "design2/send_token_to_mb.vhd" add_file -vhdl -lib work "design2/tdc_readout.vhd" add_file -vhdl -lib work "design2/trigger_begrun_state.vhd" add_file -vhdl -lib work "design2/trigger_handler.vhd" - +add_file -vhdl -lib work "design2/mdc_data_statistics.vhd" add_file -vhdl -lib work "version.vhd" diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 1778b37..0d81b42 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -30,8 +30,6 @@ use work.lattice_ecp2m_fifo.all; -- 0x22 Bit 21 -> select dummy data (0: normal data, 1: dummy data) -- 0x22 Bit 30 -> select debug output (0: off, 1: on) -- --- 0x80 15-0 -> trigger edge count --- 0x80 23-16 -> trigger length -- 0xc0 0x0010 -> select short -- 0xc0 0x0020 -> select long -- 0xc0 0x8000 -> switch trigger polarity @@ -67,6 +65,11 @@ entity mdc_oepb is ADC_SDI : out std_logic; ADC_SDO : in std_logic; ADC_CONVST : out std_logic; + --JTAG +-- JTAG_TDO : in std_logic; +-- JTAG_TDI : out std_logic; +-- JTAG_TCK : out std_logic; +-- JTAG_TMS : out std_logic; --SPI SPI_CLK : out std_logic; SPI_CS : out std_logic; @@ -97,12 +100,14 @@ architecture mdc_oepb_arch of mdc_oepb is --Clock and Reset signal clk_100 : std_logic; signal pll_locked : std_logic; + signal pll_locked_2 : std_logic; signal reset_startup : std_logic; signal reset_internal : std_logic; signal reset_sync : std_logic; signal reset_async : std_logic; signal reset_counter : std_logic_vector(23 downto 0); signal gsr_n : std_logic; + signal rx_clock : std_logic; --Media Interface to internal logic signal med_data_in : std_logic_vector(16-1 downto 0); @@ -290,20 +295,42 @@ architecture mdc_oepb_arch of mdc_oepb is signal medreg_ready: std_logic; signal medreg_write: std_logic; - signal trigger_status_i : std_logic_vector(63 downto 0); + signal trigger_status_i : std_logic_vector(79 downto 0); + + signal stat_ram_data : std_logic_vector(31 downto 0); + signal stat_ram_addr : std_logic_vector(7 downto 0); + signal stat_ram_ready : std_logic; + signal stat_ram_write : std_logic; + signal stat_ram_read : std_logic; + + signal io_addr : std_logic_vector(1 downto 0); + signal io_data_rx : std_logic_vector(31 downto 0); + signal io_data_tx : std_logic_vector(31 downto 0); + signal io_write : std_logic; + signal io_read : std_logic; + signal io_ready : std_logic; + signal io_write_ack: std_logic; + begin --------------------------------------------------------------------- -- PLL: 100 MHz --------------------------------------------------------------------- - PLL100 : pll_in25_out100 + PLL100_lock : pll_in25_out100 port map( CLK => CLK, - CLKOP => clk_100, + CLKOP => open, LOCK => pll_locked ); + PLL100 : pll_in25_out100 + port map( + CLK => rx_clock, + CLKOP => clk_100, + LOCK => pll_locked_2 + ); + reset_async <= not gsr_n; gsr_n <= pll_locked; @@ -334,7 +361,7 @@ begin THE_RESET_COUNTER_PROC: process(CLK) begin if rising_edge(CLK) then - if MED_STAT_OP(13) = '1' or pll_locked = '0' then --pll not locked or reset request received + if MED_STAT_OP(13) = '1' or pll_locked = '0' or pll_locked_2 = '0' then --pll not locked or reset request received reset_counter <= x"000E00"; reset_internal <= '1'; reset_startup <= '1'; @@ -383,6 +410,7 @@ begin SD => SD, -- Status and control port + RX_CLOCK_OUT => rx_clock, STAT_OP => MED_STAT_OP, CTRL_OP => MED_CTRL_OP, STAT_REG_OUT => med_stat_reg_i, @@ -498,11 +526,13 @@ begin THE_REG_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 10, + PORT_NUMBER => 12, PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", - 5 => x"e000", 6 => x"9000", 7 => x"e100", 8 => x"9100", 9 => x"9200", others => x"0000"), + 5 => x"e000", 6 => x"9000", 7 => x"e100", 8 => x"9100", 9 => x"9200", + 10 => x"C000", 11 => x"e400", others => x"0000"), PORT_ADDR_MASK => (0 => 9, 1 => 6, 2 => 1, 3 => 6, 4 => 0, - 5 => 0, 6 => 4, 7 => 0, 8 => 5, 9 => 2, others => 0) + 5 => 0, 6 => 4, 7 => 0, 8 => 5, 9 => 2, + 10 => 8, 11 => 2, others => 0) ) port map( CLK => clk_100, @@ -639,6 +669,30 @@ begin BUS_WRITE_ACK_IN(9) => '0', BUS_NO_MORE_DATA_IN(9) => '0', BUS_UNKNOWN_ADDR_IN(9) => medreg_write, + --Channel Statistics RAM + BUS_READ_ENABLE_OUT(10) => stat_ram_read, + BUS_WRITE_ENABLE_OUT(10) => stat_ram_write, + BUS_DATA_OUT(10*32+31 downto 10*32) => open, + BUS_ADDR_OUT(10*16+7 downto 10*16) => stat_ram_addr, + BUS_ADDR_OUT(10*16+15 downto 10*16+8)=> open, + BUS_TIMEOUT_OUT(10) => open, + BUS_DATA_IN(10*32+31 downto 10*32) => stat_ram_data, + BUS_DATAREADY_IN(10) => stat_ram_ready, + BUS_WRITE_ACK_IN(10) => stat_ram_write, + BUS_NO_MORE_DATA_IN(10) => '0', + BUS_UNKNOWN_ADDR_IN(10) => '0', + -- I/O Debug and Override + BUS_READ_ENABLE_OUT(11) => io_read, + BUS_WRITE_ENABLE_OUT(11) => io_write, + BUS_DATA_OUT(11*32+31 downto 11*32) => io_data_rx, + BUS_ADDR_OUT(11*16+1 downto 11*16) => io_addr, + BUS_ADDR_OUT(11*16+15 downto 11*16+2)=> open, + BUS_TIMEOUT_OUT(11) => open, + BUS_DATA_IN(11*32+31 downto 11*32) => io_data_tx, + BUS_DATAREADY_IN(11) => io_ready, + BUS_WRITE_ACK_IN(11) => io_write_ack, + BUS_NO_MORE_DATA_IN(11) => '0', + BUS_UNKNOWN_ADDR_IN(11) => '0', --Debugging STAT_DEBUG => open ); @@ -900,11 +954,30 @@ begin STATISTIC_READ_IN => statisticreg_read, STATISTIC_READY_OUT => statisticreg_ready, + STAT_RAM_ADDR_IN => stat_ram_addr, + STAT_RAM_DATA_OUT => stat_ram_data, + STAT_RAM_READ_IN => stat_ram_read, + STAT_RAM_WRITE_IN => stat_ram_write, + STAT_RAM_READY_OUT => stat_ram_ready, + RB_DATA_OUT => readback_mem_data_out, RB_READ_ENABLE_IN => readback_mem_read, RB_READY_OUT => readback_mem_ready, RB_EMPTY_OUT => readback_mem_empty, + IO_ADDR_IN => io_addr, + IO_DATA_RX => io_data_rx, + IO_DATA_TX => io_data_tx, + IO_READ_IN => io_read, + IO_WRITE_IN => io_write, + IO_WRITE_ACK_OUT => io_write_ack, + IO_READY_OUT => io_ready, + + JTAG_TDO => '0', --JTAG_TDO, + JTAG_TDI => open, --JTAG_TDI, + JTAG_TCK => open, --JTAG_TCK, + JTAG_TMS => open, --JTAG_TMS, + COMMON_STAT_REG_OUT => mdccontrol_common_stat_reg_out(63 downto 0), COMMON_CTRL_REG_IN => reg_common_ctrl_reg_out, STAT_REG_OUT => reg_registers_in, @@ -916,7 +989,69 @@ begin DEBUG_OUT => debug_mdc_control_i ); +------------------------------------------------------------------------------- +-- LED +------------------------------------------------------------------------------- +-- D(4) <= not buf_restart_led; -- toggle with restart +-- D(3) <= not buf_request_led; -- toggle with request +-- D(2) <= not buf_reset_led; -- toggle with network reset +-- D(1) <= med_stat_debug(51); -- not comma locked + +D(4) <= not led_blink; +D(3) <= not led_blink; +D(2) <= not led_blink; +D(1) <= not led_blink; + + process(clk_100) + begin + if rising_edge(clk_100) then + if timer_ticks(1) = '1' then + time_counter <= time_counter + 1; + end if; + + led_blink <= blink_enable and time_counter(8); + + if med_stat_op(13) = '1' then + buf_reset_led <= not buf_reset_led; + end if; + if med_stat_debug(17) = '1' then + buf_restart_led <= not buf_restart_led; + end if; + if med_stat_debug(16) = '1' then + buf_request_led <= not buf_request_led; + end if; + end if; + end process; + + + + reg_common_stat_reg_in(13 downto 0) <= mdccontrol_common_stat_reg_out(13 downto 0); + reg_common_stat_reg_in(14) <= sederr_i; + reg_common_stat_reg_in(63 downto 15) <= mdccontrol_common_stat_reg_out(63 downto 15); + reg_common_stat_reg_in(143 downto 64) <= (others => '0'); + reg_common_stat_reg_in(159 downto 144) <= (others => '0'); + blink_enable <= reg_registers_out(32); + + +------------------------------------------------------------------------------- +-- SEU circuit +------------------------------------------------------------------------------- +-- CHECK_COMP: SEDAA +-- -- synthesis translate_off +-- generic map ( +-- OSC_DIV :string => "1" +-- ); +-- -- synthesis translate_on +-- port map ( +-- SEDENABLE => '1',--SED enable active high +-- SEDSTART => '1',--SED start active high +-- SEDFRCERR => '0', +-- SEDERR => sederr_i, --pulse when s/th wrong +-- SEDDONE => seddone_i,--open,--SED cycle complete active high +-- SEDINPROG => sedinprog_i,--open, +-- SEDCLKOUT => sedclkout_i--open +-- ); --------------------------------------------------------------------- --Test... @@ -1035,93 +1170,6 @@ begin -- ); -------------------------------------------------------------------------------- --- LED -------------------------------------------------------------------------------- - D(4) <= not buf_restart_led; -- toggle with restart - D(3) <= not buf_request_led; -- toggle with request - D(2) <= not buf_reset_led; -- toggle with network reset - D(1) <= med_stat_debug(51); -- not comma locked - - - - - process(clk_100) - begin - if rising_edge(clk_100) then - if timer_ticks(1) = '1' then - time_counter <= time_counter + 1; - end if; - - if blink_enable = '1' then - led_blink <= time_counter(8); - else - led_blink <= '0'; - end if; - - if med_stat_op(13) = '1' then - buf_reset_led <= not buf_reset_led; - end if; - if med_stat_debug(17) = '1' then - buf_restart_led <= not buf_restart_led; - end if; - if med_stat_debug(16) = '1' then - buf_request_led <= not buf_request_led; - end if; - --- TAD(7 downto 0) <= med_stat_debug(39 downto 32); --- TAD(8) <= med_stat_debug(62); --- TAOD <= med_stat_op(8); --- TDST <= med_stat_op(12); - - --- TAD(3 downto 0) <= MED_STAT_OP(7 downto 4); --- TAD(4) <= reset_internal; --- TAD(5) <= reset_startup; --- TAD(6) <= reset_async; --- TAD(7) <= MED_STAT_DEBUG(49); --- TAD(8) <= MED_STAT_DEBUG(50); --- TAOD <= MED_STAT_DEBUG(51); --- TDST <= MED_STAT_DEBUG(52); --- RDYI <= MED_STAT_DEBUG(53); --- GDE <= MED_STAT_DEBUG(54); --- MODD <= MED_STAT_DEBUG(55); --- RES <= MED_STAT_DEBUG(63); - - end if; - end process; - - - - reg_common_stat_reg_in(13 downto 0) <= mdccontrol_common_stat_reg_out(13 downto 0); - reg_common_stat_reg_in(14) <= sederr_i; - reg_common_stat_reg_in(63 downto 15) <= mdccontrol_common_stat_reg_out(63 downto 15); - reg_common_stat_reg_in(143 downto 64) <= (others => '0'); - reg_common_stat_reg_in(159 downto 144) <= (others => '0'); - blink_enable <= reg_registers_out(32); - - -------------------------------------------------------------------------------- --- SEU circuit -------------------------------------------------------------------------------- --- CHECK_COMP: SEDAA --- -- synthesis translate_off --- generic map ( --- OSC_DIV :string => "1" --- ); --- -- synthesis translate_on --- port map ( --- SEDENABLE => '1',--SED enable active high --- SEDSTART => '1',--SED start active high --- SEDFRCERR => '0', --- SEDERR => sederr_i, --pulse when s/th wrong --- SEDDONE => seddone_i,--open,--SED cycle complete active high --- SEDINPROG => sedinprog_i,--open, --- SEDCLKOUT => sedclkout_i--open --- ); - - - end architecture; -- 2.43.0