From 6a3e6cba9f0083e82b11e8f9986ea1994b0d2bd9 Mon Sep 17 00:00:00 2001
From: palka <palka>
Date: Thu, 8 May 2008 08:18:00 +0000
Subject: [PATCH] dwitched nibles of incoming data, changing timing for
 synchronization

---
 optical_link/flexi_PCS_channel_synch.vhd | 33 ++++++++++++++----------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd
index bd118a4..e9827d3 100644
--- a/optical_link/flexi_PCS_channel_synch.vhd
+++ b/optical_link/flexi_PCS_channel_synch.vhd
@@ -286,9 +286,9 @@ begin
     if rising_edge(RX_CLK) then
       if RESET = '1' then                 
         fifo_data_in <= (others => '0');
-      elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then
-        fifo_data_in <= '0' & (not RX_K(0)) & RXD;
       elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then
+        fifo_data_in <= '0' & (not RX_K(0)) & RXD;
+      elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then
         fifo_data_in <= '0' & (not RX_K(1)) & RXD(7 downto 0) & RXD(15 downto 8);
       else
         fifo_data_in <= (others => '0');
@@ -296,9 +296,10 @@ begin
     end if;
   end process SHIFT_OR_NOT_DATA_IN;
 
-  SYNCH_CLOCK   : process (RX_CLK, RESET)
+--  SYNCH_CLOCK   : process (RX_CLK, RESET)
+  SYNCH_CLOCK   : process (SYSTEM_CLK, RESET)
   begin
-    if rising_edge (RX_CLK) then
+    if rising_edge (SYSTEM_CLK) then
       if RESET = '1' then
         SYNCH_CURRENT <= IDLE;
         cv_i <= (others => '0');
@@ -332,7 +333,7 @@ begin
         rx_rst_i       <= '1';
         resync_counter_up <= '1';
         resync_counter_clr <= '0';
-        if resync_counter = 200 then
+        if resync_counter(8) = '1' then
           SYNCH_NEXT <= RESYNC2;
         else
           SYNCH_NEXT <= RESYNC1;
@@ -340,11 +341,11 @@ begin
        when RESYNC2 =>
          fifo_rst <= '0';
          fifo_wr_en <= '0';
-         fsm_debug_register(2 downto 0) <= "011";
+         fsm_debug_register(2 downto 0) <= "010";
          rx_rst_i       <= '0';
          resync_counter_up <= '1';
          resync_counter_clr <= '0';
-       if resync_counter(17) = '1' then  --at least 400us 
+       if resync_counter(16) = '1' then  --at least 400us 
          SYNCH_NEXT <= RESYNC3;
        else
          SYNCH_NEXT <= RESYNC2;
@@ -353,13 +354,13 @@ begin
        when RESYNC3 =>
          fifo_rst <= '0';
          fifo_wr_en <= '0';
-         fsm_debug_register(2 downto 0) <= "100";
+         fsm_debug_register(2 downto 0) <= "010";
          rx_rst_i       <= '0';
          resync_counter_up <= '0';
          resync_counter_clr <= '1';
-         if rxd_synch_i = x"bc50" then
+         if rxd_synch_i = x"bc50" and rx_k_synch_i(1) = '1' then
            SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;
-         elsif rxd_synch_i = x"50bc" then
+         elsif rxd_synch_i = x"50bc" and rx_k_synch_i(0) = '1' then
            SYNCH_NEXT <= WAIT_2;--NORMAL_OPERATION_2;
          else
            SYNCH_NEXT <= IDLE;
@@ -368,11 +369,13 @@ begin
         fifo_rst <= '0';
         rx_rst_i   <= '0';
         fifo_wr_en <= '0';
-        fsm_debug_register(2 downto 0) <= "101";
+        fsm_debug_register(2 downto 0) <= "011";
         resync_counter_up <= '1';
         resync_counter_clr <= '0';
-        if resync_counter(29) = '1' then
+        if resync_counter(27) = '1' and rxd_synch_i = x"bc50" and rx_k_synch_i(1) = '1' then
           SYNCH_NEXT <= NORMAL_OPERATION_1;
+        elsif resync_counter(29) = '1' and (rxd_synch_i /= x"bc50" or rx_k_synch_i(1) = '0') then
+          SYNCH_NEXT <= RESYNC1; 
         else
           SYNCH_NEXT <= WAIT_1;
         end if;
@@ -380,11 +383,13 @@ begin
         fifo_rst <= '0';
         fifo_wr_en <= '0';
         rx_rst_i       <= '0';
-        fsm_debug_register(2 downto 0) <= "101";
+        fsm_debug_register(2 downto 0) <= "011";
         resync_counter_up <= '1';
         resync_counter_clr <= '0';
-        if resync_counter(29) = '1' then
+        if resync_counter(27) = '1' and rxd_synch_i = x"50bc" and rx_k_synch_i(0) = '1' then
           SYNCH_NEXT <= NORMAL_OPERATION_2;
+        elsif resync_counter(29) = '1' and (rxd_synch_i /= x"50bc" or rx_k_synch_i(0) = '0') then
+          SYNCH_NEXT <= RESYNC1;
         else
           SYNCH_NEXT <= WAIT_2;
         end if;
-- 
2.43.0