From 6b553424897b49261444ed8889b3d1384d54f00d Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 11 Aug 2017 15:29:51 +0200 Subject: [PATCH] use hitbus/szintillator from 100 MHz domain to increment number of seen edges counters. --- mupix/sources/MuPix3_board.vhd | 6 ++- mupix/sources/TimeWalk.vhd | 83 +++++++++++++++++------------- mupix/sources/TimeWalkWithFiFo.vhd | 20 ++++--- mupix/sources/mupix_components.vhd | 6 ++- 4 files changed, 64 insertions(+), 51 deletions(-) diff --git a/mupix/sources/MuPix3_board.vhd b/mupix/sources/MuPix3_board.vhd index e49a93d..e623ded 100644 --- a/mupix/sources/MuPix3_board.vhd +++ b/mupix/sources/MuPix3_board.vhd @@ -392,8 +392,10 @@ begin -- Behavioral trb_slv_clock => clk, fast_clk => fast_clk, reset => reset, - hitbus => hbus_from_mupix_fast_sync, - szintillator_trigger => szintilator_fast_sync, + hitbus => hbus_from_mupix_sync, + hitbus_fast => hbus_from_mupix_fast_sync, + szintillator_trigger => szintilator_sync, + szintillator_trigger_fast => szintilator_fast_sync, SLV_READ_IN => slv_read(8), SLV_WRITE_IN => slv_write(8), SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), diff --git a/mupix/sources/TimeWalk.vhd b/mupix/sources/TimeWalk.vhd index 8877d5e..018f038 100644 --- a/mupix/sources/TimeWalk.vhd +++ b/mupix/sources/TimeWalk.vhd @@ -12,7 +12,7 @@ entity TimeWalk is clk : in std_logic; reset : in std_logic; hitbus : in std_logic; - hitbus_timeout : in std_logic_vector(31 downto 0); + hitbus_timeout : in std_logic_vector(15 downto 0); szintillator_trigger : in std_logic; readyToWrite : in std_logic; measurementFinished : out std_logic; @@ -59,47 +59,58 @@ begin -- architecture TimeWalk_Arch signal_synchro: process (clk) is begin -- process clk if rising_edge(clk) then - hitbus_edge <= hitbus_edge(0) & hitbus_delayed; - szintillator_trigger_buffer <= szintillator_trigger; - szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger_buffer; + if reset = '1' then + hitbus_edge <= (others => '0'); + szintillator_trigger_edge <= (others => '0'); + else + hitbus_edge <= hitbus_edge(0) & hitbus_delayed; + szintillator_trigger_buffer <= szintillator_trigger; + szintillator_trigger_edge <= szintillator_trigger_edge(0) & szintillator_trigger_buffer; + end if; end if; end process signal_synchro; TimeWalk_Measurement : process (clk) is begin -- process TimeWalk_Measurement if rising_edge(clk) then - measurementFinished <= '0'; - measurementData <= (others => '0'); - case timewalk_fsm is - when idle => - latencycounter <= (others => '0'); - hitbuscounter <= (others => '0'); - if szintillator_trigger_edge = "01" then - timewalk_fsm <= waitforhitbus; - end if; - when waitforhitbus => - latencycounter <= latencycounter + 1; - if latencycounter = unsigned(hitbus_timeout(15 downto 0)) then - timewalk_fsm <= idle; - elsif hitbus_edge = "01" then - timewalk_fsm <= measurehitbus; - else - timewalk_fsm <= waitforhitbus; - end if; - when measurehitbus => - if hitbus_edge = "00" then - timewalk_fsm <= measurement_done; - else - hitbuscounter <= hitbuscounter + 1; - timewalk_fsm <= measurehitbus; - end if; - when measurement_done => - timewalk_fsm <= idle; - if readyToWrite = '1' then - measurementData <= std_logic_vector(latencycounter & hitbuscounter); - measurementFinished <= '1'; - end if; - end case; + if reset = '1' then + timewalk_fsm <= idle; + else + measurementFinished <= '0'; + measurementData <= (others => '0'); + case timewalk_fsm is + when idle => + latencycounter <= (others => '0'); + hitbuscounter <= (others => '0'); + if szintillator_trigger_edge = "01" then + timewalk_fsm <= waitforhitbus; + else + timewalk_fsm <= idle; + end if; + when waitforhitbus => + latencycounter <= latencycounter + 1; + if hitbus_edge = "01" then + timewalk_fsm <= measurehitbus; + elsif latencycounter = unsigned(hitbus_timeout) then + timewalk_fsm <= idle; + else + timewalk_fsm <= waitforhitbus; + end if; + when measurehitbus => + hitbuscounter <= hitbuscounter + 1; + if hitbus_edge = "10" then + timewalk_fsm <= measurement_done; + else + timewalk_fsm <= measurehitbus; + end if; + when measurement_done => + timewalk_fsm <= idle; + if readyToWrite = '1' then + measurementData <= std_logic_vector(latencycounter & hitbuscounter); + measurementFinished <= '1'; + end if; + end case; + end if; end if; end process TimeWalk_Measurement; diff --git a/mupix/sources/TimeWalkWithFiFo.vhd b/mupix/sources/TimeWalkWithFiFo.vhd index 59bcaac..c04d1b3 100644 --- a/mupix/sources/TimeWalkWithFiFo.vhd +++ b/mupix/sources/TimeWalkWithFiFo.vhd @@ -16,7 +16,9 @@ entity TimeWalkWithFiFo is fast_clk : in std_logic; -- fast clock samples hitbus and szintilator reset : in std_logic; hitbus : in std_logic; + hitbus_fast : in std_logic; szintillator_trigger : in std_logic; + szintillator_trigger_fast : in std_logic; -- trb slowcontrol SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -32,15 +34,13 @@ end entity TimeWalkWithFiFo; architecture TimeWalk_arch of TimeWalkWithFiFo is constant bitsBeforeWriteCounter : integer := 2; - signal hitbus_timeout : std_logic_vector(31 downto 0) := x"00000024"; + signal hitbus_timeout : std_logic_vector(15 downto 0) := x"0024"; signal resetcounters : std_logic := '0'; signal hitbusEdgeCounter : unsigned(31 downto 0) := (others => '0'); signal szintilatorEdgeCounter : unsigned(31 downto 0) := (others => '0'); signal hitbusRisingEdge : std_logic_vector(1 downto 0) := (others => '0'); signal szintilatorRisingEdge : std_logic_vector(1 downto 0) := (others => '0'); - signal hitbus_buffer : std_logic := '0'; - signal szintilator_trigger_buffer : std_logic := '0'; signal FiFo_Wren : std_logic := '0'; signal FiFo_data_in : std_logic_vector(31 downto 0) := (others => '0'); @@ -96,9 +96,9 @@ begin -- architecture TimeWalk_arch port map ( clk => fast_clk, reset => reset, - hitbus => hitbus, + hitbus => hitbus_fast, hitbus_timeout => hitbus_timeout, - szintillator_trigger => szintillator_trigger, + szintillator_trigger => szintillator_trigger_fast, readyToWrite => not FiFo_full, measurementFinished => FiFo_Wren, measurementData => FiFo_data_in); @@ -109,10 +109,8 @@ begin -- architecture TimeWalk_arch edge_counter: process (trb_slv_clock) is begin -- process edge_counter if rising_edge(trb_slv_clock) then - hitbus_buffer <= hitbus; - szintilator_trigger_buffer <= szintillator_trigger; - hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus_buffer; - szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintilator_trigger_buffer; + hitbusRisingEdge <= hitbusRisingEdge(0) & hitbus; + szintilatorRisingEdge <= szintilatorRisingEdge(0) & szintillator_trigger; if resetcounters = '1' then szintilatorEdgeCounter <= (others => '0'); hitbusEdgeCounter <= (others => '0'); @@ -205,7 +203,7 @@ begin -- architecture TimeWalk_arch elsif slv_write_in = '1' then case SLV_ADDR_IN is when x"0403" => - hitbus_timeout <= slv_data_in; + hitbus_timeout <= slv_data_in(15 downto 0); slv_ack_out <= '1'; when x"0406" => resetcounters <= slv_data_in(0); @@ -226,7 +224,7 @@ begin -- architecture TimeWalk_arch fifo_start_read <= '1'; fifo_reading_s <= '1'; when x"0403" => - slv_data_out <= hitbus_timeout; + slv_data_out(15 downto 0) <= hitbus_timeout; slv_ack_out <= '1'; when x"0404" => slv_data_out <= szintilatorEdgeCounter; diff --git a/mupix/sources/mupix_components.vhd b/mupix/sources/mupix_components.vhd index 7624e7f..a105e31 100644 --- a/mupix/sources/mupix_components.vhd +++ b/mupix/sources/mupix_components.vhd @@ -296,10 +296,12 @@ package mupix_components is component TimeWalkWithFiFo is port ( trb_slv_clock : in std_logic; - fast_clk : in std_logic; + fast_clk : in std_logic; -- fast clock samples hitbus and szintilator reset : in std_logic; hitbus : in std_logic; + hitbus_fast : in std_logic; szintillator_trigger : in std_logic; + szintillator_trigger_fast : in std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -315,7 +317,7 @@ package mupix_components is clk : in std_logic; reset : in std_logic; hitbus : in std_logic; - hitbus_timeout : in std_logic_vector(31 downto 0); + hitbus_timeout : in std_logic_vector(15 downto 0); szintillator_trigger : in std_logic; readyToWrite : in std_logic; measurementFinished : out std_logic; -- 2.43.0