From 6c79152b4caf5b977cb6bca630cd13852da203e4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 10 Feb 2023 14:03:32 +0100 Subject: [PATCH] change CTS to variable trigger logic output number --- cts/trb3sc_cts.lpf | 7 +++++++ cts/trb3sc_cts.vhd | 8 ++++---- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index 3fcc7b1..fe5ce1f 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -13,6 +13,7 @@ LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE BLOCK PATH FROM CELL THE_TDC/calibration_o*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0]; +BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/edge_rising_100_r[0]; # REGION "MEDIA_GBE" "R89C2" 25 53; REGION "MEDIA_A" "R75C100D" 45 46; @@ -117,6 +118,12 @@ MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns #MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; #MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MULTICYCLE FROM ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE FROM ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; + + + PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index d03e6e6..257c562 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -931,19 +931,19 @@ end generate; gen_inputs_kel : if USE_BACKPLANE = 0 and USE_RJADAPT = 0 generate cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0); - cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys); + cts_addon_triggers_in(34 + TRIG_GEN_OUTPUT_NUM - 1 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys); end generate; gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 generate cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(21 downto 2) <= INP(19 downto 0); - cts_addon_triggers_in(23 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys); + cts_addon_triggers_in(22 + TRIG_GEN_OUTPUT_NUM - 1 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys); end generate; gen_inputs_bkpl : if USE_BACKPLANE = 1 generate cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); cts_addon_triggers_in(33 downto 2) <= INP(95 downto 64); - cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys); + cts_addon_triggers_in(34 + TRIG_GEN_OUTPUT_NUM - 1 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys); gen_trg_inputs : for i in 0 to 8 generate - cts_addon_triggers_in(i*2+37 downto i*2+36) <= BACK_TRIG2(i) & BACK_TRIG1(i); + cts_addon_triggers_in(i*2+34 + TRIG_GEN_OUTPUT_NUM - 1 downto i*2+34+TRIG_GEN_OUTPUT_NUM) <= BACK_TRIG2(i) & BACK_TRIG1(i); end generate; end generate; -- 2.43.0