From 6c836f98d7c01bd057839b8e6ba578c86fcee7d9 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 22 Apr 2014 15:28:38 +0200 Subject: [PATCH] correct clock names for the multicycle constraint --- base/trb3_periph_32PinAddOn.lpf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf index 0432b4e..c208a01 100644 --- a/base/trb3_periph_32PinAddOn.lpf +++ b/base/trb3_periph_32PinAddOn.lpf @@ -14,8 +14,8 @@ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; -MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; -MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_i_c" 2 X ; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -- 2.43.0