From 6cb6c8add90aea20913f7016f0522999a772b708 Mon Sep 17 00:00:00 2001 From: palka Date: Mon, 4 Aug 2008 13:09:14 +0000 Subject: [PATCH] no api - test of vulom + ctu (lvl2) --- trb_cts/cts.vhd | 200 +++++++++++++++++++++++++--- trb_cts/fpga_to_etrax_data_flow.vhd | 6 +- trb_cts/vulom_interface.vhd | 9 +- 3 files changed, 192 insertions(+), 23 deletions(-) diff --git a/trb_cts/cts.vhd b/trb_cts/cts.vhd index b4eb64a..5d0c93c 100644 --- a/trb_cts/cts.vhd +++ b/trb_cts/cts.vhd @@ -621,12 +621,17 @@ architecture cts of cts is --ctu signal dtu_debug_00_i : std_logic_vector(31 downto 0); signal lvl2_trigger_i : std_logic; + signal lvl2_code_i : std_logic_vector(3 downto 0); + signal lvl2_tag_i : std_logic_vector(7 downto 0); + signal lvl2_busy_i : std_logic; signal lvl2_trigger_code_i : std_logic_vector(3 downto 0); signal lvl2_trigger_tag_i : std_logic_vector(7 downto 0); signal lvl2_trb_ack_i : std_logic; signal lvl1_trigger_i : std_logic; signal lvl1_trigger_code_i : std_logic_vector(3 downto 0); signal lvl1_trigger_tag_i : std_logic_vector(7 downto 0); + signal lvl1_trigger_saved : std_logic; + signal lvl2_trigger_saved : std_logic; --cts_etrax signal cts_etrax_register_00_i : std_logic_vector(31 downto 0); signal cts_etrax_register_01_i : std_logic_vector(31 downto 0); @@ -695,6 +700,16 @@ architecture cts of cts is signal stat_i : std_logic_vector (63 downto 0); signal stat_op_i : std_logic_vector (15 downto 0); signal ctrl_op_i : std_logic_vector (15 downto 0); + -- no api + type send_lvl1_and_lvl2_trigg is (IDLE, LVL1_A, LVL1_B, LVL1_C, LVL2_A, LVL2_B, LVL2_C); + signal current_state_send_lvl1_and_lvl2_trigg, next_state_send_lvl1_and_lvl2_trigg : send_lvl1_and_lvl2_trigg; + signal not_lvl2_busy_i : std_logic; + signal lvl1_cts_busy : std_logic; + signal lvl1_system_busy : std_logic; + signal lvl2_trb_ack_cts : std_logic; + signal lvl2_trb_ack_system : std_logic; + signal lvl2_trb_ack_cts_saved : std_logic; + signal lvl2_trb_ack_system_saved : std_logic; begin ------------------------------------------------------------------------------ -- LVDS signals @@ -943,10 +958,10 @@ begin ACK_TO_VULOM => ADO_TTL(5), ERR_TO_VULOM => ADO_TTL(6), API_DATA => open, - API_RUN_OUT => apl_run_out_i, + API_RUN_OUT => lvl1_busy_i,--apl_run_out_i, API_SHORT_TRANSFER => open, - API_DTYPE => open, - API_SEND => open,--apl_send_in_i, + API_DTYPE => lvl1_trigger_code_i, + API_SEND => apl_send_in_i, API_WRITE_IN => open, API_TARGET_ADDRESS => open, API_SEQNR_OUT => apl_seqnr_out_i,--x"00", @@ -968,9 +983,9 @@ begin START_READOUT => start_readout_i, LVL1_TRANSFER_BUSY => lvl1_busy_i ); - ADO_TTL(3 downto 2) <= (others => 'Z'); - ADO_TTL(4) <= lvl1_busy_i; - ADO_TTL(15 downto 8) <= vulom_int_reg_00(7 downto 0); +-- ADO_TTL(3 downto 2) <= (others => 'Z'); +-- ADO_TTL(4) <= lvl1_busy_i; +-- ADO_TTL(15 downto 8) <= vulom_int_reg_00(7 downto 0); -------------------------------------------------------------------------- -- dtu interface -------------------------------------------------------------------------- @@ -1001,6 +1016,37 @@ begin -- ADO_TTL(15 downto 4) <= (others => 'Z'); -- ADO_TTL(2) <= '0'; -- ADO_TTL(3) <= '0'; +SAVE_LVL2_ACK_SYSTEM: process (CLK, external_reset_i, lvl2_trb_ack_system, lvl2_trb_ack_i) +begin -- process SAVE_LVL2_ACK_SYSTEM + if rising_edge(CLK) then + if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low) + lvl2_trb_ack_system_saved <= '0'; + elsif lvl2_trb_ack_system = '1' then + lvl2_trb_ack_system_saved <= '1'; + end if; + end if; +end process SAVE_LVL2_ACK_SYSTEM; +SAVE_LVL2_ACK_CTS : process (CLK, external_reset_i, lvl2_trb_ack_cts, lvl2_trb_ack_i) +begin -- process SAVE_LVL2_ACK_SYSTEM + if rising_edge(CLK) then + if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low) + lvl2_trb_ack_cts_saved <= '0'; + elsif lvl2_trb_ack_cts = '1' then + lvl2_trb_ack_cts_saved <= '1'; + end if; + end if; +end process SAVE_LVL2_ACK_CTS ; +SET_LVL2_ACK: process (CLK, external_reset_i,lvl2_trb_ack_cts_saved,lvl2_trb_ack_system_saved, lvl2_trb_ack_i) +begin + if rising_edge(CLK) then + if external_reset_i = '1' or lvl2_trb_ack_i = '1' then + lvl2_trb_ack_i <= '0'; + elsif lvl2_trb_ack_cts_saved='1' and lvl2_trb_ack_system_saved ='1' then + lvl2_trb_ack_i <= '1'; + + end if; + end if; +end process SET_LVL2_ACK; DTU_INT: dtu_interface port map ( @@ -1023,14 +1069,136 @@ begin LVL2_TRIGGER => lvl2_trigger_i, LVL2_CODE => lvl2_code_i, LVL2_TAG => lvl2_tag_i, - LVL2_BUSY => '0', + LVL2_BUSY => lvl2_busy_i, LVL2_TRB_ACK => lvl2_trb_ack_i, DTU_DEBUG_00 => dtu_debug_00_i); - ADO_TTL(15 downto 10) <= (others => 'Z'); - -------------------------------------------------------------------------- - -- no api - -------------------------------------------------------------------------- - + ADO_TTL(15 downto 10) <= (others => 'Z'); + -------------------------------------------------------------------------- + -- no api + -------------------------------------------------------------------------- + TLK_TX_ER <= '0'; + SFP_TX_DIS <= fpga_register_06_i(15); + TLK_LOOPEN <= '0'; + TLK_LCKREFN <= '1'; + TLK_ENABLE <= '1'; + TLK_PRBSEN <= '0'; + TLK_RX_CLK_BUFR: BUFR + port map( + CE => '1', + CLR => '0', + I => TLK_RX_CLK, + O => tlk_rx_clk_r + ); + TLK_CLK_BUFR: BUFR + port map( + CE => '1', + CLR => '0', + I => TLK_CLK, + O => tlk_clk_r + ); + SAVE_LVL1_TRIGGER: process (tlk_rx_clk_r, external_reset_i, apl_send_in_i) + begin -- process SAVE_LVL1_TRIGGER + if rising_edge(tlk_rx_clk_r) then + if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL1_B then + lvl1_trigger_saved <= '0'; + elsif apl_send_in_i ='1' then + lvl1_trigger_saved <= '1'; + end if; + end if; + end process SAVE_LVL1_TRIGGER; + SAVE_LVL2_TRIGGER: process (tlk_rx_clk_r, external_reset_i,lvl2_trigger_i) + begin -- process SAVE_LVL1_TRIGGER + if rising_edge(tlk_rx_clk_r) then + if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL2_B then + lvl2_trigger_saved <= '0'; + elsif lvl2_trigger_i ='1' then + lvl2_trigger_saved <= '1'; + end if; + end if; + end process SAVE_LVL2_TRIGGER; + SEND_LVL1_AND_LVL2_TRIGG_CLK : process (tlk_clk_r,external_reset_i) + begin + if rising_edge(tlk_clk_r) then + if external_reset_i= '1' then + current_state_send_lvl1_and_lvl2_trigg <= IDLE; + else + current_state_send_lvl1_and_lvl2_trigg <= next_state_send_lvl1_and_lvl2_trigg; + end if; + end if; + end process SEND_LVL1_AND_LVL2_TRIGG_CLK; + SEND_LVL1_AND_LVL2_TRIGG_FSM: process (tlk_clk_r,lvl1_trigger_saved, lvl2_trigger_saved) + begin -- process SEND_LVL1_AND_LVL2_TRIGG_FSM + case current_state_send_lvl1_and_lvl2_trigg is + when IDLE => + TLK_TX_EN <= '0'; + TLK_TXD <= x"1000"; + if lvl1_trigger_saved = '1' then + next_state_send_lvl1_and_lvl2_trigg <= LVL1_A; + elsif lvl1_trigger_saved = '1' and lvl2_trigger_saved = '1' then + next_state_send_lvl1_and_lvl2_trigg <= LVL1_A; + elsif lvl2_trigger_saved = '1' then + next_state_send_lvl1_and_lvl2_trigg <= LVL2_A; + else + next_state_send_lvl1_and_lvl2_trigg <= IDLE; + end if; + when LVL1_A => + TLK_TX_EN <= '1'; + TLK_TXD <= x"1" & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8); + next_state_send_lvl1_and_lvl2_trigg <= LVL1_B; + when LVL1_B => + TLK_TX_EN <= '1'; + TLK_TXD <= x"1" & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8); + next_state_send_lvl1_and_lvl2_trigg <= LVL1_C; + when LVL1_C => + TLK_TX_EN <= '1'; + TLK_TXD <= x"1" & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8); + next_state_send_lvl1_and_lvl2_trigg <= IDLE; + when LVL2_A => + TLK_TX_EN <= '1'; + TLK_TXD <= x"2" & lvl2_code_i & lvl2_trigger_tag_i; + next_state_send_lvl1_and_lvl2_trigg <= LVL2_B; + when LVL2_B => + TLK_TX_EN <= '1'; + TLK_TXD <= x"2" & lvl2_code_i & lvl2_trigger_tag_i; + next_state_send_lvl1_and_lvl2_trigg <= LVL2_C; + when LVL2_C => + TLK_TX_EN <= '1'; + TLK_TXD <= x"2" & lvl2_code_i & lvl2_trigger_tag_i; + next_state_send_lvl1_and_lvl2_trigg <= IDLE; + when others => + TLK_TX_EN <= '0'; + TLK_TXD <= x"1000"; + next_state_send_lvl1_and_lvl2_trigg <= IDLE; + end case; + end process SEND_LVL1_AND_LVL2_TRIGG_FSM; + CHECK_LVL1_BUSY: process (tlk_rx_clk_r, external_reset_i) + begin + if rising_edge(tlk_rx_clk_r) then + if external_reset_i = '1' or (TLK_RX_DV = '1' and TLK_RXD(15 downto 12) = x"1") then + lvl1_system_busy <= '0'; + elsif lvl1_trigger_saved = '1' then + lvl1_system_busy <= '1'; + end if; + end if; + end process CHECK_LVL1_BUSY; + lvl1_busy_i <= lvl1_system_busy or lvl1_cts_busy; + CHECK_LVL2_BUSY: process (tlk_rx_clk_r, external_reset_i) + begin + if rising_edge(tlk_rx_clk_r) then + if external_reset_i = '1' or (TLK_RX_DV = '1' and TLK_RXD(15 downto 12) = x"2") then + lvl2_busy_i <= '0'; + elsif lvl2_trigger_saved = '1' then + lvl2_busy_i <= '1'; + end if; + end if; + end process CHECK_LVL2_BUSY; + not_lvl2_busy_i <= not lvl2_busy_i; + ACK_LVL2_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => not_lvl2_busy_i, + pulse => lvl2_trb_ack_system); -------------------------------------------------------------------------- -- event from cts to etrax -------------------------------------------------------------------------- @@ -1056,10 +1224,10 @@ begin DATA_OUT => data_out_i, DATA_VALID => data_valid_i, ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, - LVL1_BUSY => lvl1_busy_i, + LVL1_BUSY => lvl1_cts_busy,--lvl1_busy_i, LVL2_START => lvl2_trigger_i, - LVL2_CODE => lvl2_trigger_code_i(3), - LVL2_TRB_ACK => lvl2_trb_ack_i, + LVL2_CODE => '0',--lvl2_trigger_code_i(3), + LVL2_TRB_ACK => lvl2_trb_ack_cts, CTS_ETRAX_REGISTER_00 => cts_etrax_register_00_i, CTS_ETRAX_REGISTER_01 => cts_etrax_register_01_i, CTS_ETRAX_REGISTER_02 => cts_etrax_register_02_i, @@ -1165,7 +1333,7 @@ begin FPGA_REGISTER_0d => x"00000000",--fpga_register_0d_i, FPGA_REGISTER_0e => fpga_register_0e_i,--fpga_register_0d_i, EXTERNAL_RESET => external_reset, - LVL2_VALID => '0' + LVL2_VALID => lvl2_code_i(3)--lvl2_trigger_code_i(3) ); fpga_register_01_i <= vulom_int_reg_00; fpga_register_02_i <= '0' & "000" & "00"& TLK_RX_DV & TLK_RX_ER & TLK_RXD & x"00";-- diff --git a/trb_cts/fpga_to_etrax_data_flow.vhd b/trb_cts/fpga_to_etrax_data_flow.vhd index 7e230c4..706cafa 100644 --- a/trb_cts/fpga_to_etrax_data_flow.vhd +++ b/trb_cts/fpga_to_etrax_data_flow.vhd @@ -381,8 +381,8 @@ begin lvl2_debug (2 downto 0) <= "001"; lvl1_fifo_rd_en_fsm <= '0'; tdc_data_valid_i_fsm <= '0'; - if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then --- if LVL2_START = '1' then +-- if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then + if LVL2_START = '1' then LVL2_START_fsm_nextstate <= READOUT_WORD1; else LVL2_START_fsm_nextstate <= IDLE; @@ -527,7 +527,7 @@ begin if RESET = '1' then LVL1_BUSY <= '0'; else - LVL1_BUSY <= lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i; --here + LVL1_BUSY <= lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i; --here end if; end if; end process REGITERING_SIGNALS; diff --git a/trb_cts/vulom_interface.vhd b/trb_cts/vulom_interface.vhd index 736609a..d03375c 100644 --- a/trb_cts/vulom_interface.vhd +++ b/trb_cts/vulom_interface.vhd @@ -176,7 +176,8 @@ begin seq_ok <= '0'; ack <= '0'; err <= '0'; - if not_transfer_busy_pulse = '1' then +-- if not_transfer_busy_pulse = '1' then + if VULOM_TO_API_current = IDLE then CHECK_next <= SEND_ACK_2; else CHECK_next <= SEND_ACK_1; @@ -354,16 +355,16 @@ begin -- if trigger_counter /= trigger_tag then -- VULOM_TO_API_next <= TRIGGER_MISSMATCH; -- else - VULOM_TO_API_next <= WAIT_FOR_END_BUSY; + VULOM_TO_API_next <= WAIT_FOR_END_BUSY; -- end if; when WAIT_FOR_END_BUSY => vulom_interface_debug(3 downto 0) <= x"6"; busy_i <= '1'; API_SEND <= '0'; --api --- if api_ready_pulse = '1' then + if api_ready_pulse = '1' then --just cts - if not_transfer_busy_pulse = '1' then +-- if not_transfer_busy_pulse = '1' then VULOM_TO_API_next <= IDLE; else VULOM_TO_API_next <= WAIT_FOR_END_BUSY; -- 2.43.0