From 6d38759e08a0eb15dff68d18137d2257ad037f0f Mon Sep 17 00:00:00 2001 From: Michael Wiebusch Date: Thu, 20 Jun 2013 17:53:21 +0200 Subject: [PATCH] unstable stuff for playing around --- xml_spielwiese/MIMOSA26_JTAG_SPEC.xml | 787 ++++++++++++++++++++++++ xml_spielwiese/cgitest.pl | 240 ++++++++ xml_spielwiese/chain01sensor01_orig.ini | 31 + xml_spielwiese/mergexml.pl | 18 + xml_spielwiese/query.pl | 26 + xml_spielwiese/settings.xml | 10 + xml_spielwiese/styles.css | 43 ++ xml_spielwiese/update_specfile.sh | 8 + xml_spielwiese/xml2ini.pl | 98 +++ 9 files changed, 1261 insertions(+) create mode 100644 xml_spielwiese/MIMOSA26_JTAG_SPEC.xml create mode 100755 xml_spielwiese/cgitest.pl create mode 100644 xml_spielwiese/chain01sensor01_orig.ini create mode 100755 xml_spielwiese/mergexml.pl create mode 100755 xml_spielwiese/query.pl create mode 100644 xml_spielwiese/settings.xml create mode 100644 xml_spielwiese/styles.css create mode 100755 xml_spielwiese/update_specfile.sh create mode 100755 xml_spielwiese/xml2ini.pl diff --git a/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml b/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml new file mode 100644 index 0000000..2fd9ee1 --- /dev/null +++ b/xml_spielwiese/MIMOSA26_JTAG_SPEC.xml @@ -0,0 +1,787 @@ + + + + +The CONTROL_PIX_REG registers are 40 bits large; they allow setting parameters of the readout controller. These +registers are reserved for sensor's debugging by the IPHC/IRFU group. A end user has to respect to the default values. +\t + + Reserved, Not Used + + + Selection bit of Test1Pad + + + Selection bit of Test2Pad + + + Row number of the frame. It depends of readout mode. When the En_HalfMatrx mode is active, the value is 0x013F otherwise 0x023F. When the En_LineMarker mode is active, add two rows at the end of matrix. + + + Selection parameter of row for digital marker (MK_Test_D) + + + Selection parameter of row for analogue marker (MK_Test_A) + + + + +The CONTROL_SUZE_REG registers are 48 bits large; they allow setting parameters of the readout controller for SUZE. +We suggest an end user to only use default values except for data stream output parameters +\t + + Reserved, Not Used + + + Selection bit of Test4Pad + + + Selection bit of Test3Pad + + + Enable mode scan test discriminators, all matrix + + + Enable mode scan test + + + Enable mode scan test for multiplexer of SUZE + + + Enable mode scan test discriminators + + + Row number of the frame. It depends of readout mode. When the En_HalfMatrx mode is active, the value is 0x013F otherwise 0x023F. When the En_LineMarker mode is active, add two rows at the end of matrix. + + + Selection parameter of row for digital + + + Determines the data stream on the channel or in one channel + + + Determines the clock rate of the outputs channel or in one channel + + + Authorizes the initialization test of the FIFO or not. High level active. + + + Discriminator switched ON/Off + + + Cf. cfg multiplexors configuration + + + Idem + + + Idem + + + Idem + + + + +(a.k.a. BIAS_DAC) +The BIAS_DAC register is 152 bit wide; it sets simultaneously the 19 DAC registers. +As show bellow these 8-bit DACs set voltage and current bias. After reset the register is set to 0, a value which fixes the +minimum power consumption of the circuit. The current values of the DACs are read while the new values are downloaded +during the access to the register. An image of the value of each DAC can be measured on its corresponding test pad. +\t + + External circuit monitoring Vtest + + + Pixel source follower bias IPIX + + + Discriminator bias 2 IDIS2 + + + Discriminator bias 1 IDIS1 + + + Discriminator Reference 2 VDREF2 + + + Discriminator Reference 1 (Bank A) VDREF1A + + + Discriminator Reference 1 (Bank B) VDREF1B + + + Discriminator Reference 1 (Bank C) VDREF1C + + + Discriminator Reference 1 (Bank D) VDREF1D + + + Analogue Buffer bias IAnaBUF + + + Test Level, emulates a pixel output + + + IDEM + + + LVDS PAD bias + + + LVDS PAD bias + + + Discriminator bias 2 (mode low consp.) + + + Discriminator bias 1 (mode low consp.) + + + Ref&Tst Buffer bias + + + Discriminator Power Pulse bias + + + Discriminator Clamping bias + + + + +The DIS_DISCRI register is 1152 bits large. The purpose of this register is to disable the discriminator on a specific +column if it is noisy, by gating Latch signal and setting the output discriminator at 0. +The default value of the DIS_DISCRI register is 0; it means that all discriminators are activated. Setting a bit to 1 disables +the corresponding discriminator. In MIMOSA26, the DisableLatch<0> is on the left hand side while DisableLatch<1151> +is on the right hand side. +\t + + disables discriminators (whole columns) + + + + +The register called Header_Reg includes 4 registers of 16 bits as shown below. + +For both modes according to the register DUALCHANNEL the header and the trailer of each data frame can be +different. The following table shows the possible Header and the Trailer which ensure the unicity in the data frame. The +unicity is guaranteed without the Frame counter. +\t + + Synchronisation header for serial output0 + + + Synchronisation header for serial output1 + + + Synchronisation trailer serial output0 + + + Synchronisation trailer serial output1 + + + + +The LINEPAT0_REG register is 1152 bits large. The purpose of this register is to emulate discriminators outputs rows in +En_LineMarker and Pattern_Only modes. +When Pattern_Only is active, the values stored in the pixel matrix are ignored and the value of LINEPAT0_REG +is sent to the output. This is a test mode which emulates the (digital) pixel response with the contents programmed into the +LINEPAT0_REG register in order to verify the digital processing. The pattern is alternated with the contents of the +LINEPAT1_REG. +In the En_LineMarker mode, it adds two rows at the end of matrix for a readout chip and the LINEPATL0_REG +register is read to emulate the discriminators outputs of these two supplementary rows. +After the initialisation phase (reset), this register is preset to 0. + +In MIMOSA26, the LinePatL0Reg <0> is on the left hand side while LinePatL0Reg <1151> is on the right hand side. +\t + + Emulate discriminators rows + + + + +The LINEPAT1_REG register is 1152 bits large. The purpose of this register is to emulate discriminators outputs rows in +En_LineMarker and Pattern_Only modes. +When Pattern_Only is active, the values stored in the pixel matrix are ignored and the value of LINEPAT1_REG +is sent to the output. This is a test mode which emulates the (digital) pixel response with the contents programmed into the +LINEPAT0_REG register in order to verify the digital processing. The pattern is alternated with the contents of the +LINEPAT1_REG. +In the En_LineMarker mode, it adds two rows at the end of matrix for a readout chip and the LINEPATL1_REG +register is read to emulate the discriminators outputs of these two supplementary rows. + +In MIMOSA26, the LinePatL1Reg <0> is on the left hand side while LinePatL1Reg <1151> is on the right hand side. +With Line1_PAT_REG together these two signals will form the elements of the simulated frame given to SUZE part. +\t + + Emulate discriminators rows + + + + +The RO_MODE0 registers are 8 bits large; they allow the user to select specific digital mode of the chip. + +(1) The minimum wide of asynchronous external START signal is 500 ns, and this signal is active at high level. +(2) When En_ExtStart is disabled, it’s possible to generate internal START by accessing JTAG_Start bit. JTAG_Start +signal is realized by three JTAG access: First step, this bit is set to 0, second step it is set to 1, and at last it is set to 0. +\t + + Enable the internal injection of VTEST + + + Set the row shift register to 320 in place of 576 bits. + + + Disable LVDS and active clock CMOS. + + + Add two rows at the end of matrix for a chip Readout: The LINEPAT_REG register is selected to emulate discriminators outputs. For analogue outputs, the 2 Test Levels, VTEST1 and VTEST2 are selected which emulate a pixel output. + + + Select Marker signal or Readout Clock for digital and analogue data (MK_CLKA and MK_CLKD pads) + + + Test Mode: Select LINEPAT_REG to emulate discriminators outputs + + + Enable external START input synchronisation (1) + + + Enable Jtag START input synchronisation (2) + + + + +The RO_MODE1 registers are 8 bits large; they allow selecting specific analogue mode of the chip. +\t + + Reinitializes the frame counter to 0. + + + Enable analog output + + + Enable scan pixel mode + + + Disable the internal reference + + + Enable internal PLL + + + Enable the Power pulse Amplifier + + + Enable the discri power pulse mode + + + Enable the discri. test mode + + + + +The SEQUENCER_PIX_REG registers are 128 bits large; this register contains all parameters to generate readout pixel +and discriminator sequence. +\t + + Connect pixel output to common column + + + Set reference voltage for diode + + + Set reference voltage for clamping + + + Sample after clamping + + + Sample before clamping + + + Latch state of the discriminator + + + Activate power supply for pixel + + + + +The SEQUENCER_SUZE_REG registers are 160 bits large; this register contains all parameters to generate readout zero +suppression (SUZE) sequence. +\t + + Sample signal for multiplexer after Priority look ahead + + + Synchronization signal every line for Priority Look Ahead + + + Synchronization signal every line for memory management + + + Synchronization signal every line for Priority Look Ahead + + + Synchronization signal 6 times every line for memory management shifted of 5 ns compared with CkReadpix + + + Synchronization signal 6 times every line for memory management + + + Synchronization signal every line for memory management + + + Synchronization signal every line for all SUZE part + + + Reset signal 6 times every line for Priority Look Ahead + + + Reset frame signal for memory management + + + diff --git a/xml_spielwiese/cgitest.pl b/xml_spielwiese/cgitest.pl new file mode 100755 index 0000000..20cd811 --- /dev/null +++ b/xml_spielwiese/cgitest.pl @@ -0,0 +1,240 @@ +#!/usr/bin/perl -w +print "Content-type: text/html\n\n"; + +my $me="cgitest.pl"; + +use strict; +use warnings; +use XML::LibXML; +use POSIX; + + + +sub initPage { + +print < + +CGI Testrange + +EOF +printJavaScripts(); +print < + + +
+ +
+
+ +
+ + + + + + + +EOF + +} + + + +my %cgiHash = &read_input; + + +if (!keys %cgiHash) { # if script is called without arguments: initialize the html structure + initPage(); + exit; +} + + +my $parser = XML::LibXML->new(); +my $specfile = "./MIMOSA26_JTAG_SPEC.xml"; + + +my $setfile = "./settings.xml"; + + + + + + +if ($cgiHash{'print'} eq 'spectree') { +print_registers($specfile); +} + + +if ($cgiHash{'print'} eq 'settree') { +print_registers($setfile); +} + + + + + + + + +#################### SUBLAND ###################### + + +sub print_registers { +my $xmlfile = $_[0]; +my $xmltree = $parser->parse_file($xmlfile); +my @registers = $xmltree->findnodes("/MAPS/register"); +print ""; +for my $register ( @registers ){ + + my $registerName = $register->findvalue("./\@name"); + my $registerId = $register->findvalue("./\@id"); + my $registerSize = $register->findvalue("./\@size"); + + my $flistid = $xmlfile.$registerName; + + print ""; + + print <+ +EOF + print ""; + #print ""; + + + print ""; + #print ""; + + print ''; + print ''; + print '"; + print ""; +} +print "
$registerName$registerId
'; + print_fields($xmlfile,$register); + print "
"; +} + +sub print_fields { + + my $register = $_[1]; + my $xmlfile = $_[0]; + my $registerName = $register->findvalue("./\@name"); + my @fields = $register->findnodes("./field"); + print ""; + for my $field (@fields){ + my $fieldName = $field->findvalue("./\@name"); + my $readOnlyFlag = 0; + my $fieldValue = $field->findvalue("./\@value"); + my $fieldId = $xmlfile."//".$registerName."/".$fieldName; + if ($fieldValue eq "") { + $fieldValue = $field->findvalue("./\@defaultValue"); + $readOnlyFlag=1; + } + + print ""; + print ""; + print ""; + if ($readOnlyFlag){ + print <$fieldValue +EOF + } else { + print < + + +EOF + #print ''; + } + print ""; + } + print "
$fieldName = '; + #print < +#EOF + print '
"; + +} + + +sub read_input +{ + my $buffer; my @pairs; my $pair; my $name; my $value;my %FORM; + # Read in text + $ENV{'REQUEST_METHOD'} =~ tr/a-z/A-Z/; + if ($ENV{'REQUEST_METHOD'} eq "POST") + { + read(STDIN, $buffer, $ENV{'CONTENT_LENGTH'}); + } else + { + $buffer = $ENV{'QUERY_STRING'}; + } + # Split information into name/value pairs + @pairs = split(/&/, $buffer); + foreach $pair (@pairs) + { + ($name, $value) = split(/=/, $pair); + $value =~ tr/+/ /; + $value =~ s/%(..)/pack("C", hex($1))/eg; + $FORM{$name} = $value; + } + %FORM; +} + + + +sub printJavaScripts { + + +####### javascript function land ################ + + +print < +function toggleVis(elementId) { +if( document.getElementById(elementId).style.visibility == "visible") { + document.getElementById(elementId).style.visibility = "collapse"; +} else { + document.getElementById(elementId).style.visibility = "visible" ; +} +} +function showElement(elementId) { + document.getElementById(elementId).style.visibility = "visible" ; +} +function hideElement(elementId) { + document.getElementById(elementId).style.visibility = "hidden" ; +} +function collapseElement(elementId) { + document.getElementById(elementId).style.visibility = "collapse" ; +} + + + + +EOF + +} diff --git a/xml_spielwiese/chain01sensor01_orig.ini b/xml_spielwiese/chain01sensor01_orig.ini new file mode 100644 index 0000000..936179f --- /dev/null +++ b/xml_spielwiese/chain01sensor01_orig.ini @@ -0,0 +1,31 @@ +[General] +IRLEN=5 +BYPASSREG=1F +[Data] +; format: Key= Register number ( arbitrary, sorted by), Value=IR( hexadecimal, lower bits are used)","length(bits,decimal)","DR(hexadecimal) +; configuration taken from CCMOS_SCTRL_MIMOSA26_JTAG_config_files.org/daq_test_2x80Mhz_1_chip_hit_fe55.TXT +;00=0F,152,006432020276FFAAFFFF32768020280A0A0A0A64 ; BIAS_DAC assumed 19*8bit +00=0F,152,00643220204D0000000032768020280A0A0A0A64 ; BIAS_DAC assumed 19*8bit +;00=0F,152,0064322020731005100532768020280A0A0A0A64 ; BIAS_DAC assumed 19*8bit ==> resulted in almost constant 1 +01=1E,8,00000002 ; RO_MODE0"cmS50r +;1=1E,8,00000012 ; RO_MODE0, En_LineMarker +;1=1E,8,00000006 ; RO_MODE0, Pattern_Only=1 +02=1D,8,00000000 ; RO_MODE1, basic configuration value +03=13,40,0000000023F00000; CTRL_PIX_REG, basic configuration value +04=12,128,7FFF004001C03C00001C60007FFFFFFF ; SEQUENCER_PIX_REG, basic configuration value +05=16,64,5555555580018001 ; HEADER_TRAILER_REG, assumed 4*16bit +;06=17,48,00000048FC01E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=0, Test_after_mux = 0, ScanLineTst=0x001 (10bit) +;06=17,48,000000C90401E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, En_scan=1, entestdatadisc = 0, En_auto_scan_discri=1, Test_after_mux = 0, ScanLineTst=0x001 (10bit) +06=17,48,00000008FC00E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout +;06=17,48,000000090400E000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, RowLastSuze incremented by two +;06=17,48,00000008FC00F000 ; CTRL_SUZE_REG: dualchannelout, clkrateout, disckgmodgate=1 +07=15,160,055530001000055582AA0555E001600005552000 ; SEQUENCER_SUZE_REG, basic configuration value +08=11,1152,055555555000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; DIS_DISCRI +09=10,1152,000003333000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033310000 ; LINE0_PATTERN_REG +10=14,1152,1646464641111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111116F6F6FFF1 ; LINE1_PATTERN_REG +;11=18,144,7ABD1E6F278BC01208038180a0401808035C ; CTRL_8B10B_REG0 assumed 16*9bit: 15C, 001, 002, 003, 004, 005, 006, 007, 008, 009, 0F0, 0F1, 0F2, 0F3, 0F4, 0F5 +;12=19,312,0080d5400d5755d5755d5755d5755d5755d575500255061221200800169223980f60a06882a06330 ; CTRL_8B10B_REG1, assumed 312*1bit + + + + diff --git a/xml_spielwiese/mergexml.pl b/xml_spielwiese/mergexml.pl new file mode 100755 index 0000000..0f6fbb2 --- /dev/null +++ b/xml_spielwiese/mergexml.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl -w + +use strict; +use warnings; +use XML::LibXML; + +my $parser = XML::LibXML->new(); + +my $doc1 = $ARGV[0]; +my $doc2 = $ARGV[1]; + +my $xml1 = $parser->parse_file($doc1); +my $xml2 = $parser->parse_file($doc2); + +my $new_xml = XML::LibXML::Element->new( 'XML' ); +$new_xml->appendWellBalancedChunk( $xml1->documentElement()->toString() ); +$new_xml->appendWellBalancedChunk( $xml2->documentElement()->toString() ); +print $new_xml->toString(1); diff --git a/xml_spielwiese/query.pl b/xml_spielwiese/query.pl new file mode 100755 index 0000000..98e438e --- /dev/null +++ b/xml_spielwiese/query.pl @@ -0,0 +1,26 @@ +#!/usr/bin/perl -w + +use strict; +use warnings; +use XML::LibXML; + +my $parser = XML::LibXML->new(); + +my $doc1 = $ARGV[0]; + +my $xml1 = $parser->parse_file($doc1); + + +my $query = "//register/field[\@name='NU']"; + +my @nodes = $xml1->findnodes($query); + +for my $node ( @nodes) { +my $parentnode = $node->parentNode; +my @attributelist = $node->attributes(); +print $parentnode->nodeName(),"->",$node->nodeName(), ": ", $node->textContent(), "\n"; +for my $attribute ( @attributelist) { + print $attribute->name."\t".$attribute->value."\n"; +} + +} diff --git a/xml_spielwiese/settings.xml b/xml_spielwiese/settings.xml new file mode 100644 index 0000000..58b773a --- /dev/null +++ b/xml_spielwiese/settings.xml @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/xml_spielwiese/styles.css b/xml_spielwiese/styles.css new file mode 100644 index 0000000..04e2971 --- /dev/null +++ b/xml_spielwiese/styles.css @@ -0,0 +1,43 @@ + +body { + color: black; background-color: white; + font-family: Helvetica,Arial,sans-serif; + font-size: 12; + margin: 0; padding: 1em; +} + +table { + font-size: 12; +} + +#roterBereich { + position:absolute; + top:130px; + left:30px; + width:320px; + padding:10px; + margin:0px; + border:2px solid #EE0000; +} +#blauerBereich { + position:absolute; + top:130px; + left:400px; + width:320px; + padding:10px; + margin:0px; + border:2px solid #0000EE; +} + +input[type="text"] +{ + font-size:12px; + height:20px; + width:120px; +} + +input[type="button"] +{ + font-size:12px; + height:20px; +} diff --git a/xml_spielwiese/update_specfile.sh b/xml_spielwiese/update_specfile.sh new file mode 100755 index 0000000..0f23d0d --- /dev/null +++ b/xml_spielwiese/update_specfile.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +here=$(pwd) + +cd ../MIMOSA26_Registers +./GenerateSpecFile.sh | tee "$here/MIMOSA26_JTAG_SPEC.xml" + +cd "$here" diff --git a/xml_spielwiese/xml2ini.pl b/xml_spielwiese/xml2ini.pl new file mode 100755 index 0000000..d92eb49 --- /dev/null +++ b/xml_spielwiese/xml2ini.pl @@ -0,0 +1,98 @@ +#!/usr/bin/perl -w + +use strict; +use warnings; +use XML::LibXML; +use POSIX; + +my $parser = XML::LibXML->new(); + +my $specfile = "./MIMOSA26_JTAG_SPEC.xml"; +my $spectree = $parser->parse_file($specfile); + +my $setfile = "./settings.xml"; +my $settree = $parser->parse_file($setfile); + +my @registers = $spectree->findnodes("/MAPS/register"); + + + +my $specMapsType = $spectree->findvalue("/MAPS/\@type"); +my $setMapsType = $settree->findvalue("/MAPS/\@type"); + +# check if specification file and settings file are compatible +if ($specMapsType ne $setMapsType) { + die "MAPS type mismatch between settings and specification file!\n"; +} + + + + + +my $registerCounter = 0; +for my $register ( @registers){ + + register2hex($register); + $registerCounter++; +} + +#print $new_xml->toString(1); + + +sub register2hex { +# TODO +# try catch blocks? +# good work so far + my $register = $_[0]; + my $registerName = $register->findvalue("./\@name"); + my $registerId = $register->findvalue("./\@id"); + my $registerSize = $register->findvalue("./\@size"); + my $stringSize = ceil($registerSize/32)*8; + + + my $result = 0; + + my @fields = $register->findnodes("./field"); + + for my $field (@fields){ + my $name = $field->findvalue("./\@name"); + my $start = $field->findvalue("./\@start"); + my $end = $field->findvalue("./\@end"); + my $size = $field->findvalue("./\@size"); + + # check for setting in the settings file + my $value = $settree->findvalue("/MAPS/register[\@name='".$registerName."']/field[\@name='".$name."']/\@value"); + if ($value ne "") { + #print "Setting found! $value\n"; + } else { # if nothing found, then use the default value from the specfile + $value = $field->findvalue("./\@defaultValue"); + #print "Use default setting: $value\n"; + } + + $value = any2dec($value); # convert any numeric code to decimal + my $calcedsize = $end-$start+1; + if ( $calcedsize != $size) { + die "start/stop/size mismatch in register $registerName : field $name\n"; + } + #print "$name: $start -> $end = $calcedsize/$size\n"; + $result = $result | ($value<<$start); + #print "value: $value\n"; + } + my $resultstring = sprintf("%0".$stringSize."X",$result); + print ";$registerName\n"; + printf ("%02d=%s,%d,%s\n",$registerCounter,$registerId,$registerSize,$resultstring); + +} + + +sub any2dec { # converts numeric expressions 0x, 0b or decimal to decimal + + my $argument = $_[0]; + #print "any2dec input argument $argument\n"; + + if ( $argument =~ m/0[bxBX]/) { + return oct $argument; + } else { + return $argument; + } +} -- 2.43.0