From 6e04d8836706864bbf1ca7bf2faf8c59ae5b1750 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 29 Sep 2017 10:53:37 +0200 Subject: [PATCH] Remove wrong constraint files --- 32PinAddOn/unimportant_lines_constraints.lpf | 4 --- ADA_Addon/par.p2t | 21 ++++++++++++++ ADA_Addon/unimportant_lines_constraints.lpf | 4 --- base/basic_constraints.lpf | 29 ++------------------ cbmtof/unimportant_lines_constraints.lpf | 5 ---- gpin/unimportant_lines_constraints.lpf | 4 --- hadesstart/unimportant_lines_constraints.lpf | 4 --- scripts/compile.pl | 4 +-- wasa/unimportant_lines_constraints.lpf | 4 --- 9 files changed, 25 insertions(+), 54 deletions(-) delete mode 100644 32PinAddOn/unimportant_lines_constraints.lpf create mode 100644 ADA_Addon/par.p2t delete mode 100644 ADA_Addon/unimportant_lines_constraints.lpf delete mode 100644 cbmtof/unimportant_lines_constraints.lpf delete mode 100644 gpin/unimportant_lines_constraints.lpf delete mode 100644 hadesstart/unimportant_lines_constraints.lpf delete mode 100644 wasa/unimportant_lines_constraints.lpf diff --git a/32PinAddOn/unimportant_lines_constraints.lpf b/32PinAddOn/unimportant_lines_constraints.lpf deleted file mode 100644 index 0c65598..0000000 --- a/32PinAddOn/unimportant_lines_constraints.lpf +++ /dev/null @@ -1,4 +0,0 @@ -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; - -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x; diff --git a/ADA_Addon/par.p2t b/ADA_Addon/par.p2t new file mode 100644 index 0000000..246acd7 --- /dev/null +++ b/ADA_Addon/par.p2t @@ -0,0 +1,21 @@ +#-w +#-i 15 +#-l 5 +#-y +#-s 12 +#-t 6 +#-c 1 +#-e 2 +##-g guidefile.ncd +##-m nodelist.txt +#-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 + +-w +-l 5 +-i 6 +-n 1 +-t 5 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=ON:parHoldLimit=10000 diff --git a/ADA_Addon/unimportant_lines_constraints.lpf b/ADA_Addon/unimportant_lines_constraints.lpf deleted file mode 100644 index 0c65598..0000000 --- a/ADA_Addon/unimportant_lines_constraints.lpf +++ /dev/null @@ -1,4 +0,0 @@ -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; - -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x; diff --git a/base/basic_constraints.lpf b/base/basic_constraints.lpf index f69e819..c079c8f 100644 --- a/base/basic_constraints.lpf +++ b/base/basic_constraints.lpf @@ -7,39 +7,14 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# -SYSCONFIG MCCLK_FREQ = 20; - -FREQUENCY PORT CLK_CORE_PCLK 240 MHz; -FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz; -FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz; - -FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz; -FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz; -FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125 MHz; - -FREQUENCY PORT CLK_EXT_PCLK 200 MHz; -FREQUENCY PORT CLK_EXT_PLL_LEFT 200 MHz; -FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz; - - -MULTICYCLE TO CELL "THE_MEDIA_INT*/sci*" 20 ns; -MULTICYCLE FROM CELL "THE_MEDIA_INT*/sci*" 20 ns; -MULTICYCLE TO CELL "THE_MEDIA_INT*/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "THE_MEDIA_INT*/sci_write_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_INT*/sci_write_i"; -BLOCK PATH TO CLKNET "THE_MEDIA_INT*/sci_read_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_INT*/sci_read_i"; - -FREQUENCY NET "THE_MEDIA_INT*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps -FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps - BLOCK PATH TO PORT "LED*"; BLOCK PATH TO PORT "SFP*"; BLOCK PATH FROM PORT "SFP*"; BLOCK PATH TO PORT "PROGRAMN"; BLOCK PATH TO PORT "TEMPSENS"; BLOCK PATH FROM PORT "TEMPSENS"; -BLOCK PATH TO PORT "TESTLINE"; +BLOCK PATH TO PORT "TEST_LINE"; PROHIBIT PRIMARY NET "ENPIRION_CLOCK_c" ; PROHIBIT SECONDARY NET "ENPIRION_CLOCK_c" ; + diff --git a/cbmtof/unimportant_lines_constraints.lpf b/cbmtof/unimportant_lines_constraints.lpf deleted file mode 100644 index 614d7a0..0000000 --- a/cbmtof/unimportant_lines_constraints.lpf +++ /dev/null @@ -1,5 +0,0 @@ -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x; -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x; - -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_osc TO CLKNET clk_100_osc 5x; -# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_EXT_c 2x; diff --git a/gpin/unimportant_lines_constraints.lpf b/gpin/unimportant_lines_constraints.lpf deleted file mode 100644 index 0c65598..0000000 --- a/gpin/unimportant_lines_constraints.lpf +++ /dev/null @@ -1,4 +0,0 @@ -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; - -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x; diff --git a/hadesstart/unimportant_lines_constraints.lpf b/hadesstart/unimportant_lines_constraints.lpf deleted file mode 100644 index 0c65598..0000000 --- a/hadesstart/unimportant_lines_constraints.lpf +++ /dev/null @@ -1,4 +0,0 @@ -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; - -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x; diff --git a/scripts/compile.pl b/scripts/compile.pl index 227b27e..e2f605b 100755 --- a/scripts/compile.pl +++ b/scripts/compile.pl @@ -136,12 +136,12 @@ if ($con==1 || $all==1) { system("cat tdc_release/dirich_tdc_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("ln -s $cwd/../../tdc/base/cores/ecp5/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo"); } else { - system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +# system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat tdc_release/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); system("cat tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); system("ln -s $cwd/../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo"); } - system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +# system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); #edit the lpf file according to tdc settings system("unlink $WORKDIR/compile_tdc.pl"); diff --git a/wasa/unimportant_lines_constraints.lpf b/wasa/unimportant_lines_constraints.lpf deleted file mode 100644 index 69a8e5b..0000000 --- a/wasa/unimportant_lines_constraints.lpf +++ /dev/null @@ -1,4 +0,0 @@ -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x; -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x; - -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_internal TO CLKNET clk_100_internal 5x; -- 2.43.0