From 6e0e04820b00295cdb23738539297c62b57df8e5 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 26 May 2009 16:33:00 +0000 Subject: [PATCH] minor fixes --- trb_net16_ibuf.vhd | 6 ++-- trb_net16_obuf_nodata.vhd | 4 +-- trb_net16_regIO.vhd | 74 +++++++++++++++------------------------ trb_net_std.vhd | 2 +- 4 files changed, 35 insertions(+), 51 deletions(-) diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 9263c96..fe0a229 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -28,16 +28,16 @@ entity trb_net16_ibuf is -- Media direction port MED_DATAREADY_IN : in std_logic; MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); MED_READ_OUT : out std_logic; MED_ERROR_IN : in std_logic_vector (2 downto 0); -- Internal direction port INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_INIT_DATAREADY_OUT : out std_logic; INT_INIT_READ_IN : in std_logic; INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); INT_REPLY_DATAREADY_OUT : out std_logic; INT_REPLY_READ_IN : in std_logic; INT_ERROR_OUT : out std_logic_vector (2 downto 0); diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd index a9dccad..318efe6 100644 --- a/trb_net16_obuf_nodata.vhd +++ b/trb_net16_obuf_nodata.vhd @@ -78,7 +78,6 @@ begin end if; buf_MED_DATAREADY_OUT <= '0'; - if (SEND_ACK_IN or reg_SEND_ACK_IN or reg_SEND_ACK_IN_2) = '1' then buf_MED_DATAREADY_OUT <= '1'; end if; @@ -89,8 +88,9 @@ begin if buf_MED_PACKET_NUM_OUT = c_F3 and MED_READ_IN = '1' then transfer_counter := c_H0; buf_MED_DATA_OUT(2 downto 0) <= TYPE_ACK; - buf_MED_DATAREADY_OUT <= '0'; + buf_MED_DATAREADY_OUT <= SEND_ACK_IN or reg_SEND_ACK_IN_2; end if; + buf_MED_PACKET_NUM_OUT <= transfer_counter; if buf_MED_PACKET_NUM_OUT = c_F3 and MED_READ_IN = '1' then diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index ca81170..235e546 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -768,8 +768,6 @@ begin elsif REGISTERS_OUT_write_enable(i) = '1' then tmp := saved_Reg_high & saved_Reg_low; buf_REGISTERS_OUT(j) <= tmp(j-i*c_REGIO_REG_WIDTH); --- elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"D0") then --- buf_REGISTERS_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REG_WIDTH); end if; end if; end process; @@ -780,52 +778,38 @@ begin end generate; end generate; - gen_cregout : for i in 0 to std_COMCTRLREG-1 generate - gen_cregoutff1 : for j in i*c_REGIO_REG_WIDTH to (i+1)*c_REGIO_REG_WIDTH-1 generate - process(CLK) - variable tmp : std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - begin - if rising_edge(CLK) then - if RESET = '1' then - buf_COMMON_CTRL_REG_OUT(j) <= '0'; - elsif COMMON_REGISTERS_OUT_write_enable(i) = '1' then - tmp := saved_Reg_high & saved_Reg_low; - buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*c_REGIO_REG_WIDTH); --- elsif EXT_REG_WRITE_IN = '1' and EXT_REG_ADDR_IN = (conv_std_logic_vector(i,8) or x"20") then --- buf_COMMON_CTRL_REG_OUT(j) <= EXT_REG_DATA_IN(j-i*c_REGIO_REG_WIDTH); - end if; + + gen_strobe_ctrl_regs : if std_COMCTRLREG >= 1 generate + process(CLK) + begin + if rising_edge(CLK) then + if COMMON_REGISTERS_OUT_write_enable(0) = '1' then + buf_COMMON_CTRL_REG_OUT(31 downto 0) <= saved_Reg_high & saved_Reg_low; + else + buf_COMMON_CTRL_REG_OUT(31 downto 0) <= (others => '0'); end if; - end process; - end generate; + end if; + end process; end generate; - --- ext_data_output : process(CLK) --- variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1; --- variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1; --- variable regnum_cSTAT : integer range 0 to std_COMSTATREG-1; --- variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1; --- begin --- regnum_STAT := conv_integer(EXT_REG_ADDR_IN(NUM_STAT_REGS-1 downto 0)); --- regnum_CTRL := conv_integer(EXT_REG_ADDR_IN(NUM_CTRL_REGS-1 downto 0)); --- regnum_cSTAT := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0)); --- regnum_cCTRL := conv_integer(EXT_REG_ADDR_IN(std_COMneededwidth-1 downto 0)); --- if rising_edge(CLK) then --- if RESET = '1' then --- EXT_REG_DATA_OUT <= (others => '0'); --- elsif EXT_REG_ADDR_IN(7 downto 6) = "01" then --- EXT_REG_DATA_OUT <= (others => '0'); --- elsif EXT_REG_ADDR_IN(7 downto 6) = "10" then --- EXT_REG_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+31 downto regnum_STAT*c_REGIO_REG_WIDTH); --- elsif EXT_REG_ADDR_IN(7 downto 6) = "11" then --- EXT_REG_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+31 downto regnum_CTRL*c_REGIO_REG_WIDTH); --- elsif EXT_REG_ADDR_IN(5) = '0' then --- EXT_REG_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+31 downto regnum_cSTAT*c_REGIO_REG_WIDTH); --- else --if EXT_CTRL_ADDR_IN(5) = '1' then --- EXT_REG_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+31 downto regnum_cCTRL*c_REGIO_REG_WIDTH); --- end if; --- end if; --- end process; + gen_normal_ctrl_regs : if std_COMCTRLREG > 1 generate + gen_cregout : for i in 1 to std_COMCTRLREG-1 generate + gen_cregoutff1 : for j in i*c_REGIO_REG_WIDTH to (i+1)*c_REGIO_REG_WIDTH-1 generate + process(CLK) + variable tmp : std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + begin + if rising_edge(CLK) then + if RESET = '1' then + buf_COMMON_CTRL_REG_OUT(j) <= '0'; + elsif COMMON_REGISTERS_OUT_write_enable(i) = '1' then + tmp := saved_Reg_high & saved_Reg_low; + buf_COMMON_CTRL_REG_OUT(j) <= tmp(j-i*c_REGIO_REG_WIDTH); + end if; + end if; + end process; + end generate; + end generate; + end generate; process(CLK) begin diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 370546f..f70c6c1 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -101,7 +101,7 @@ package trb_net_std is --common registers --maximum: 4, because of regio implementation constant std_COMSTATREG : integer := 2; - constant std_COMCTRLREG : integer := 1; + constant std_COMCTRLREG : integer := 2; --needed address width for common registers constant std_COMneededwidth : integer := 1; constant c_REGIO_ADDRESS_WIDTH : integer := 16; -- 2.43.0