From 6e7dc79736d60de3cd70f8c151d7032e89898183 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 14 Sep 2011 13:54:58 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/spi_dpram_32_to_8.jhd | 10 +- lattice/ecp2m/spi_dpram_32_to_8.lpc | 117 +- lattice/ecp2m/spi_dpram_32_to_8.srp | 18 +- lattice/ecp2m/spi_dpram_32_to_8.vhd | 322 +- media_interfaces/ecp3_sfp/.cvsignore | 1 + .../ecp3_sfp/serdes_onboard_full.ipx | 10 + .../ecp3_sfp/serdes_onboard_full.vhd | 26 +- media_interfaces/ecp3_sfp/sfp_0_200_int.ipx | 10 + media_interfaces/ecp3_sfp/sfp_0_200_int.lpc | 258 ++ media_interfaces/ecp3_sfp/sfp_0_200_int.pp | 195 + .../ecp3_sfp/sfp_0_200_int.readme | 153 + media_interfaces/ecp3_sfp/sfp_0_200_int.sort | 1 + media_interfaces/ecp3_sfp/sfp_0_200_int.tft | 100 + media_interfaces/ecp3_sfp/sfp_0_200_int.txt | 59 + media_interfaces/ecp3_sfp/sfp_0_200_int.vhd | 3122 +++++++++++++++++ media_interfaces/trb_net16_med_ecp3_sfp.vhd | 674 ++++ .../trb_net16_med_ecp3_sfp_4_onboard.vhd | 795 +++++ trb_net16_hub_logic.vhd | 110 +- trb_net_components.vhd | 1948 +++++----- 19 files changed, 6685 insertions(+), 1244 deletions(-) create mode 100644 media_interfaces/ecp3_sfp/serdes_onboard_full.ipx create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.ipx create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.lpc create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.pp create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.readme create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.sort create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.tft create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.txt create mode 100644 media_interfaces/ecp3_sfp/sfp_0_200_int.vhd create mode 100644 media_interfaces/trb_net16_med_ecp3_sfp.vhd create mode 100644 media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd diff --git a/lattice/ecp2m/spi_dpram_32_to_8.jhd b/lattice/ecp2m/spi_dpram_32_to_8.jhd index a5c1c35..72ff8c6 100755 --- a/lattice/ecp2m/spi_dpram_32_to_8.jhd +++ b/lattice/ecp2m/spi_dpram_32_to_8.jhd @@ -1 +1,9 @@ -MODULE spi_dpram_32_to_8 +MODULE spi_dpram_32_to_8 DEFIN spi_dpram_32_to_8.vhd + SUBMODULE DP16KB + INSTANCE spi_dpram_32_to_8_0_1_0 + SUBMODULE VLO + INSTANCE scuba_vlo_inst + SUBMODULE VHI + INSTANCE scuba_vhi_inst + SUBMODULE DP16KB + INSTANCE spi_dpram_32_to_8_0_0_1 diff --git a/lattice/ecp2m/spi_dpram_32_to_8.lpc b/lattice/ecp2m/spi_dpram_32_to_8.lpc index e8199cb..e960abb 100755 --- a/lattice/ecp2m/spi_dpram_32_to_8.lpc +++ b/lattice/ecp2m/spi_dpram_32_to_8.lpc @@ -1,57 +1,60 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-6F900C -SpeedGrade=-6 -Package=FPBGA900 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=RAM_DP_TRUE -CoreRevision=7.1 -ModuleName=spi_dpram_32_to_8 -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=08/24/2009 -Time=13:18:12 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -AAddress=64 -BAddress=256 -AData=32 -BData=8 -enByte=0 -ByteSize=9 -AadPipeline=0 -BadPipeline=0 -AinPipeline=0 -BinPipeline=0 -AoutPipeline=0 -BoutPipeline=0 -AMOR=0 -BMOR=0 -AInData=Registered -BInData=Registered -AAdControl=Registered -BAdControl=Registered -MemFile= -MemFormat=bin -Reset=Sync -GSR=Enabled -WriteA=Normal -WriteB=Normal -Pad=0 -EnECC=0 -Optimization=Speed -Pipeline=0 +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-5F1152C +SpeedGrade=5 +Package=FPBGA1152 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.1 +ModuleName=spi_dpram_32_to_8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/12/2011 +Time=17:31:07 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +AAddress=64 +BAddress=256 +AData=32 +BData=8 +enByte=0 +ByteSize=9 +AadPipeline=0 +BadPipeline=0 +AinPipeline=0 +BinPipeline=0 +AoutPipeline=0 +BoutPipeline=0 +AMOR=0 +BMOR=0 +AInData=Registered +BInData=Registered +AAdControl=Registered +BAdControl=Registered +MemFile= +MemFormat=bin +Reset=Sync +GSR=Enabled +WriteA=Normal +WriteB=Normal +Pad=0 +EnECC=0 +Optimization=Speed +Pipeline=0 + +[FilesGenerated] +=mem diff --git a/lattice/ecp2m/spi_dpram_32_to_8.srp b/lattice/ecp2m/spi_dpram_32_to_8.srp index bd91c46..279c98b 100755 --- a/lattice/ecp2m/spi_dpram_32_to_8.srp +++ b/lattice/ecp2m/spi_dpram_32_to_8.srp @@ -1,14 +1,14 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Mon Aug 24 13:18:12 2009 +SCUBA, Version Diamond_1.3_Production (92) +Mon Sep 12 17:31:08 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. - Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_spi_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 6 -widtha 32 -baddr_width 8 -widthb 8 -anum_words 64 -bnum_words 256 -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e - Circuit name : slv_spi_dpram + Issued command : /d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n spi_dpram_32_to_8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 6 -widtha 32 -baddr_width 8 -widthb 8 -anum_words 64 -bnum_words 256 -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e + Circuit name : spi_dpram_32_to_8 Module type : RAM_DP_TRUE Module Version : 7.1 Ports : @@ -16,12 +16,12 @@ Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. Outputs : QA[31:0], QB[7:0] I/O buffer : not inserted EDIF output : suppressed - VHDL output : slv_spi_dpram.vhd - VHDL template : slv_spi_dpram_tmpl.vhd - VHDL testbench : tb_slv_spi_dpram_tmpl.vhd + VHDL output : spi_dpram_32_to_8.vhd + VHDL template : spi_dpram_32_to_8_tmpl.vhd + VHDL testbench : tb_spi_dpram_32_to_8_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : big endian - Report output : slv_spi_dpram.srp + Report output : spi_dpram_32_to_8.srp Element Usage : DP16KB : 2 Estimated Resource Usage: diff --git a/lattice/ecp2m/spi_dpram_32_to_8.vhd b/lattice/ecp2m/spi_dpram_32_to_8.vhd index 8c9411c..d15c265 100755 --- a/lattice/ecp2m/spi_dpram_32_to_8.vhd +++ b/lattice/ecp2m/spi_dpram_32_to_8.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) -- Module Version: 7.1 ---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 8 -num_rows 64 -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e +--/d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 8 -num_rows 64 -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e --- Mon Aug 24 13:18:12 2009 +-- Mon Sep 12 17:31:08 2011 library IEEE; use IEEE.std_logic_1164.all; @@ -13,21 +13,21 @@ use ecp2m.components.all; entity spi_dpram_32_to_8 is port ( - DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(7 downto 0); - AddressA: in std_logic_vector(5 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(31 downto 0); + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(7 downto 0); + AddressA: in std_logic_vector(5 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); QB: out std_logic_vector(7 downto 0)); -end entity; +end spi_dpram_32_to_8; architecture Structure of spi_dpram_32_to_8 is @@ -44,82 +44,82 @@ architecture Structure of spi_dpram_32_to_8 is end component; component DP16KB -- synopsys translate_off - generic (GSR : in String; WRITEMODE_B : in String; - CSDECODE_B : in std_logic_vector(2 downto 0); - CSDECODE_A : in std_logic_vector(2 downto 0); - WRITEMODE_A : in String; RESETMODE : in String; - REGMODE_B : in String; REGMODE_A : in String; + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); -- synopsys translate_on - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; DOB16: out std_logic; DOB17: out std_logic); end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute CSDECODE_B : string; - attribute CSDECODE_A : string; - attribute WRITEMODE_B : string; - attribute WRITEMODE_A : string; - attribute GSR : string; - attribute RESETMODE : string; - attribute REGMODE_B : string; - attribute REGMODE_A : string; - attribute DATA_WIDTH_B : string; - attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; attribute MEM_LPC_FILE of spi_dpram_32_to_8_0_0_1 : label is "spi_dpram_32_to_8.lpc"; attribute MEM_INIT_FILE of spi_dpram_32_to_8_0_0_1 : label is ""; attribute CSDECODE_B of spi_dpram_32_to_8_0_0_1 : label is "0b000"; @@ -149,44 +149,44 @@ begin -- component instantiation statements spi_dpram_32_to_8_0_0_1: DP16KB -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 18) -- synopsys translate_on - port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), - DIA3=>DataInA(3), DIA4=>DataInA(8), DIA5=>DataInA(9), - DIA6=>DataInA(10), DIA7=>DataInA(11), DIA8=>scuba_vlo, - DIA9=>DataInA(16), DIA10=>DataInA(17), DIA11=>DataInA(18), - DIA12=>DataInA(19), DIA13=>DataInA(24), DIA14=>DataInA(25), - DIA15=>DataInA(26), DIA16=>DataInA(27), DIA17=>scuba_vlo, - ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, - ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), - ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), - ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo, - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, - CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), - DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1), - ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4), - ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7), - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), - DOA3=>QA(3), DOA4=>QA(8), DOA5=>QA(9), DOA6=>QA(10), - DOA7=>QA(11), DOA8=>open, DOA9=>QA(16), DOA10=>QA(17), - DOA11=>QA(18), DOA12=>QA(19), DOA13=>QA(24), DOA14=>QA(25), - DOA15=>QA(26), DOA16=>QA(27), DOA17=>open, DOB0=>QB(0), - DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), + DIA3=>DataInA(3), DIA4=>DataInA(8), DIA5=>DataInA(9), + DIA6=>DataInA(10), DIA7=>DataInA(11), DIA8=>scuba_vlo, + DIA9=>DataInA(16), DIA10=>DataInA(17), DIA11=>DataInA(18), + DIA12=>DataInA(19), DIA13=>DataInA(24), DIA14=>DataInA(25), + DIA15=>DataInA(26), DIA16=>DataInA(27), DIA17=>scuba_vlo, + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), + ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), + ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, + CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), + DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1), + ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4), + ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7), + ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, + ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), + DOA3=>QA(3), DOA4=>QA(8), DOA5=>QA(9), DOA6=>QA(10), + DOA7=>QA(11), DOA8=>open, DOA9=>QA(16), DOA10=>QA(17), + DOA11=>QA(18), DOA12=>QA(19), DOA13=>QA(24), DOA14=>QA(25), + DOA15=>QA(26), DOA16=>QA(27), DOA17=>open, DOB0=>QB(0), + DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); scuba_vhi_inst: VHI @@ -197,44 +197,44 @@ begin spi_dpram_32_to_8_0_1_0: DP16KB -- synopsys translate_off - generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 18) -- synopsys translate_on - port map (DIA0=>DataInA(4), DIA1=>DataInA(5), DIA2=>DataInA(6), - DIA3=>DataInA(7), DIA4=>DataInA(12), DIA5=>DataInA(13), - DIA6=>DataInA(14), DIA7=>DataInA(15), DIA8=>scuba_vlo, - DIA9=>DataInA(20), DIA10=>DataInA(21), DIA11=>DataInA(22), - DIA12=>DataInA(23), DIA13=>DataInA(28), DIA14=>DataInA(29), - DIA15=>DataInA(30), DIA16=>DataInA(31), DIA17=>scuba_vlo, - ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, - ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), - ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), - ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo, - ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, - CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, - CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(4), - DIB1=>DataInB(5), DIB2=>DataInB(6), DIB3=>DataInB(7), - DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, - DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, - DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, - DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, - DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, - ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1), - ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4), - ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7), - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, - CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, - RSTB=>ResetB, DOA0=>QA(4), DOA1=>QA(5), DOA2=>QA(6), - DOA3=>QA(7), DOA4=>QA(12), DOA5=>QA(13), DOA6=>QA(14), - DOA7=>QA(15), DOA8=>open, DOA9=>QA(20), DOA10=>QA(21), - DOA11=>QA(22), DOA12=>QA(23), DOA13=>QA(28), DOA14=>QA(29), - DOA15=>QA(30), DOA16=>QA(31), DOA17=>open, DOB0=>QB(4), - DOB1=>QB(5), DOB2=>QB(6), DOB3=>QB(7), DOB4=>open, - DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, - DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + port map (DIA0=>DataInA(4), DIA1=>DataInA(5), DIA2=>DataInA(6), + DIA3=>DataInA(7), DIA4=>DataInA(12), DIA5=>DataInA(13), + DIA6=>DataInA(14), DIA7=>DataInA(15), DIA8=>scuba_vlo, + DIA9=>DataInA(20), DIA10=>DataInA(21), DIA11=>DataInA(22), + DIA12=>DataInA(23), DIA13=>DataInA(28), DIA14=>DataInA(29), + DIA15=>DataInA(30), DIA16=>DataInA(31), DIA17=>scuba_vlo, + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), + ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), + ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA, + CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(4), + DIB1=>DataInB(5), DIB2=>DataInB(6), DIB3=>DataInB(7), + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1), + ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4), + ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7), + ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, + ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(4), DOA1=>QA(5), DOA2=>QA(6), + DOA3=>QA(7), DOA4=>QA(12), DOA5=>QA(13), DOA6=>QA(14), + DOA7=>QA(15), DOA8=>open, DOA9=>QA(20), DOA10=>QA(21), + DOA11=>QA(22), DOA12=>QA(23), DOA13=>QA(28), DOA14=>QA(29), + DOA15=>QA(30), DOA16=>QA(31), DOA17=>open, DOB0=>QB(4), + DOB1=>QB(5), DOB2=>QB(6), DOB3=>QB(7), DOB4=>open, + DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); end Structure; diff --git a/media_interfaces/ecp3_sfp/.cvsignore b/media_interfaces/ecp3_sfp/.cvsignore index 164798c..92fe863 100644 --- a/media_interfaces/ecp3_sfp/.cvsignore +++ b/media_interfaces/ecp3_sfp/.cvsignore @@ -7,3 +7,4 @@ *pp *readme *tft +*sort diff --git a/media_interfaces/ecp3_sfp/serdes_onboard_full.ipx b/media_interfaces/ecp3_sfp/serdes_onboard_full.ipx new file mode 100644 index 0000000..61a9b74 --- /dev/null +++ b/media_interfaces/ecp3_sfp/serdes_onboard_full.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd b/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd index b95e437..6500eb8 100644 --- a/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd +++ b/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd @@ -1525,7 +1525,7 @@ use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity rx_reset_sm is +entity rx_reset_sm_full is generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -1536,9 +1536,9 @@ port ( rx_los_low_ch_s : in std_logic; rx_pcs_rst_ch_c : out std_logic ); -end rx_reset_sm ; +end rx_reset_sm_full ; -architecture rx_reset_sm_arch of rx_reset_sm is +architecture rx_reset_sm_arch of rx_reset_sm_full is type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL); @@ -1713,7 +1713,7 @@ use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; -entity tx_reset_sm is +entity tx_reset_sm_full is generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -1722,9 +1722,9 @@ port ( rst_qd_c : out std_logic; tx_pcs_rst_ch_c : out std_logic ); -end tx_reset_sm; +end tx_reset_sm_full; -architecture tx_reset_sm_arch of tx_reset_sm is +architecture tx_reset_sm_arch of tx_reset_sm_full is type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); @@ -2026,7 +2026,7 @@ port ( Z : out std_logic); end component; -component rx_reset_sm +component rx_reset_sm_full generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -2039,7 +2039,7 @@ port ( ); end component ; -component tx_reset_sm +component tx_reset_sm_full generic (count_index: integer :=18); port ( rst_n : in std_logic; @@ -3182,7 +3182,7 @@ port map ( END IF; END PROCESS; -rx_reset_sm_ch0 : rx_reset_sm +rx_reset_sm_ch0 : rx_reset_sm_full --synopsys translate_off generic map (count_index => 4) --synopsys translate_on @@ -3204,7 +3204,7 @@ port map ( END IF; END PROCESS; -rx_reset_sm_ch1 : rx_reset_sm +rx_reset_sm_ch1 : rx_reset_sm_full --synopsys translate_off generic map (count_index => 4) --synopsys translate_on @@ -3226,7 +3226,7 @@ port map ( END IF; END PROCESS; -rx_reset_sm_ch2 : rx_reset_sm +rx_reset_sm_ch2 : rx_reset_sm_full --synopsys translate_off generic map (count_index => 4) --synopsys translate_on @@ -3248,7 +3248,7 @@ port map ( END IF; END PROCESS; -rx_reset_sm_ch3 : rx_reset_sm +rx_reset_sm_ch3 : rx_reset_sm_full --synopsys translate_off generic map (count_index => 4) --synopsys translate_on @@ -3272,7 +3272,7 @@ port map ( END PROCESS; -- reset sequence for tx -tx_reset_sm_ch : tx_reset_sm +tx_reset_sm_ch : tx_reset_sm_full --synopsys translate_off generic map (count_index => 4) --synopsys translate_on diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.ipx b/media_interfaces/ecp3_sfp/sfp_0_200_int.ipx new file mode 100644 index 0000000..a5e6edb --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.lpc b/media_interfaces/ecp3_sfp/sfp_0_200_int.lpc new file mode 100644 index 0000000..02b56e6 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.lpc @@ -0,0 +1,258 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.1 +ModuleName=sfp_0_200_int +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/06/2011 +Time=10:18:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +_mode0=RXTX +_mode1=DISABLED +_mode2=DISABLED +_mode3=DISABLED +_protocol0=G8B10B +_protocol1=G8B10B +_protocol2=G8B10B +_protocol3=G8B10B +_ldr0=DISABLED +_ldr1=DISABLED +_ldr2=DISABLED +_ldr3=DISABLED +_datarange=2 +_pll_txsrc=INTERNAL +_refclk_mult=10X +_refclk_rate=200 +_tx_protocol0=G8B10B +_tx_protocol1=DISABLED +_tx_protocol2=DISABLED +_tx_protocol3=DISABLED +_tx_data_rate0=FULL +_tx_data_rate1=FULL +_tx_data_rate2=FULL +_tx_data_rate3=FULL +_tx_data_width0=16 +_tx_data_width1=8 +_tx_data_width2=8 +_tx_data_width3=8 +_tx_fifo0=ENABLED +_tx_fifo1=ENABLED +_tx_fifo2=ENABLED +_tx_fifo3=ENABLED +_tx_ficlk_rate0=100 +_tx_ficlk_rate1=200 +_tx_ficlk_rate2=200 +_tx_ficlk_rate3=200 +_pll_rxsrc0=INTERNAL +_pll_rxsrc1=EXTERNAL +_pll_rxsrc2=EXTERNAL +_pll_rxsrc3=EXTERNAL +Multiplier0= +Multiplier1= +Multiplier2= +Multiplier3= +_rx_datarange0=2 +_rx_datarange1=2 +_rx_datarange2=2 +_rx_datarange3=2 +_rx_protocol0=G8B10B +_rx_protocol1=DISABLED +_rx_protocol2=DISABLED +_rx_protocol3=DISABLED +_rx_data_rate0=FULL +_rx_data_rate1=FULL +_rx_data_rate2=FULL +_rx_data_rate3=FULL +_rxrefclk_rate0=200 +_rxrefclk_rate1=200 +_rxrefclk_rate2=200 +_rxrefclk_rate3=200 +_rx_data_width0=16 +_rx_data_width1=8 +_rx_data_width2=8 +_rx_data_width3=8 +_rx_fifo0=ENABLED +_rx_fifo1=ENABLED +_rx_fifo2=ENABLED +_rx_fifo3=ENABLED +_rx_ficlk_rate0=100 +_rx_ficlk_rate1=200 +_rx_ficlk_rate2=200 +_rx_ficlk_rate3=200 +_tdrv_ch0=0 +_tdrv_ch1=0 +_tdrv_ch2=0 +_tdrv_ch3=0 +_tx_pre0=DISABLED +_tx_pre1=DISABLED +_tx_pre2=DISABLED +_tx_pre3=DISABLED +_rterm_tx0=50 +_rterm_tx1=50 +_rterm_tx2=50 +_rterm_tx3=50 +_rx_eq0=DISABLED +_rx_eq1=DISABLED +_rx_eq2=DISABLED +_rx_eq3=DISABLED +_rterm_rx0=50 +_rterm_rx1=50 +_rterm_rx2=50 +_rterm_rx3=50 +_rx_dcc0=DC +_rx_dcc1=AC +_rx_dcc2=AC +_rx_dcc3=AC +_los_threshold_mode0=LOS_E +_los_threshold_mode1=LOS_E +_los_threshold_mode2=LOS_E +_los_threshold_mode3=LOS_E +_los_threshold_lo0=2 +_los_threshold_lo1=2 +_los_threshold_lo2=2 +_los_threshold_lo3=2 +_los_threshold_hi0=7 +_los_threshold_hi1=7 +_los_threshold_hi2=7 +_los_threshold_hi3=7 +_pll_term=50 +_pll_dcc=AC +_pll_lol_set=0 +_tx_sb0=DISABLED +_tx_sb1=DISABLED +_tx_sb2=DISABLED +_tx_sb3=DISABLED +_tx_8b10b0=ENABLED +_tx_8b10b1=ENABLED +_tx_8b10b2=ENABLED +_tx_8b10b3=ENABLED +_rx_sb0=DISABLED +_rx_sb1=DISABLED +_rx_sb2=DISABLED +_rx_sb3=DISABLED +_ird0=DISABLED +_ird1=DISABLED +_ird2=DISABLED +_ird3=DISABLED +_rx_8b10b0=ENABLED +_rx_8b10b1=ENABLED +_rx_8b10b2=ENABLED +_rx_8b10b3=ENABLED +_rxwa0=ENABLED +_rxwa1=ENABLED +_rxwa2=ENABLED +_rxwa3=ENABLED +_ilsm0=ENABLED +_ilsm1=ENABLED +_ilsm2=ENABLED +_ilsm3=ENABLED +_scomma0=K28P157 +_scomma1=K28P157 +_scomma2=K28P157 +_scomma3=K28P157 +_comma_a0=1100000101 +_comma_a1=1100000101 +_comma_a2=1100000101 +_comma_a3=1100000101 +_comma_b0=0011111010 +_comma_b1=0011111010 +_comma_b2=0011111010 +_comma_b3=0011111010 +_comma_m0=1111111100 +_comma_m1=1111111100 +_comma_m2=1111111100 +_comma_m3=1111111100 +_ctc0=DISABLED +_ctc1=DISABLED +_ctc2=DISABLED +_ctc3=DISABLED +_cc_match_mode0=2 +_cc_match_mode1=1 +_cc_match_mode2=1 +_cc_match_mode3=1 +_k00=01 +_k01=01 +_k02=00 +_k03=00 +_k10=01 +_k11=00 +_k12=00 +_k13=00 +_k20=01 +_k21=01 +_k22=01 +_k23=01 +_k30=01 +_k31=01 +_k32=01 +_k33=01 +_byten00=00011100 +_byten01=00011100 +_byten02=00000000 +_byten03=00000000 +_byten10=00011100 +_byten11=00000000 +_byten12=00000000 +_byten13=00000000 +_byten20=00011100 +_byten21=00011100 +_byten22=00011100 +_byten23=00011100 +_byten30=00011100 +_byten31=00011100 +_byten32=00011100 +_byten33=00011100 +_cc_min_ipg0=1 +_cc_min_ipg1=3 +_cc_min_ipg2=3 +_cc_min_ipg3=3 +_cchmark=9 +_cclmark=7 +_loopback=DISABLED +_lbtype0=DISABLED +_lbtype1=DISABLED +_lbtype2=DISABLED +_lbtype3=DISABLED +_teidle_ch0=DISABLED +_teidle_ch1=DISABLED +_teidle_ch2=DISABLED +_teidle_ch3=DISABLED +_rst_gen=ENABLED +_rx_los_port0=Internal +_rx_los_port1=Internal +_rx_los_port2=Internal +_rx_los_port3=Internal +_sci_ports=ENABLED +_sci_int_port=DISABLED +_refck2core=DISABLED +Regen=auto +PAR1=0 +PARTrace1=0 +PAR3=0 +PARTrace3=0 + +[FilesGenerated] +sfp_0_200_int.pp=pp +sfp_0_200_int.tft=tft +sfp_0_200_int.txt=pcs_module +sfp_0_200_int.sym=sym diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.pp b/media_interfaces/ecp3_sfp/sfp_0_200_int.pp new file mode 100644 index 0000000..0d48813 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.pp @@ -0,0 +1,195 @@ +#define _device_name "LFE3-150EA" +#define _ch0_pll_rxsrc "REFCLK_CORE" +#define _ch0_mode "RXTX" +#define _ch0_protocol "G8B10B" +#define _ch0_ldr "DISABLED" +#define _ch0_tx_data_rate "FULL" +#define _ch0_tx_data_width "16" +#define _ch0_tx_fifo "ENABLED" +#define _ch0_tx_ficlk_rate 100 +#define _ch0_rx_datarange "MEDHIGH" +#define _ch0_rx_data_rate "FULL" +#define _ch0_rxrefclk_rate "200" +#define _ch0_rx_data_width "16" +#define _ch0_rx_fifo "ENABLED" +#define _ch0_rx_ficlk_rate 100 +#define _ch0_tdrv "0" +#define _ch0_tx_pre "DISABLED" +#define _ch0_rterm_tx "50" +#define _ch0_rx_eq "DISABLED" +#define _ch0_rterm_rx "50" +#define _ch0_rx_dcc "DC" +#define _los_threshold_mode0 "LOS_E" +#define _los_threshold_lo0 "2" +#define _ch0_tx_sb "DISABLED" +#define _ch0_tx_8b10b "ENABLED" +#define _ch0_rx_sb "DISABLED" +#define _ch0_ird "DISABLED" +#define _ch0_rx_8b10b "ENABLED" +#define _ch0_rxwa "ENABLED" +#define _ch0_ilsm "ENABLED" +#define _ch0_scomma "K28P157" +#define _ch0_comma_a "1100000101" +#define _ch0_comma_b "0011111010" +#define _ch0_comma_m "1111111100" +#define _ch0_ctc "DISABLED" +#define _ch0_cc_match_mode "2" +#define _ch0_byten "0100011100" +#define _ch0_byten1 "0100011100" +#define _ch0_byten2 "0100011100" +#define _ch0_byten3 "0100011100" +#define _ch0_cc_min_ipg "1" +#define _ch0_lbtype "DISABLED" +#define _ch0_teidle "DISABLED" +#define _ch0_rx_lol_port "INTERNAL" + +#define _ch1_pll_rxsrc "REFCLK_EXT" +#define _ch1_mode "DISABLED" +#define _ch1_protocol "G8B10B" +#define _ch1_ldr "DISABLED" +#define _ch1_tx_data_rate "FULL" +#define _ch1_tx_data_width "8" +#define _ch1_tx_fifo "ENABLED" +#define _ch1_tx_ficlk_rate 200 +#define _ch1_rx_datarange "MEDHIGH" +#define _ch1_rx_data_rate "FULL" +#define _ch1_rxrefclk_rate "200" +#define _ch1_rx_data_width "8" +#define _ch1_rx_fifo "ENABLED" +#define _ch1_rx_ficlk_rate 200 +#define _ch1_tdrv "0" +#define _ch1_tx_pre "DISABLED" +#define _ch1_rterm_tx "50" +#define _ch1_rx_eq "DISABLED" +#define _ch1_rterm_rx "50" +#define _ch1_rx_dcc "AC" +#define _los_threshold_mode1 "LOS_E" +#define _los_threshold_lo1 "2" +#define _ch1_tx_sb "DISABLED" +#define _ch1_tx_8b10b "ENABLED" +#define _ch1_rx_sb "DISABLED" +#define _ch1_ird "DISABLED" +#define _ch1_rx_8b10b "ENABLED" +#define _ch1_rxwa "ENABLED" +#define _ch1_ilsm "ENABLED" +#define _ch1_scomma "K28P157" +#define _ch1_comma_a "1100000101" +#define _ch1_comma_b "0011111010" +#define _ch1_comma_m "1111111100" +#define _ch1_ctc "DISABLED" +#define _ch1_cc_match_mode "1" +#define _ch1_byten "0100011100" +#define _ch1_byten1 "0000000000" +#define _ch1_byten2 "0100011100" +#define _ch1_byten3 "0100011100" +#define _ch1_cc_min_ipg "3" +#define _ch1_lbtype "DISABLED" +#define _ch1_teidle "DISABLED" +#define _ch1_rx_lol_port "INTERNAL" + +#define _ch2_pll_rxsrc "REFCLK_EXT" +#define _ch2_mode "DISABLED" +#define _ch2_protocol "G8B10B" +#define _ch2_ldr "DISABLED" +#define _ch2_tx_data_rate "FULL" +#define _ch2_tx_data_width "8" +#define _ch2_tx_fifo "ENABLED" +#define _ch2_tx_ficlk_rate 200 +#define _ch2_rx_datarange "MEDHIGH" +#define _ch2_rx_data_rate "FULL" +#define _ch2_rxrefclk_rate "200" +#define _ch2_rx_data_width "8" +#define _ch2_rx_fifo "ENABLED" +#define _ch2_rx_ficlk_rate 200 +#define _ch2_tdrv "0" +#define _ch2_tx_pre "DISABLED" +#define _ch2_rterm_tx "50" +#define _ch2_rx_eq "DISABLED" +#define _ch2_rterm_rx "50" +#define _ch2_rx_dcc "AC" +#define _los_threshold_mode2 "LOS_E" +#define _los_threshold_lo2 "2" +#define _ch2_tx_sb "DISABLED" +#define _ch2_tx_8b10b "ENABLED" +#define _ch2_rx_sb "DISABLED" +#define _ch2_ird "DISABLED" +#define _ch2_rx_8b10b "ENABLED" +#define _ch2_rxwa "ENABLED" +#define _ch2_ilsm "ENABLED" +#define _ch2_scomma "K28P157" +#define _ch2_comma_a "1100000101" +#define _ch2_comma_b "0011111010" +#define _ch2_comma_m "1111111100" +#define _ch2_ctc "DISABLED" +#define _ch2_cc_match_mode "1" +#define _ch2_byten "0000000000" +#define _ch2_byten1 "0000000000" +#define _ch2_byten2 "0100011100" +#define _ch2_byten3 "0100011100" +#define _ch2_cc_min_ipg "3" +#define _ch2_lbtype "DISABLED" +#define _ch2_teidle "DISABLED" +#define _ch2_rx_lol_port "INTERNAL" + +#define _ch3_pll_rxsrc "REFCLK_EXT" +#define _ch3_mode "DISABLED" +#define _ch3_protocol "G8B10B" +#define _ch3_ldr "DISABLED" +#define _ch3_tx_data_rate "FULL" +#define _ch3_tx_data_width "8" +#define _ch3_tx_fifo "ENABLED" +#define _ch3_tx_ficlk_rate 200 +#define _ch3_rx_datarange "MEDHIGH" +#define _ch3_rx_data_rate "FULL" +#define _ch3_rxrefclk_rate "200" +#define _ch3_rx_data_width "8" +#define _ch3_rx_fifo "ENABLED" +#define _ch3_rx_ficlk_rate 200 +#define _ch3_tdrv "0" +#define _ch3_tx_pre "DISABLED" +#define _ch3_rterm_tx "50" +#define _ch3_rx_eq "DISABLED" +#define _ch3_rterm_rx "50" +#define _ch3_rx_dcc "AC" +#define _los_threshold_mode3 "LOS_E" +#define _los_threshold_lo3 "2" +#define _ch3_tx_sb "DISABLED" +#define _ch3_tx_8b10b "ENABLED" +#define _ch3_rx_sb "DISABLED" +#define _ch3_ird "DISABLED" +#define _ch3_rx_8b10b "ENABLED" +#define _ch3_rxwa "ENABLED" +#define _ch3_ilsm "ENABLED" +#define _ch3_scomma "K28P157" +#define _ch3_comma_a "1100000101" +#define _ch3_comma_b "0011111010" +#define _ch3_comma_m "1111111100" +#define _ch3_ctc "DISABLED" +#define _ch3_cc_match_mode "1" +#define _ch3_byten "0000000000" +#define _ch3_byten1 "0000000000" +#define _ch3_byten2 "0100011100" +#define _ch3_byten3 "0100011100" +#define _ch3_cc_min_ipg "3" +#define _ch3_lbtype "DISABLED" +#define _ch3_teidle "DISABLED" +#define _ch3_rx_lol_port "INTERNAL" + +#define _datarange "MEDHIGH" +#define _pll_txsrc "REFCLK_CORE" +#define _refclk_mult "10X" +#define _refclk_rate 200 +#define _pll_term "50" +#define _pll_dcc "AC" +#define _pll_lol_set "0" +#define _cchmark "9" +#define _cclmark "7" +#define _rst_gen "ENABLED" +#define _sci_ports "ENABLED" +#define _sci_int_port "DISABLED" +#define _refck2core "DISABLED" +#define _circuit_name sfp_0_200_int +#define _lang vhdl + +#include +#include diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.readme b/media_interfaces/ecp3_sfp/sfp_0_200_int.readme new file mode 100644 index 0000000..e671e69 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.readme @@ -0,0 +1,153 @@ + + TOOL: orcapp + DATE: 19-MAR-2008 13:11:52 + TITLE: Lattice Semiconductor Corporation + MODULE: sfp_0_200_int + DESIGN: sfp_0_200_int + FILENAME: sfp_0_200_int.readme + PROJECT: Unknown + VERSION: 2.0 + This file is auto generated by the ispLEVER + + +NOTE: This readme file has been provided to instantiate the interface +netlist. Since this template contains synthesis attributes for precision that +are crucial to the design flow, we recommend that you use this +template in your FPGA design. +entity chip is +port ( + +-- Add your FPGA design top level I/Os here + + +-- ASIC side pins for PCSD. These pins must exist for the +-- PCS core. + refclkp : in std_logic; + refclkn : in std_logic; + hdinp_ch0 : in std_logic; + hdinn_ch0 : in std_logic; + hdinp_ch1 : in std_logic; + hdinn_ch1 : in std_logic; + hdinp_ch2 : in std_logic; + hdinn_ch2 : in std_logic; + hdinp_ch3 : in std_logic; + hdinn_ch3 : in std_logic; + + hdoutp_ch0 : out std_logic; + hdoutn_ch0 : out std_logic; + hdoutp_ch1 : out std_logic; + hdoutn_ch1 : out std_logic; + hdoutp_ch2 : out std_logic; + hdoutn_ch2 : out std_logic; + hdoutp_ch3 : out std_logic; + hdoutn_ch3 : out std_logic; + + +); +end chip; + +architecture chip_arch of chip is + +-- This defines all the high-speed ports. You may have to remove +-- some of them depending on your design. +attribute nopad : string; +attribute nopad of + refclkp, refclkn, + hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1, + hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3, + hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1, + hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true"; + + COMPONENT sfp_0_200_int + PORT( + hdinp_ch0 : IN std_logic; + hdinn_ch0 : IN std_logic; + sci_sel_ch0 : IN std_logic; + rxiclk_ch0 : IN std_logic; + txiclk_ch0 : IN std_logic; + fpga_rxrefclk_ch0 : IN std_logic; + txdata_ch0 : IN std_logic_vector(15 downto 0); + tx_k_ch0 : IN std_logic_vector(1 downto 0); + tx_force_disp_ch0 : IN std_logic_vector(1 downto 0); + tx_disp_sel_ch0 : IN std_logic_vector(1 downto 0); + sb_felb_ch0_c : IN std_logic; + sb_felb_rst_ch0_c : IN std_logic; + tx_pwrup_ch0_c : IN std_logic; + rx_pwrup_ch0_c : IN std_logic; + tx_div2_mode_ch0_c : IN std_logic; + rx_div2_mode_ch0_c : IN std_logic; + sci_wrdata : IN std_logic_vector(7 downto 0); + sci_addr : IN std_logic_vector(5 downto 0); + sci_sel_quad : IN std_logic; + sci_rd : IN std_logic; + sci_wrn : IN std_logic; + fpga_txrefclk : IN std_logic; + tx_serdes_rst_c : IN std_logic; + rst_n : IN std_logic; + serdes_rst_qd_c : IN std_logic; + hdoutp_ch0 : OUT std_logic; + hdoutn_ch0 : OUT std_logic; + rx_full_clk_ch0 : OUT std_logic; + rx_half_clk_ch0 : OUT std_logic; + tx_full_clk_ch0 : OUT std_logic; + tx_half_clk_ch0 : OUT std_logic; + rxdata_ch0 : OUT std_logic_vector(15 downto 0); + rx_k_ch0 : OUT std_logic_vector(1 downto 0); + rx_disp_err_ch0 : OUT std_logic_vector(1 downto 0); + rx_cv_err_ch0 : OUT std_logic_vector(1 downto 0); + rx_los_low_ch0_s : OUT std_logic; + lsm_status_ch0_s : OUT std_logic; + rx_cdr_lol_ch0_s : OUT std_logic; + sci_rddata : OUT std_logic_vector(7 downto 0); + tx_pll_lol_qd_s : OUT std_logic + ); + END COMPONENT; + + + + uut: sfp_0_200_int PORT MAP( + hdinp_ch0 => hdinp_ch0, + hdinn_ch0 => hdinn_ch0, + hdoutp_ch0 => hdoutp_ch0, + hdoutn_ch0 => hdoutn_ch0, + sci_sel_ch0 => sci_sel_ch0, + rxiclk_ch0 => rxiclk_ch0, + txiclk_ch0 => txiclk_ch0, + rx_full_clk_ch0 => rx_full_clk_ch0, + rx_half_clk_ch0 => rx_half_clk_ch0, + tx_full_clk_ch0 => tx_full_clk_ch0, + tx_half_clk_ch0 => tx_half_clk_ch0, + fpga_rxrefclk_ch0 => fpga_rxrefclk_ch0, + txdata_ch0 => txdata_ch0, + tx_k_ch0 => tx_k_ch0, + tx_force_disp_ch0 => tx_force_disp_ch0, + tx_disp_sel_ch0 => tx_disp_sel_ch0, + rxdata_ch0 => rxdata_ch0, + rx_k_ch0 => rx_k_ch0, + rx_disp_err_ch0 => rx_disp_err_ch0, + rx_cv_err_ch0 => rx_cv_err_ch0, + sb_felb_ch0_c => sb_felb_ch0_c, + sb_felb_rst_ch0_c => sb_felb_rst_ch0_c, + tx_pwrup_ch0_c => tx_pwrup_ch0_c, + rx_pwrup_ch0_c => rx_pwrup_ch0_c, + rx_los_low_ch0_s => rx_los_low_ch0_s, + lsm_status_ch0_s => lsm_status_ch0_s, + rx_cdr_lol_ch0_s => rx_cdr_lol_ch0_s, + tx_div2_mode_ch0_c => tx_div2_mode_ch0_c, + rx_div2_mode_ch0_c => rx_div2_mode_ch0_c, + sci_wrdata => sci_wrdata, + sci_addr => sci_addr, + sci_rddata => sci_rddata, + sci_sel_quad => sci_sel_quad, + sci_rd => sci_rd, + sci_wrn => sci_wrn, + fpga_txrefclk => fpga_txrefclk, + tx_serdes_rst_c => tx_serdes_rst_c, + tx_pll_lol_qd_s => tx_pll_lol_qd_s, + rst_n => rst_n, + serdes_rst_qd_c => serdes_rst_qd_c + ); + + + + diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.sort b/media_interfaces/ecp3_sfp/sfp_0_200_int.sort new file mode 100644 index 0000000..68c4432 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.sort @@ -0,0 +1 @@ +sfp_0_200_int.vhd diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.tft b/media_interfaces/ecp3_sfp/sfp_0_200_int.tft new file mode 100644 index 0000000..b9db080 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.tft @@ -0,0 +1,100 @@ +@set suppresnewline=on@ + +@comment --------------------------------------------------------------------- @ +@comment Template-drive TFI generator @ +@comment Template for TFI generation. @ +@comment --------------------------------------------------------------------- @ + +@set suppresnewline=off@ + TOOL: orcapp + DATE: 19-MAR-2008 13:11:52 + TITLE: %title% + MODULE: %module% + DESIGN: %module% + FILENAME: %filename% + PROJECT: %project% + VERSION: %ver% + This file is auto generated by the ispLEVER +@set suppresnewline=on@ + +@cr@ +@cr@ + +@set sigdelim=@ + +NOTE: This readme file has been provided to instantiate the interface@cr@ +netlist. Since this template contains synthesis attributes for precision that@cr@ +are crucial to the design flow, we recommend that you use this@cr@ +template in your FPGA design.@cr@ +entity chip is@cr@ +port (@cr@ +@cr@ +-- Add your FPGA design top level I/Os here@cr@ +@cr@ +@cr@ +-- ASIC side pins for PCSD. These pins must exist for the@cr@ +-- PCS core.@cr@ + refclkp : in std_logic;@cr@ + refclkn : in std_logic;@cr@ + hdinp_ch0 : in std_logic;@cr@ + hdinn_ch0 : in std_logic;@cr@ + hdinp_ch1 : in std_logic;@cr@ + hdinn_ch1 : in std_logic;@cr@ + hdinp_ch2 : in std_logic;@cr@ + hdinn_ch2 : in std_logic;@cr@ + hdinp_ch3 : in std_logic;@cr@ + hdinn_ch3 : in std_logic;@cr@ +@cr@ + hdoutp_ch0 : out std_logic;@cr@ + hdoutn_ch0 : out std_logic;@cr@ + hdoutp_ch1 : out std_logic;@cr@ + hdoutn_ch1 : out std_logic;@cr@ + hdoutp_ch2 : out std_logic;@cr@ + hdoutn_ch2 : out std_logic;@cr@ + hdoutp_ch3 : out std_logic;@cr@ + hdoutn_ch3 : out std_logic;@cr@ +@cr@ +@cr@ +);@cr@ +end chip;@cr@ +@cr@ +architecture chip_arch of chip is@cr@ +@cr@ +-- This defines all the high-speed ports. You may have to remove@cr@ +-- some of them depending on your design.@cr@ +attribute nopad : string;@cr@ +attribute nopad of@cr@ + refclkp, refclkn,@cr@ + hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@ + hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@ + hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@ + hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@ + +@cr@ +@tab@COMPONENT %module% +@set sigdelim=@ +@cr@@tab@PORT( +@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@ +@ifhas oport=*@ @comment if the design has any output ports... @ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@ + @set sigdelim=;@ + @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@ +@endif@ +@ifnhas oport=*@ @comment we need an "else in this language! @ + @set sigdelim=;@ + @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@ +@endif@ +@cr@@tab@@tab@);@cr@ +@tab@END COMPONENT;@cr@@cr@ +@comment Now do a signal declaration for each port @ + +@cr@@cr@ +@comment do the component instantiation @ +@set sigdelim=,@ +@tab@uut: %module% PORT MAP( +@iterate@%port% +@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@ +@cr@@tab@);@cr@@cr@ +@set suppresnewline=off@ + + diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.txt b/media_interfaces/ecp3_sfp/sfp_0_200_int.txt new file mode 100644 index 0000000..5166f48 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.txt @@ -0,0 +1,59 @@ +# This file is used by the simulation model as well as the ispLEVER bitstream +# generation process to automatically initialize the PCSD quad to the mode +# selected in the IPexpress. This file is expected to be modified by the +# end user to adjust the PCSD quad to the final design requirements. + +DEVICE_NAME "LFE3-150EA" +CH0_PROTOCOL "G8B10B" +CH0_MODE "RXTX" +CH1_MODE "DISABLED" +CH2_MODE "DISABLED" +CH3_MODE "DISABLED" +CH0_CDR_SRC "REFCLK_CORE" +PLL_SRC "REFCLK_CORE" +TX_DATARATE_RANGE "MEDHIGH" +CH0_RX_DATARATE_RANGE "MEDHIGH" +REFCK_MULT "10X" +#REFCLK_RATE 200 +CH0_RX_DATA_RATE "FULL" +CH0_TX_DATA_RATE "FULL" +CH0_TX_DATA_WIDTH "16" +CH0_RX_DATA_WIDTH "16" +CH0_TX_FIFO "ENABLED" +CH0_RX_FIFO "ENABLED" +CH0_TDRV "0" +#CH0_TX_FICLK_RATE 100 +#CH0_RXREFCLK_RATE "200" +#CH0_RX_FICLK_RATE 100 +CH0_TX_PRE "DISABLED" +CH0_RTERM_TX "50" +CH0_RX_EQ "DISABLED" +CH0_RTERM_RX "50" +CH0_RX_DCC "DC" +CH0_LOS_THRESHOLD_LO "2" +PLL_TERM "50" +PLL_DCC "AC" +PLL_LOL_SET "0" +CH0_TX_SB "DISABLED" +CH0_RX_SB "DISABLED" +CH0_TX_8B10B "ENABLED" +CH0_RX_8B10B "ENABLED" +CH0_COMMA_A "1100000101" +CH0_COMMA_B "0011111010" +CH0_COMMA_M "1111111100" +CH0_RXWA "ENABLED" +CH0_ILSM "ENABLED" +CH0_CTC "DISABLED" +CH0_CC_MATCH3 "0100011100" +CH0_CC_MATCH4 "0100011100" +CH0_CC_MATCH_MODE "2" +CH0_CC_MIN_IPG "1" +CCHMARK "9" +CCLMARK "7" +CH0_SSLB "DISABLED" +CH0_SPLBPORTS "DISABLED" +CH0_PCSLBPORTS "DISABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "DISABLED" + + diff --git a/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd b/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd new file mode 100644 index 0000000..bae3e22 --- /dev/null +++ b/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd @@ -0,0 +1,3122 @@ + + + +--synopsys translate_off + +library pcsd_work; +use pcsd_work.all; +library IEEE; +use IEEE.std_logic_1164.all; + +entity PCSD is +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String +-- CONFIG_FILE : String := "sfp_0_200_int.txt"; +-- QUAD_MODE : String := "SINGLE"; +-- CH0_CDR_SRC : String := "REFCLK_CORE"; +-- CH1_CDR_SRC : String := "REFCLK_EXT"; +-- CH2_CDR_SRC : String := "REFCLK_EXT"; +-- CH3_CDR_SRC : String := "REFCLK_EXT"; +-- PLL_SRC : String := "REFCLK_CORE" + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); + +end PCSD; + +architecture PCSD_arch of PCSD is + + +component PCSD_sim +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String; + CH1_CDR_SRC : String; + CH2_CDR_SRC : String; + CH3_CDR_SRC : String; + PLL_SRC : String + ); +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + +begin + +PCSD_sim_inst : PCSD_sim +generic map ( + CONFIG_FILE => CONFIG_FILE, + QUAD_MODE => QUAD_MODE, + CH0_CDR_SRC => CH0_CDR_SRC, + CH1_CDR_SRC => CH1_CDR_SRC, + CH2_CDR_SRC => CH2_CDR_SRC, + CH3_CDR_SRC => CH3_CDR_SRC, + PLL_SRC => PLL_SRC + ) +port map ( + HDINN0 => HDINN0, + HDINN1 => HDINN1, + HDINN2 => HDINN2, + HDINN3 => HDINN3, + HDINP0 => HDINP0, + HDINP1 => HDINP1, + HDINP2 => HDINP2, + HDINP3 => HDINP3, + REFCLKN => REFCLKN, + REFCLKP => REFCLKP, + CIN11 => CIN11, + CIN10 => CIN10, + CIN9 => CIN9, + CIN8 => CIN8, + CIN7 => CIN7, + CIN6 => CIN6, + CIN5 => CIN5, + CIN4 => CIN4, + CIN3 => CIN3, + CIN2 => CIN2, + CIN1 => CIN1, + CIN0 => CIN0, + CYAWSTN => CYAWSTN, + FF_EBRD_CLK_3 => FF_EBRD_CLK_3, + FF_EBRD_CLK_2 => FF_EBRD_CLK_2, + FF_EBRD_CLK_1 => FF_EBRD_CLK_1, + FF_EBRD_CLK_0 => FF_EBRD_CLK_0, + FF_RXI_CLK_3 => FF_RXI_CLK_3, + FF_RXI_CLK_2 => FF_RXI_CLK_2, + FF_RXI_CLK_1 => FF_RXI_CLK_1, + FF_RXI_CLK_0 => FF_RXI_CLK_0, + FF_TX_D_0_0 => FF_TX_D_0_0, + FF_TX_D_0_1 => FF_TX_D_0_1, + FF_TX_D_0_2 => FF_TX_D_0_2, + FF_TX_D_0_3 => FF_TX_D_0_3, + FF_TX_D_0_4 => FF_TX_D_0_4, + FF_TX_D_0_5 => FF_TX_D_0_5, + FF_TX_D_0_6 => FF_TX_D_0_6, + FF_TX_D_0_7 => FF_TX_D_0_7, + FF_TX_D_0_8 => FF_TX_D_0_8, + FF_TX_D_0_9 => FF_TX_D_0_9, + FF_TX_D_0_10 => FF_TX_D_0_10, + FF_TX_D_0_11 => FF_TX_D_0_11, + FF_TX_D_0_12 => FF_TX_D_0_12, + FF_TX_D_0_13 => FF_TX_D_0_13, + FF_TX_D_0_14 => FF_TX_D_0_14, + FF_TX_D_0_15 => FF_TX_D_0_15, + FF_TX_D_0_16 => FF_TX_D_0_16, + FF_TX_D_0_17 => FF_TX_D_0_17, + FF_TX_D_0_18 => FF_TX_D_0_18, + FF_TX_D_0_19 => FF_TX_D_0_19, + FF_TX_D_0_20 => FF_TX_D_0_20, + FF_TX_D_0_21 => FF_TX_D_0_21, + FF_TX_D_0_22 => FF_TX_D_0_22, + FF_TX_D_0_23 => FF_TX_D_0_23, + FF_TX_D_1_0 => FF_TX_D_1_0, + FF_TX_D_1_1 => FF_TX_D_1_1, + FF_TX_D_1_2 => FF_TX_D_1_2, + FF_TX_D_1_3 => FF_TX_D_1_3, + FF_TX_D_1_4 => FF_TX_D_1_4, + FF_TX_D_1_5 => FF_TX_D_1_5, + FF_TX_D_1_6 => FF_TX_D_1_6, + FF_TX_D_1_7 => FF_TX_D_1_7, + FF_TX_D_1_8 => FF_TX_D_1_8, + FF_TX_D_1_9 => FF_TX_D_1_9, + FF_TX_D_1_10 => FF_TX_D_1_10, + FF_TX_D_1_11 => FF_TX_D_1_11, + FF_TX_D_1_12 => FF_TX_D_1_12, + FF_TX_D_1_13 => FF_TX_D_1_13, + FF_TX_D_1_14 => FF_TX_D_1_14, + FF_TX_D_1_15 => FF_TX_D_1_15, + FF_TX_D_1_16 => FF_TX_D_1_16, + FF_TX_D_1_17 => FF_TX_D_1_17, + FF_TX_D_1_18 => FF_TX_D_1_18, + FF_TX_D_1_19 => FF_TX_D_1_19, + FF_TX_D_1_20 => FF_TX_D_1_20, + FF_TX_D_1_21 => FF_TX_D_1_21, + FF_TX_D_1_22 => FF_TX_D_1_22, + FF_TX_D_1_23 => FF_TX_D_1_23, + FF_TX_D_2_0 => FF_TX_D_2_0, + FF_TX_D_2_1 => FF_TX_D_2_1, + FF_TX_D_2_2 => FF_TX_D_2_2, + FF_TX_D_2_3 => FF_TX_D_2_3, + FF_TX_D_2_4 => FF_TX_D_2_4, + FF_TX_D_2_5 => FF_TX_D_2_5, + FF_TX_D_2_6 => FF_TX_D_2_6, + FF_TX_D_2_7 => FF_TX_D_2_7, + FF_TX_D_2_8 => FF_TX_D_2_8, + FF_TX_D_2_9 => FF_TX_D_2_9, + FF_TX_D_2_10 => FF_TX_D_2_10, + FF_TX_D_2_11 => FF_TX_D_2_11, + FF_TX_D_2_12 => FF_TX_D_2_12, + FF_TX_D_2_13 => FF_TX_D_2_13, + FF_TX_D_2_14 => FF_TX_D_2_14, + FF_TX_D_2_15 => FF_TX_D_2_15, + FF_TX_D_2_16 => FF_TX_D_2_16, + FF_TX_D_2_17 => FF_TX_D_2_17, + FF_TX_D_2_18 => FF_TX_D_2_18, + FF_TX_D_2_19 => FF_TX_D_2_19, + FF_TX_D_2_20 => FF_TX_D_2_20, + FF_TX_D_2_21 => FF_TX_D_2_21, + FF_TX_D_2_22 => FF_TX_D_2_22, + FF_TX_D_2_23 => FF_TX_D_2_23, + FF_TX_D_3_0 => FF_TX_D_3_0, + FF_TX_D_3_1 => FF_TX_D_3_1, + FF_TX_D_3_2 => FF_TX_D_3_2, + FF_TX_D_3_3 => FF_TX_D_3_3, + FF_TX_D_3_4 => FF_TX_D_3_4, + FF_TX_D_3_5 => FF_TX_D_3_5, + FF_TX_D_3_6 => FF_TX_D_3_6, + FF_TX_D_3_7 => FF_TX_D_3_7, + FF_TX_D_3_8 => FF_TX_D_3_8, + FF_TX_D_3_9 => FF_TX_D_3_9, + FF_TX_D_3_10 => FF_TX_D_3_10, + FF_TX_D_3_11 => FF_TX_D_3_11, + FF_TX_D_3_12 => FF_TX_D_3_12, + FF_TX_D_3_13 => FF_TX_D_3_13, + FF_TX_D_3_14 => FF_TX_D_3_14, + FF_TX_D_3_15 => FF_TX_D_3_15, + FF_TX_D_3_16 => FF_TX_D_3_16, + FF_TX_D_3_17 => FF_TX_D_3_17, + FF_TX_D_3_18 => FF_TX_D_3_18, + FF_TX_D_3_19 => FF_TX_D_3_19, + FF_TX_D_3_20 => FF_TX_D_3_20, + FF_TX_D_3_21 => FF_TX_D_3_21, + FF_TX_D_3_22 => FF_TX_D_3_22, + FF_TX_D_3_23 => FF_TX_D_3_23, + FF_TXI_CLK_0 => FF_TXI_CLK_0, + FF_TXI_CLK_1 => FF_TXI_CLK_1, + FF_TXI_CLK_2 => FF_TXI_CLK_2, + FF_TXI_CLK_3 => FF_TXI_CLK_3, + FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, + FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, + FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, + FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, + FFC_CK_CORE_TX => FFC_CK_CORE_TX, + FFC_EI_EN_0 => FFC_EI_EN_0, + FFC_EI_EN_1 => FFC_EI_EN_1, + FFC_EI_EN_2 => FFC_EI_EN_2, + FFC_EI_EN_3 => FFC_EI_EN_3, + FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, + FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, + FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, + FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, + FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, + FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, + FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, + FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, + FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, + FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, + FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, + FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, + FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, + FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, + FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, + FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, + FFC_MACRO_RST => FFC_MACRO_RST, + FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, + FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, + FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, + FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, + FFC_PCIE_CT_0 => FFC_PCIE_CT_0, + FFC_PCIE_CT_1 => FFC_PCIE_CT_1, + FFC_PCIE_CT_2 => FFC_PCIE_CT_2, + FFC_PCIE_CT_3 => FFC_PCIE_CT_3, + FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, + FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, + FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, + FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, + FFC_QUAD_RST => FFC_QUAD_RST, + FFC_RRST_0 => FFC_RRST_0, + FFC_RRST_1 => FFC_RRST_1, + FFC_RRST_2 => FFC_RRST_2, + FFC_RRST_3 => FFC_RRST_3, + FFC_RXPWDNB_0 => FFC_RXPWDNB_0, + FFC_RXPWDNB_1 => FFC_RXPWDNB_1, + FFC_RXPWDNB_2 => FFC_RXPWDNB_2, + FFC_RXPWDNB_3 => FFC_RXPWDNB_3, + FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, + FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, + FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, + FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, + FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, + FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, + FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, + FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, + FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, + FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, + FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, + FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, + FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, + FFC_TRST => FFC_TRST, + FFC_TXPWDNB_0 => FFC_TXPWDNB_0, + FFC_TXPWDNB_1 => FFC_TXPWDNB_1, + FFC_TXPWDNB_2 => FFC_TXPWDNB_2, + FFC_TXPWDNB_3 => FFC_TXPWDNB_3, + FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, + FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, + FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, + FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, + FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, + FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, + FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, + FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, + FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, + FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, + FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, + FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, + FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, + FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, + FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, + FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, + LDR_CORE2TX_0 => LDR_CORE2TX_0, + LDR_CORE2TX_1 => LDR_CORE2TX_1, + LDR_CORE2TX_2 => LDR_CORE2TX_2, + LDR_CORE2TX_3 => LDR_CORE2TX_3, + FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, + FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, + FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, + FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, + PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, + PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, + PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, + PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, + PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, + PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, + PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, + PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, + PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, + PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, + PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, + PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, + PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, + PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, + PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, + PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, + PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, + PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, + PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, + PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, + SCIADDR0 => SCIADDR0, + SCIADDR1 => SCIADDR1, + SCIADDR2 => SCIADDR2, + SCIADDR3 => SCIADDR3, + SCIADDR4 => SCIADDR4, + SCIADDR5 => SCIADDR5, + SCIENAUX => SCIENAUX, + SCIENCH0 => SCIENCH0, + SCIENCH1 => SCIENCH1, + SCIENCH2 => SCIENCH2, + SCIENCH3 => SCIENCH3, + SCIRD => SCIRD, + SCISELAUX => SCISELAUX, + SCISELCH0 => SCISELCH0, + SCISELCH1 => SCISELCH1, + SCISELCH2 => SCISELCH2, + SCISELCH3 => SCISELCH3, + SCIWDATA0 => SCIWDATA0, + SCIWDATA1 => SCIWDATA1, + SCIWDATA2 => SCIWDATA2, + SCIWDATA3 => SCIWDATA3, + SCIWDATA4 => SCIWDATA4, + SCIWDATA5 => SCIWDATA5, + SCIWDATA6 => SCIWDATA6, + SCIWDATA7 => SCIWDATA7, + SCIWSTN => SCIWSTN, + HDOUTN0 => HDOUTN0, + HDOUTN1 => HDOUTN1, + HDOUTN2 => HDOUTN2, + HDOUTN3 => HDOUTN3, + HDOUTP0 => HDOUTP0, + HDOUTP1 => HDOUTP1, + HDOUTP2 => HDOUTP2, + HDOUTP3 => HDOUTP3, + COUT19 => COUT19, + COUT18 => COUT18, + COUT17 => COUT17, + COUT16 => COUT16, + COUT15 => COUT15, + COUT14 => COUT14, + COUT13 => COUT13, + COUT12 => COUT12, + COUT11 => COUT11, + COUT10 => COUT10, + COUT9 => COUT9, + COUT8 => COUT8, + COUT7 => COUT7, + COUT6 => COUT6, + COUT5 => COUT5, + COUT4 => COUT4, + COUT3 => COUT3, + COUT2 => COUT2, + COUT1 => COUT1, + COUT0 => COUT0, + FF_RX_D_0_0 => FF_RX_D_0_0, + FF_RX_D_0_1 => FF_RX_D_0_1, + FF_RX_D_0_2 => FF_RX_D_0_2, + FF_RX_D_0_3 => FF_RX_D_0_3, + FF_RX_D_0_4 => FF_RX_D_0_4, + FF_RX_D_0_5 => FF_RX_D_0_5, + FF_RX_D_0_6 => FF_RX_D_0_6, + FF_RX_D_0_7 => FF_RX_D_0_7, + FF_RX_D_0_8 => FF_RX_D_0_8, + FF_RX_D_0_9 => FF_RX_D_0_9, + FF_RX_D_0_10 => FF_RX_D_0_10, + FF_RX_D_0_11 => FF_RX_D_0_11, + FF_RX_D_0_12 => FF_RX_D_0_12, + FF_RX_D_0_13 => FF_RX_D_0_13, + FF_RX_D_0_14 => FF_RX_D_0_14, + FF_RX_D_0_15 => FF_RX_D_0_15, + FF_RX_D_0_16 => FF_RX_D_0_16, + FF_RX_D_0_17 => FF_RX_D_0_17, + FF_RX_D_0_18 => FF_RX_D_0_18, + FF_RX_D_0_19 => FF_RX_D_0_19, + FF_RX_D_0_20 => FF_RX_D_0_20, + FF_RX_D_0_21 => FF_RX_D_0_21, + FF_RX_D_0_22 => FF_RX_D_0_22, + FF_RX_D_0_23 => FF_RX_D_0_23, + FF_RX_D_1_0 => FF_RX_D_1_0, + FF_RX_D_1_1 => FF_RX_D_1_1, + FF_RX_D_1_2 => FF_RX_D_1_2, + FF_RX_D_1_3 => FF_RX_D_1_3, + FF_RX_D_1_4 => FF_RX_D_1_4, + FF_RX_D_1_5 => FF_RX_D_1_5, + FF_RX_D_1_6 => FF_RX_D_1_6, + FF_RX_D_1_7 => FF_RX_D_1_7, + FF_RX_D_1_8 => FF_RX_D_1_8, + FF_RX_D_1_9 => FF_RX_D_1_9, + FF_RX_D_1_10 => FF_RX_D_1_10, + FF_RX_D_1_11 => FF_RX_D_1_11, + FF_RX_D_1_12 => FF_RX_D_1_12, + FF_RX_D_1_13 => FF_RX_D_1_13, + FF_RX_D_1_14 => FF_RX_D_1_14, + FF_RX_D_1_15 => FF_RX_D_1_15, + FF_RX_D_1_16 => FF_RX_D_1_16, + FF_RX_D_1_17 => FF_RX_D_1_17, + FF_RX_D_1_18 => FF_RX_D_1_18, + FF_RX_D_1_19 => FF_RX_D_1_19, + FF_RX_D_1_20 => FF_RX_D_1_20, + FF_RX_D_1_21 => FF_RX_D_1_21, + FF_RX_D_1_22 => FF_RX_D_1_22, + FF_RX_D_1_23 => FF_RX_D_1_23, + FF_RX_D_2_0 => FF_RX_D_2_0, + FF_RX_D_2_1 => FF_RX_D_2_1, + FF_RX_D_2_2 => FF_RX_D_2_2, + FF_RX_D_2_3 => FF_RX_D_2_3, + FF_RX_D_2_4 => FF_RX_D_2_4, + FF_RX_D_2_5 => FF_RX_D_2_5, + FF_RX_D_2_6 => FF_RX_D_2_6, + FF_RX_D_2_7 => FF_RX_D_2_7, + FF_RX_D_2_8 => FF_RX_D_2_8, + FF_RX_D_2_9 => FF_RX_D_2_9, + FF_RX_D_2_10 => FF_RX_D_2_10, + FF_RX_D_2_11 => FF_RX_D_2_11, + FF_RX_D_2_12 => FF_RX_D_2_12, + FF_RX_D_2_13 => FF_RX_D_2_13, + FF_RX_D_2_14 => FF_RX_D_2_14, + FF_RX_D_2_15 => FF_RX_D_2_15, + FF_RX_D_2_16 => FF_RX_D_2_16, + FF_RX_D_2_17 => FF_RX_D_2_17, + FF_RX_D_2_18 => FF_RX_D_2_18, + FF_RX_D_2_19 => FF_RX_D_2_19, + FF_RX_D_2_20 => FF_RX_D_2_20, + FF_RX_D_2_21 => FF_RX_D_2_21, + FF_RX_D_2_22 => FF_RX_D_2_22, + FF_RX_D_2_23 => FF_RX_D_2_23, + FF_RX_D_3_0 => FF_RX_D_3_0, + FF_RX_D_3_1 => FF_RX_D_3_1, + FF_RX_D_3_2 => FF_RX_D_3_2, + FF_RX_D_3_3 => FF_RX_D_3_3, + FF_RX_D_3_4 => FF_RX_D_3_4, + FF_RX_D_3_5 => FF_RX_D_3_5, + FF_RX_D_3_6 => FF_RX_D_3_6, + FF_RX_D_3_7 => FF_RX_D_3_7, + FF_RX_D_3_8 => FF_RX_D_3_8, + FF_RX_D_3_9 => FF_RX_D_3_9, + FF_RX_D_3_10 => FF_RX_D_3_10, + FF_RX_D_3_11 => FF_RX_D_3_11, + FF_RX_D_3_12 => FF_RX_D_3_12, + FF_RX_D_3_13 => FF_RX_D_3_13, + FF_RX_D_3_14 => FF_RX_D_3_14, + FF_RX_D_3_15 => FF_RX_D_3_15, + FF_RX_D_3_16 => FF_RX_D_3_16, + FF_RX_D_3_17 => FF_RX_D_3_17, + FF_RX_D_3_18 => FF_RX_D_3_18, + FF_RX_D_3_19 => FF_RX_D_3_19, + FF_RX_D_3_20 => FF_RX_D_3_20, + FF_RX_D_3_21 => FF_RX_D_3_21, + FF_RX_D_3_22 => FF_RX_D_3_22, + FF_RX_D_3_23 => FF_RX_D_3_23, + FF_RX_F_CLK_0 => FF_RX_F_CLK_0, + FF_RX_F_CLK_1 => FF_RX_F_CLK_1, + FF_RX_F_CLK_2 => FF_RX_F_CLK_2, + FF_RX_F_CLK_3 => FF_RX_F_CLK_3, + FF_RX_H_CLK_0 => FF_RX_H_CLK_0, + FF_RX_H_CLK_1 => FF_RX_H_CLK_1, + FF_RX_H_CLK_2 => FF_RX_H_CLK_2, + FF_RX_H_CLK_3 => FF_RX_H_CLK_3, + FF_TX_F_CLK_0 => FF_TX_F_CLK_0, + FF_TX_F_CLK_1 => FF_TX_F_CLK_1, + FF_TX_F_CLK_2 => FF_TX_F_CLK_2, + FF_TX_F_CLK_3 => FF_TX_F_CLK_3, + FF_TX_H_CLK_0 => FF_TX_H_CLK_0, + FF_TX_H_CLK_1 => FF_TX_H_CLK_1, + FF_TX_H_CLK_2 => FF_TX_H_CLK_2, + FF_TX_H_CLK_3 => FF_TX_H_CLK_3, + FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, + FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, + FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, + FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, + FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, + FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, + FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, + FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, + FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, + FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, + FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, + FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, + FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, + FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, + FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, + FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, + FFS_PCIE_CON_0 => FFS_PCIE_CON_0, + FFS_PCIE_CON_1 => FFS_PCIE_CON_1, + FFS_PCIE_CON_2 => FFS_PCIE_CON_2, + FFS_PCIE_CON_3 => FFS_PCIE_CON_3, + FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, + FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, + FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, + FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, + FFS_PLOL => FFS_PLOL, + FFS_RLOL_0 => FFS_RLOL_0, + FFS_RLOL_1 => FFS_RLOL_1, + FFS_RLOL_2 => FFS_RLOL_2, + FFS_RLOL_3 => FFS_RLOL_3, + FFS_RLOS_HI_0 => FFS_RLOS_HI_0, + FFS_RLOS_HI_1 => FFS_RLOS_HI_1, + FFS_RLOS_HI_2 => FFS_RLOS_HI_2, + FFS_RLOS_HI_3 => FFS_RLOS_HI_3, + FFS_RLOS_LO_0 => FFS_RLOS_LO_0, + FFS_RLOS_LO_1 => FFS_RLOS_LO_1, + FFS_RLOS_LO_2 => FFS_RLOS_LO_2, + FFS_RLOS_LO_3 => FFS_RLOS_LO_3, + FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, + FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, + FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, + FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, + FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, + FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, + FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, + FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, + PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, + PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, + PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, + PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, + PCIE_RXVALID_0 => PCIE_RXVALID_0, + PCIE_RXVALID_1 => PCIE_RXVALID_1, + PCIE_RXVALID_2 => PCIE_RXVALID_2, + PCIE_RXVALID_3 => PCIE_RXVALID_3, + FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, + FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, + FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, + FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, + FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, + FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, + FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, + FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, + LDR_RX2CORE_0 => LDR_RX2CORE_0, + LDR_RX2CORE_1 => LDR_RX2CORE_1, + LDR_RX2CORE_2 => LDR_RX2CORE_2, + LDR_RX2CORE_3 => LDR_RX2CORE_3, + REFCK2CORE => REFCK2CORE, + SCIINT => SCIINT, + SCIRDATA0 => SCIRDATA0, + SCIRDATA1 => SCIRDATA1, + SCIRDATA2 => SCIRDATA2, + SCIRDATA3 => SCIRDATA3, + SCIRDATA4 => SCIRDATA4, + SCIRDATA5 => SCIRDATA5, + SCIRDATA6 => SCIRDATA6, + SCIRDATA7 => SCIRDATA7, + REFCLK_FROM_NQ => REFCLK_FROM_NQ, + REFCLK_TO_NQ => REFCLK_TO_NQ + ); + +end PCSD_arch; + +--synopsys translate_on + +--THIS MODULE IS INSTANTIATED PER RX CHANNEL +--Reset Sequence Generator +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity rx_reset_sm is +generic (count_index: integer :=18); +port ( + rst_n : in std_logic; + refclkdiv2 : in std_logic; + tx_pll_lol_qd_s : in std_logic; + rx_serdes_rst_ch_c: out std_logic; + rx_cdr_lol_ch_s : in std_logic; + rx_los_low_ch_s : in std_logic; + rx_pcs_rst_ch_c : out std_logic +); +end rx_reset_sm ; + +architecture rx_reset_sm_arch of rx_reset_sm is + +type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL); + +signal cs: statetype; -- current state of lsm +signal ns: statetype; -- next state of lsm + +signal tx_pll_lol_qd_s_int: std_logic; +signal rx_los_low_int: std_logic; +signal plol_los_int: std_logic; +signal rx_lol_los : std_logic; +signal rx_lol_los_int: std_logic; +signal rx_lol_los_del: std_logic; +signal rx_pcs_rst_ch_c_int: std_logic; +signal rx_serdes_rst_ch_c_int: std_logic; + +signal reset_timer1: std_logic; +signal reset_timer2: std_logic; + +signal counter1: std_logic_vector(1 downto 0); +signal TIMER1: std_logic; + +signal counter2: std_logic_vector(18 downto 0); +signal TIMER2 : std_logic; + +begin + +rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ; + +process(refclkdiv2,rst_n) +begin + if rising_edge(refclkdiv2) then + if rst_n = '0' then + cs <= WAIT_FOR_PLOL; + rx_lol_los_int <= '1'; + rx_lol_los_del <= '1'; + tx_pll_lol_qd_s_int <= '1'; + rx_pcs_rst_ch_c <= '1'; + rx_serdes_rst_ch_c <= '0'; + rx_los_low_int <= '1'; + else + cs <= ns; + rx_lol_los_del <= rx_lol_los; + rx_lol_los_int <= rx_lol_los_del; + tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; + rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int; + rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int; + rx_los_low_int <= rx_los_low_ch_s; + end if; + end if; +end process; + +--TIMER1 = 3NS; +--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles +--A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1] + +process(refclkdiv2, reset_timer1) +begin + if rising_edge(refclkdiv2) then + if reset_timer1 = '1' then + counter1 <= "00"; + TIMER1 <= '0'; + else + if counter1(1) = '1' then + TIMER1 <='1'; + else + TIMER1 <='0'; + counter1 <= counter1 + 1 ; + end if; + end if; + end if; +end process; + +--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles +--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] + +process(refclkdiv2, reset_timer2) +begin + if rising_edge(refclkdiv2) then + if reset_timer2 = '1' then + counter2 <= "0000000000000000000"; + TIMER2 <= '0'; + else + if counter2(count_index) = '1' then + TIMER2 <='1'; + else + TIMER2 <='0'; + counter2 <= counter2 + 1 ; + end if; + end if; + end if; +end process; + + +process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2) +begin + reset_timer1 <= '0'; + reset_timer2 <= '0'; + + case cs is + when WAIT_FOR_PLOL => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '0'; + if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal + ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next + else + ns <= RX_SERDES_RESET; + end if; + + when RX_SERDES_RESET => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '1'; + reset_timer1 <= '1'; + ns <= WAIT_FOR_TIMER1; + + + when WAIT_FOR_TIMER1 => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '1'; + if TIMER1 = '1' then + ns <= CHECK_LOL_LOS; + else + ns <= WAIT_FOR_TIMER1; + end if; + + when CHECK_LOL_LOS => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '0'; + reset_timer2 <= '1'; + ns <= WAIT_FOR_TIMER2; + + when WAIT_FOR_TIMER2 => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '0'; + if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES + if TIMER2 = '1' then + if rx_lol_los_int = '1' then + ns <= WAIT_FOR_PLOL; + else + ns <= NORMAL; + end if; + else + ns <= WAIT_FOR_TIMER2; + end if; + else + ns <= CHECK_LOL_LOS; --RESET TIMER2 + end if; + + when NORMAL => + rx_pcs_rst_ch_c_int <= '0'; + rx_serdes_rst_ch_c_int <= '0'; + if rx_lol_los_int = '1' then + ns <= WAIT_FOR_PLOL; + else + ns <= NORMAL; + end if; + + when others => + ns <= WAIT_FOR_PLOL; + + end case; + +end process; + + +end rx_reset_sm_arch; + +--THIS MODULE IS INSTANTIATED PER TX QUAD +--TX Reset Sequence state machine-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity tx_reset_sm is +generic (count_index: integer :=18); +port ( + rst_n : in std_logic; + refclkdiv2 : in std_logic; + tx_pll_lol_qd_s : in std_logic; + rst_qd_c : out std_logic; + tx_pcs_rst_ch_c : out std_logic + ); +end tx_reset_sm; + +architecture tx_reset_sm_arch of tx_reset_sm is + +type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL); + +signal cs: statetype; -- current state of lsm +signal ns: statetype; -- next state of lsm + +signal tx_pll_lol_qd_s_int : std_logic; +signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0); +signal rst_qd_c_int : std_logic; + +signal reset_timer1: std_logic; +signal reset_timer2: std_logic; + +signal counter1: std_logic_vector(2 downto 0); +signal TIMER1: std_logic; + +signal counter2: std_logic_vector(18 downto 0); +signal TIMER2: std_logic; + +begin + +process (refclkdiv2, rst_n) +begin + if rst_n = '0' then + cs <= QUAD_RESET; + tx_pll_lol_qd_s_int <= '1'; + tx_pcs_rst_ch_c <= '1'; + rst_qd_c <= '1'; + else if rising_edge(refclkdiv2) then + cs <= ns; + tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; + tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0); + rst_qd_c <= rst_qd_c_int; + end if; + end if; +end process; +--TIMER1 = 20ns; +--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles +-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] + + +process (refclkdiv2, reset_timer1) +begin + if rising_edge(refclkdiv2) then + if reset_timer1 = '1' then + counter1 <= "000"; + TIMER1 <= '0'; + else + if counter1(2) = '1' then + TIMER1 <= '1'; + else + TIMER1 <='0'; + counter1 <= counter1 + 1 ; + end if; + end if; + end if; +end process; + + +--TIMER2 = 1,400,000 UI; +--WORST CASE CYCLES is with smallest multipier factor. +-- This would be with X8 clock multiplier in DIV2 mode +-- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES +-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES +-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] + + +process(refclkdiv2, reset_timer2) +begin + if rising_edge(refclkdiv2) then + if reset_timer2 = '1' then + counter2 <= "0000000000000000000"; + TIMER2 <= '0'; + else + if counter2(count_index) = '1' then + TIMER2 <='1'; + else + TIMER2 <='0'; + counter2 <= counter2 + 1 ; + end if; + end if; + end if; +end process; + +process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int) +begin + + reset_timer1 <= '0'; + reset_timer2 <= '0'; + + case cs is + + when QUAD_RESET => + tx_pcs_rst_ch_c_int <= "1111"; + rst_qd_c_int <= '1'; + reset_timer1 <= '1'; + ns <= WAIT_FOR_TIMER1; + + when WAIT_FOR_TIMER1 => + tx_pcs_rst_ch_c_int <= "1111"; + rst_qd_c_int <= '1'; + if TIMER1 = '1' then + ns <= CHECK_PLOL; + else + ns <= WAIT_FOR_TIMER1; + end if; + + when CHECK_PLOL => + tx_pcs_rst_ch_c_int <= "1111"; + rst_qd_c_int <= '0'; + reset_timer2 <= '1'; + ns <= WAIT_FOR_TIMER2; + + when WAIT_FOR_TIMER2 => + tx_pcs_rst_ch_c_int <= "1111"; + rst_qd_c_int <= '0'; + if TIMER2 = '1' then + if tx_pll_lol_qd_s_int = '1' then + ns <= QUAD_RESET; + else + ns <= NORMAL; + end if; + else + ns <= WAIT_FOR_TIMER2; + end if; + + when NORMAL => + tx_pcs_rst_ch_c_int <= "0000"; + rst_qd_c_int <= '0'; + if tx_pll_lol_qd_s_int = '1' then + ns <= QUAD_RESET; + else + ns <= NORMAL; + end if; + + when others => + ns <= QUAD_RESET; + + end case; + +end process; + +end tx_reset_sm_arch; + + +--synopsys translate_off +library ECP3; +use ECP3.components.all; +--synopsys translate_on + + +library IEEE, STD; +use IEEE.std_logic_1164.all; +use STD.TEXTIO.all; + +entity sfp_0_200_int is + GENERIC (USER_CONFIG_FILE : String := "sfp_0_200_int.txt"); + port ( +------------------ +-- CH0 -- + hdinp_ch0, hdinn_ch0 : in std_logic; + hdoutp_ch0, hdoutn_ch0 : out std_logic; + sci_sel_ch0 : in std_logic; + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + fpga_rxrefclk_ch0 : in std_logic; + txdata_ch0 : in std_logic_vector (15 downto 0); + tx_k_ch0 : in std_logic_vector (1 downto 0); + tx_force_disp_ch0 : in std_logic_vector (1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector (1 downto 0); + rxdata_ch0 : out std_logic_vector (15 downto 0); + rx_k_ch0 : out std_logic_vector (1 downto 0); + rx_disp_err_ch0 : out std_logic_vector (1 downto 0); + rx_cv_err_ch0 : out std_logic_vector (1 downto 0); + sb_felb_ch0_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + rx_los_low_ch0_s : out std_logic; + lsm_status_ch0_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; +-- CH1 -- +-- CH2 -- +-- CH3 -- +---- Miscillaneous ports + sci_wrdata : in std_logic_vector (7 downto 0); + sci_addr : in std_logic_vector (5 downto 0); + sci_rddata : out std_logic_vector (7 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic); + +end sfp_0_200_int; + + +architecture sfp_0_200_int_arch of sfp_0_200_int is + +component VLO +port ( + Z : out std_logic); +end component; + +component VHI +port ( + Z : out std_logic); +end component; + +component rx_reset_sm +generic (count_index: integer :=18); +port ( + rst_n : in std_logic; + refclkdiv2 : in std_logic; + tx_pll_lol_qd_s : in std_logic; + rx_serdes_rst_ch_c: out std_logic; + rx_cdr_lol_ch_s : in std_logic; + rx_los_low_ch_s : in std_logic; + rx_pcs_rst_ch_c : out std_logic +); +end component ; + +component tx_reset_sm +generic (count_index: integer :=18); +port ( + rst_n : in std_logic; + refclkdiv2 : in std_logic; + tx_pll_lol_qd_s : in std_logic; + rst_qd_c : out std_logic; + tx_pcs_rst_ch_c : out std_logic + ); +end component; + +component PCSD +--synopsys translate_off +GENERIC( + CONFIG_FILE : String; + QUAD_MODE : String; + CH0_CDR_SRC : String := "REFCLK_EXT"; + CH1_CDR_SRC : String := "REFCLK_EXT"; + CH2_CDR_SRC : String := "REFCLK_EXT"; + CH3_CDR_SRC : String := "REFCLK_EXT"; + PLL_SRC : String + ); +--synopsys translate_on +port ( + HDINN0 : in std_logic; + HDINN1 : in std_logic; + HDINN2 : in std_logic; + HDINN3 : in std_logic; + HDINP0 : in std_logic; + HDINP1 : in std_logic; + HDINP2 : in std_logic; + HDINP3 : in std_logic; + REFCLKN : in std_logic; + REFCLKP : in std_logic; + CIN0 : in std_logic; + CIN1 : in std_logic; + CIN2 : in std_logic; + CIN3 : in std_logic; + CIN4 : in std_logic; + CIN5 : in std_logic; + CIN6 : in std_logic; + CIN7 : in std_logic; + CIN8 : in std_logic; + CIN9 : in std_logic; + CIN10 : in std_logic; + CIN11 : in std_logic; + CYAWSTN : in std_logic; + FF_EBRD_CLK_0 : in std_logic; + FF_EBRD_CLK_1 : in std_logic; + FF_EBRD_CLK_2 : in std_logic; + FF_EBRD_CLK_3 : in std_logic; + FF_RXI_CLK_0 : in std_logic; + FF_RXI_CLK_1 : in std_logic; + FF_RXI_CLK_2 : in std_logic; + FF_RXI_CLK_3 : in std_logic; + FF_TX_D_0_0 : in std_logic; + FF_TX_D_0_1 : in std_logic; + FF_TX_D_0_2 : in std_logic; + FF_TX_D_0_3 : in std_logic; + FF_TX_D_0_4 : in std_logic; + FF_TX_D_0_5 : in std_logic; + FF_TX_D_0_6 : in std_logic; + FF_TX_D_0_7 : in std_logic; + FF_TX_D_0_8 : in std_logic; + FF_TX_D_0_9 : in std_logic; + FF_TX_D_0_10 : in std_logic; + FF_TX_D_0_11 : in std_logic; + FF_TX_D_0_12 : in std_logic; + FF_TX_D_0_13 : in std_logic; + FF_TX_D_0_14 : in std_logic; + FF_TX_D_0_15 : in std_logic; + FF_TX_D_0_16 : in std_logic; + FF_TX_D_0_17 : in std_logic; + FF_TX_D_0_18 : in std_logic; + FF_TX_D_0_19 : in std_logic; + FF_TX_D_0_20 : in std_logic; + FF_TX_D_0_21 : in std_logic; + FF_TX_D_0_22 : in std_logic; + FF_TX_D_0_23 : in std_logic; + FF_TX_D_1_0 : in std_logic; + FF_TX_D_1_1 : in std_logic; + FF_TX_D_1_2 : in std_logic; + FF_TX_D_1_3 : in std_logic; + FF_TX_D_1_4 : in std_logic; + FF_TX_D_1_5 : in std_logic; + FF_TX_D_1_6 : in std_logic; + FF_TX_D_1_7 : in std_logic; + FF_TX_D_1_8 : in std_logic; + FF_TX_D_1_9 : in std_logic; + FF_TX_D_1_10 : in std_logic; + FF_TX_D_1_11 : in std_logic; + FF_TX_D_1_12 : in std_logic; + FF_TX_D_1_13 : in std_logic; + FF_TX_D_1_14 : in std_logic; + FF_TX_D_1_15 : in std_logic; + FF_TX_D_1_16 : in std_logic; + FF_TX_D_1_17 : in std_logic; + FF_TX_D_1_18 : in std_logic; + FF_TX_D_1_19 : in std_logic; + FF_TX_D_1_20 : in std_logic; + FF_TX_D_1_21 : in std_logic; + FF_TX_D_1_22 : in std_logic; + FF_TX_D_1_23 : in std_logic; + FF_TX_D_2_0 : in std_logic; + FF_TX_D_2_1 : in std_logic; + FF_TX_D_2_2 : in std_logic; + FF_TX_D_2_3 : in std_logic; + FF_TX_D_2_4 : in std_logic; + FF_TX_D_2_5 : in std_logic; + FF_TX_D_2_6 : in std_logic; + FF_TX_D_2_7 : in std_logic; + FF_TX_D_2_8 : in std_logic; + FF_TX_D_2_9 : in std_logic; + FF_TX_D_2_10 : in std_logic; + FF_TX_D_2_11 : in std_logic; + FF_TX_D_2_12 : in std_logic; + FF_TX_D_2_13 : in std_logic; + FF_TX_D_2_14 : in std_logic; + FF_TX_D_2_15 : in std_logic; + FF_TX_D_2_16 : in std_logic; + FF_TX_D_2_17 : in std_logic; + FF_TX_D_2_18 : in std_logic; + FF_TX_D_2_19 : in std_logic; + FF_TX_D_2_20 : in std_logic; + FF_TX_D_2_21 : in std_logic; + FF_TX_D_2_22 : in std_logic; + FF_TX_D_2_23 : in std_logic; + FF_TX_D_3_0 : in std_logic; + FF_TX_D_3_1 : in std_logic; + FF_TX_D_3_2 : in std_logic; + FF_TX_D_3_3 : in std_logic; + FF_TX_D_3_4 : in std_logic; + FF_TX_D_3_5 : in std_logic; + FF_TX_D_3_6 : in std_logic; + FF_TX_D_3_7 : in std_logic; + FF_TX_D_3_8 : in std_logic; + FF_TX_D_3_9 : in std_logic; + FF_TX_D_3_10 : in std_logic; + FF_TX_D_3_11 : in std_logic; + FF_TX_D_3_12 : in std_logic; + FF_TX_D_3_13 : in std_logic; + FF_TX_D_3_14 : in std_logic; + FF_TX_D_3_15 : in std_logic; + FF_TX_D_3_16 : in std_logic; + FF_TX_D_3_17 : in std_logic; + FF_TX_D_3_18 : in std_logic; + FF_TX_D_3_19 : in std_logic; + FF_TX_D_3_20 : in std_logic; + FF_TX_D_3_21 : in std_logic; + FF_TX_D_3_22 : in std_logic; + FF_TX_D_3_23 : in std_logic; + FF_TXI_CLK_0 : in std_logic; + FF_TXI_CLK_1 : in std_logic; + FF_TXI_CLK_2 : in std_logic; + FF_TXI_CLK_3 : in std_logic; + FFC_CK_CORE_RX_0 : in std_logic; + FFC_CK_CORE_RX_1 : in std_logic; + FFC_CK_CORE_RX_2 : in std_logic; + FFC_CK_CORE_RX_3 : in std_logic; + FFC_CK_CORE_TX : in std_logic; + FFC_EI_EN_0 : in std_logic; + FFC_EI_EN_1 : in std_logic; + FFC_EI_EN_2 : in std_logic; + FFC_EI_EN_3 : in std_logic; + FFC_ENABLE_CGALIGN_0 : in std_logic; + FFC_ENABLE_CGALIGN_1 : in std_logic; + FFC_ENABLE_CGALIGN_2 : in std_logic; + FFC_ENABLE_CGALIGN_3 : in std_logic; + FFC_FB_LOOPBACK_0 : in std_logic; + FFC_FB_LOOPBACK_1 : in std_logic; + FFC_FB_LOOPBACK_2 : in std_logic; + FFC_FB_LOOPBACK_3 : in std_logic; + FFC_LANE_RX_RST_0 : in std_logic; + FFC_LANE_RX_RST_1 : in std_logic; + FFC_LANE_RX_RST_2 : in std_logic; + FFC_LANE_RX_RST_3 : in std_logic; + FFC_LANE_TX_RST_0 : in std_logic; + FFC_LANE_TX_RST_1 : in std_logic; + FFC_LANE_TX_RST_2 : in std_logic; + FFC_LANE_TX_RST_3 : in std_logic; + FFC_MACRO_RST : in std_logic; + FFC_PCI_DET_EN_0 : in std_logic; + FFC_PCI_DET_EN_1 : in std_logic; + FFC_PCI_DET_EN_2 : in std_logic; + FFC_PCI_DET_EN_3 : in std_logic; + FFC_PCIE_CT_0 : in std_logic; + FFC_PCIE_CT_1 : in std_logic; + FFC_PCIE_CT_2 : in std_logic; + FFC_PCIE_CT_3 : in std_logic; + FFC_PFIFO_CLR_0 : in std_logic; + FFC_PFIFO_CLR_1 : in std_logic; + FFC_PFIFO_CLR_2 : in std_logic; + FFC_PFIFO_CLR_3 : in std_logic; + FFC_QUAD_RST : in std_logic; + FFC_RRST_0 : in std_logic; + FFC_RRST_1 : in std_logic; + FFC_RRST_2 : in std_logic; + FFC_RRST_3 : in std_logic; + FFC_RXPWDNB_0 : in std_logic; + FFC_RXPWDNB_1 : in std_logic; + FFC_RXPWDNB_2 : in std_logic; + FFC_RXPWDNB_3 : in std_logic; + FFC_SB_INV_RX_0 : in std_logic; + FFC_SB_INV_RX_1 : in std_logic; + FFC_SB_INV_RX_2 : in std_logic; + FFC_SB_INV_RX_3 : in std_logic; + FFC_SB_PFIFO_LP_0 : in std_logic; + FFC_SB_PFIFO_LP_1 : in std_logic; + FFC_SB_PFIFO_LP_2 : in std_logic; + FFC_SB_PFIFO_LP_3 : in std_logic; + FFC_SIGNAL_DETECT_0 : in std_logic; + FFC_SIGNAL_DETECT_1 : in std_logic; + FFC_SIGNAL_DETECT_2 : in std_logic; + FFC_SIGNAL_DETECT_3 : in std_logic; + FFC_SYNC_TOGGLE : in std_logic; + FFC_TRST : in std_logic; + FFC_TXPWDNB_0 : in std_logic; + FFC_TXPWDNB_1 : in std_logic; + FFC_TXPWDNB_2 : in std_logic; + FFC_TXPWDNB_3 : in std_logic; + FFC_RATE_MODE_RX_0 : in std_logic; + FFC_RATE_MODE_RX_1 : in std_logic; + FFC_RATE_MODE_RX_2 : in std_logic; + FFC_RATE_MODE_RX_3 : in std_logic; + FFC_RATE_MODE_TX_0 : in std_logic; + FFC_RATE_MODE_TX_1 : in std_logic; + FFC_RATE_MODE_TX_2 : in std_logic; + FFC_RATE_MODE_TX_3 : in std_logic; + FFC_DIV11_MODE_RX_0 : in std_logic; + FFC_DIV11_MODE_RX_1 : in std_logic; + FFC_DIV11_MODE_RX_2 : in std_logic; + FFC_DIV11_MODE_RX_3 : in std_logic; + FFC_DIV11_MODE_TX_0 : in std_logic; + FFC_DIV11_MODE_TX_1 : in std_logic; + FFC_DIV11_MODE_TX_2 : in std_logic; + FFC_DIV11_MODE_TX_3 : in std_logic; + LDR_CORE2TX_0 : in std_logic; + LDR_CORE2TX_1 : in std_logic; + LDR_CORE2TX_2 : in std_logic; + LDR_CORE2TX_3 : in std_logic; + FFC_LDR_CORE2TX_EN_0 : in std_logic; + FFC_LDR_CORE2TX_EN_1 : in std_logic; + FFC_LDR_CORE2TX_EN_2 : in std_logic; + FFC_LDR_CORE2TX_EN_3 : in std_logic; + PCIE_POWERDOWN_0_0 : in std_logic; + PCIE_POWERDOWN_0_1 : in std_logic; + PCIE_POWERDOWN_1_0 : in std_logic; + PCIE_POWERDOWN_1_1 : in std_logic; + PCIE_POWERDOWN_2_0 : in std_logic; + PCIE_POWERDOWN_2_1 : in std_logic; + PCIE_POWERDOWN_3_0 : in std_logic; + PCIE_POWERDOWN_3_1 : in std_logic; + PCIE_RXPOLARITY_0 : in std_logic; + PCIE_RXPOLARITY_1 : in std_logic; + PCIE_RXPOLARITY_2 : in std_logic; + PCIE_RXPOLARITY_3 : in std_logic; + PCIE_TXCOMPLIANCE_0 : in std_logic; + PCIE_TXCOMPLIANCE_1 : in std_logic; + PCIE_TXCOMPLIANCE_2 : in std_logic; + PCIE_TXCOMPLIANCE_3 : in std_logic; + PCIE_TXDETRX_PR2TLB_0 : in std_logic; + PCIE_TXDETRX_PR2TLB_1 : in std_logic; + PCIE_TXDETRX_PR2TLB_2 : in std_logic; + PCIE_TXDETRX_PR2TLB_3 : in std_logic; + SCIADDR0 : in std_logic; + SCIADDR1 : in std_logic; + SCIADDR2 : in std_logic; + SCIADDR3 : in std_logic; + SCIADDR4 : in std_logic; + SCIADDR5 : in std_logic; + SCIENAUX : in std_logic; + SCIENCH0 : in std_logic; + SCIENCH1 : in std_logic; + SCIENCH2 : in std_logic; + SCIENCH3 : in std_logic; + SCIRD : in std_logic; + SCISELAUX : in std_logic; + SCISELCH0 : in std_logic; + SCISELCH1 : in std_logic; + SCISELCH2 : in std_logic; + SCISELCH3 : in std_logic; + SCIWDATA0 : in std_logic; + SCIWDATA1 : in std_logic; + SCIWDATA2 : in std_logic; + SCIWDATA3 : in std_logic; + SCIWDATA4 : in std_logic; + SCIWDATA5 : in std_logic; + SCIWDATA6 : in std_logic; + SCIWDATA7 : in std_logic; + SCIWSTN : in std_logic; + REFCLK_FROM_NQ : in std_logic; + HDOUTN0 : out std_logic; + HDOUTN1 : out std_logic; + HDOUTN2 : out std_logic; + HDOUTN3 : out std_logic; + HDOUTP0 : out std_logic; + HDOUTP1 : out std_logic; + HDOUTP2 : out std_logic; + HDOUTP3 : out std_logic; + COUT0 : out std_logic; + COUT1 : out std_logic; + COUT2 : out std_logic; + COUT3 : out std_logic; + COUT4 : out std_logic; + COUT5 : out std_logic; + COUT6 : out std_logic; + COUT7 : out std_logic; + COUT8 : out std_logic; + COUT9 : out std_logic; + COUT10 : out std_logic; + COUT11 : out std_logic; + COUT12 : out std_logic; + COUT13 : out std_logic; + COUT14 : out std_logic; + COUT15 : out std_logic; + COUT16 : out std_logic; + COUT17 : out std_logic; + COUT18 : out std_logic; + COUT19 : out std_logic; + FF_RX_D_0_0 : out std_logic; + FF_RX_D_0_1 : out std_logic; + FF_RX_D_0_2 : out std_logic; + FF_RX_D_0_3 : out std_logic; + FF_RX_D_0_4 : out std_logic; + FF_RX_D_0_5 : out std_logic; + FF_RX_D_0_6 : out std_logic; + FF_RX_D_0_7 : out std_logic; + FF_RX_D_0_8 : out std_logic; + FF_RX_D_0_9 : out std_logic; + FF_RX_D_0_10 : out std_logic; + FF_RX_D_0_11 : out std_logic; + FF_RX_D_0_12 : out std_logic; + FF_RX_D_0_13 : out std_logic; + FF_RX_D_0_14 : out std_logic; + FF_RX_D_0_15 : out std_logic; + FF_RX_D_0_16 : out std_logic; + FF_RX_D_0_17 : out std_logic; + FF_RX_D_0_18 : out std_logic; + FF_RX_D_0_19 : out std_logic; + FF_RX_D_0_20 : out std_logic; + FF_RX_D_0_21 : out std_logic; + FF_RX_D_0_22 : out std_logic; + FF_RX_D_0_23 : out std_logic; + FF_RX_D_1_0 : out std_logic; + FF_RX_D_1_1 : out std_logic; + FF_RX_D_1_2 : out std_logic; + FF_RX_D_1_3 : out std_logic; + FF_RX_D_1_4 : out std_logic; + FF_RX_D_1_5 : out std_logic; + FF_RX_D_1_6 : out std_logic; + FF_RX_D_1_7 : out std_logic; + FF_RX_D_1_8 : out std_logic; + FF_RX_D_1_9 : out std_logic; + FF_RX_D_1_10 : out std_logic; + FF_RX_D_1_11 : out std_logic; + FF_RX_D_1_12 : out std_logic; + FF_RX_D_1_13 : out std_logic; + FF_RX_D_1_14 : out std_logic; + FF_RX_D_1_15 : out std_logic; + FF_RX_D_1_16 : out std_logic; + FF_RX_D_1_17 : out std_logic; + FF_RX_D_1_18 : out std_logic; + FF_RX_D_1_19 : out std_logic; + FF_RX_D_1_20 : out std_logic; + FF_RX_D_1_21 : out std_logic; + FF_RX_D_1_22 : out std_logic; + FF_RX_D_1_23 : out std_logic; + FF_RX_D_2_0 : out std_logic; + FF_RX_D_2_1 : out std_logic; + FF_RX_D_2_2 : out std_logic; + FF_RX_D_2_3 : out std_logic; + FF_RX_D_2_4 : out std_logic; + FF_RX_D_2_5 : out std_logic; + FF_RX_D_2_6 : out std_logic; + FF_RX_D_2_7 : out std_logic; + FF_RX_D_2_8 : out std_logic; + FF_RX_D_2_9 : out std_logic; + FF_RX_D_2_10 : out std_logic; + FF_RX_D_2_11 : out std_logic; + FF_RX_D_2_12 : out std_logic; + FF_RX_D_2_13 : out std_logic; + FF_RX_D_2_14 : out std_logic; + FF_RX_D_2_15 : out std_logic; + FF_RX_D_2_16 : out std_logic; + FF_RX_D_2_17 : out std_logic; + FF_RX_D_2_18 : out std_logic; + FF_RX_D_2_19 : out std_logic; + FF_RX_D_2_20 : out std_logic; + FF_RX_D_2_21 : out std_logic; + FF_RX_D_2_22 : out std_logic; + FF_RX_D_2_23 : out std_logic; + FF_RX_D_3_0 : out std_logic; + FF_RX_D_3_1 : out std_logic; + FF_RX_D_3_2 : out std_logic; + FF_RX_D_3_3 : out std_logic; + FF_RX_D_3_4 : out std_logic; + FF_RX_D_3_5 : out std_logic; + FF_RX_D_3_6 : out std_logic; + FF_RX_D_3_7 : out std_logic; + FF_RX_D_3_8 : out std_logic; + FF_RX_D_3_9 : out std_logic; + FF_RX_D_3_10 : out std_logic; + FF_RX_D_3_11 : out std_logic; + FF_RX_D_3_12 : out std_logic; + FF_RX_D_3_13 : out std_logic; + FF_RX_D_3_14 : out std_logic; + FF_RX_D_3_15 : out std_logic; + FF_RX_D_3_16 : out std_logic; + FF_RX_D_3_17 : out std_logic; + FF_RX_D_3_18 : out std_logic; + FF_RX_D_3_19 : out std_logic; + FF_RX_D_3_20 : out std_logic; + FF_RX_D_3_21 : out std_logic; + FF_RX_D_3_22 : out std_logic; + FF_RX_D_3_23 : out std_logic; + FF_RX_F_CLK_0 : out std_logic; + FF_RX_F_CLK_1 : out std_logic; + FF_RX_F_CLK_2 : out std_logic; + FF_RX_F_CLK_3 : out std_logic; + FF_RX_H_CLK_0 : out std_logic; + FF_RX_H_CLK_1 : out std_logic; + FF_RX_H_CLK_2 : out std_logic; + FF_RX_H_CLK_3 : out std_logic; + FF_TX_F_CLK_0 : out std_logic; + FF_TX_F_CLK_1 : out std_logic; + FF_TX_F_CLK_2 : out std_logic; + FF_TX_F_CLK_3 : out std_logic; + FF_TX_H_CLK_0 : out std_logic; + FF_TX_H_CLK_1 : out std_logic; + FF_TX_H_CLK_2 : out std_logic; + FF_TX_H_CLK_3 : out std_logic; + FFS_CC_OVERRUN_0 : out std_logic; + FFS_CC_OVERRUN_1 : out std_logic; + FFS_CC_OVERRUN_2 : out std_logic; + FFS_CC_OVERRUN_3 : out std_logic; + FFS_CC_UNDERRUN_0 : out std_logic; + FFS_CC_UNDERRUN_1 : out std_logic; + FFS_CC_UNDERRUN_2 : out std_logic; + FFS_CC_UNDERRUN_3 : out std_logic; + FFS_LS_SYNC_STATUS_0 : out std_logic; + FFS_LS_SYNC_STATUS_1 : out std_logic; + FFS_LS_SYNC_STATUS_2 : out std_logic; + FFS_LS_SYNC_STATUS_3 : out std_logic; + FFS_CDR_TRAIN_DONE_0 : out std_logic; + FFS_CDR_TRAIN_DONE_1 : out std_logic; + FFS_CDR_TRAIN_DONE_2 : out std_logic; + FFS_CDR_TRAIN_DONE_3 : out std_logic; + FFS_PCIE_CON_0 : out std_logic; + FFS_PCIE_CON_1 : out std_logic; + FFS_PCIE_CON_2 : out std_logic; + FFS_PCIE_CON_3 : out std_logic; + FFS_PCIE_DONE_0 : out std_logic; + FFS_PCIE_DONE_1 : out std_logic; + FFS_PCIE_DONE_2 : out std_logic; + FFS_PCIE_DONE_3 : out std_logic; + FFS_PLOL : out std_logic; + FFS_RLOL_0 : out std_logic; + FFS_RLOL_1 : out std_logic; + FFS_RLOL_2 : out std_logic; + FFS_RLOL_3 : out std_logic; + FFS_RLOS_HI_0 : out std_logic; + FFS_RLOS_HI_1 : out std_logic; + FFS_RLOS_HI_2 : out std_logic; + FFS_RLOS_HI_3 : out std_logic; + FFS_RLOS_LO_0 : out std_logic; + FFS_RLOS_LO_1 : out std_logic; + FFS_RLOS_LO_2 : out std_logic; + FFS_RLOS_LO_3 : out std_logic; + FFS_RXFBFIFO_ERROR_0 : out std_logic; + FFS_RXFBFIFO_ERROR_1 : out std_logic; + FFS_RXFBFIFO_ERROR_2 : out std_logic; + FFS_RXFBFIFO_ERROR_3 : out std_logic; + FFS_TXFBFIFO_ERROR_0 : out std_logic; + FFS_TXFBFIFO_ERROR_1 : out std_logic; + FFS_TXFBFIFO_ERROR_2 : out std_logic; + FFS_TXFBFIFO_ERROR_3 : out std_logic; + PCIE_PHYSTATUS_0 : out std_logic; + PCIE_PHYSTATUS_1 : out std_logic; + PCIE_PHYSTATUS_2 : out std_logic; + PCIE_PHYSTATUS_3 : out std_logic; + PCIE_RXVALID_0 : out std_logic; + PCIE_RXVALID_1 : out std_logic; + PCIE_RXVALID_2 : out std_logic; + PCIE_RXVALID_3 : out std_logic; + FFS_SKP_ADDED_0 : out std_logic; + FFS_SKP_ADDED_1 : out std_logic; + FFS_SKP_ADDED_2 : out std_logic; + FFS_SKP_ADDED_3 : out std_logic; + FFS_SKP_DELETED_0 : out std_logic; + FFS_SKP_DELETED_1 : out std_logic; + FFS_SKP_DELETED_2 : out std_logic; + FFS_SKP_DELETED_3 : out std_logic; + LDR_RX2CORE_0 : out std_logic; + LDR_RX2CORE_1 : out std_logic; + LDR_RX2CORE_2 : out std_logic; + LDR_RX2CORE_3 : out std_logic; + REFCK2CORE : out std_logic; + SCIINT : out std_logic; + SCIRDATA0 : out std_logic; + SCIRDATA1 : out std_logic; + SCIRDATA2 : out std_logic; + SCIRDATA3 : out std_logic; + SCIRDATA4 : out std_logic; + SCIRDATA5 : out std_logic; + SCIRDATA6 : out std_logic; + SCIRDATA7 : out std_logic; + REFCLK_TO_NQ : out std_logic +); +end component; + attribute CONFIG_FILE: string; + attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; + attribute QUAD_MODE: string; + attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; + attribute PLL_SRC: string; + attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute CH0_CDR_SRC: string; + attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; + attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; + attribute black_box_pad_pin: string; + attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; + +signal refclk_from_nq : std_logic := '0'; +signal fpsc_vlo : std_logic := '0'; +signal fpsc_vhi : std_logic := '1'; +signal cin : std_logic_vector (11 downto 0) := "000000000000"; +signal cout : std_logic_vector (19 downto 0); +signal tx_full_clk_ch0_sig : std_logic; + +signal refclk2fpga_sig : std_logic; +signal tx_pll_lol_qd_sig : std_logic; +signal rx_los_low_ch0_sig : std_logic; +signal rx_los_low_ch1_sig : std_logic; +signal rx_los_low_ch2_sig : std_logic; +signal rx_los_low_ch3_sig : std_logic; +signal rx_cdr_lol_ch0_sig : std_logic; +signal rx_cdr_lol_ch1_sig : std_logic; +signal rx_cdr_lol_ch2_sig : std_logic; +signal rx_cdr_lol_ch3_sig : std_logic; + +signal rx_serdes_rst_ch0_c : std_logic; +signal rx_pcs_rst_ch0_c : std_logic; + +-- reset sequence for rx +signal refclkdiv2_rx_ch0 : std_logic; + +signal refclkdiv2_tx_ch : std_logic; +signal tx_pcs_rst_ch_c : std_logic; +signal rst_qd_c : std_logic; + + +begin + +vlo_inst : VLO port map(Z => fpsc_vlo); +vhi_inst : VHI port map(Z => fpsc_vhi); + + rx_los_low_ch0_s <= rx_los_low_ch0_sig; + rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; + tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; + tx_full_clk_ch0 <= tx_full_clk_ch0_sig; + +-- pcs_quad instance +PCSD_INST : PCSD +--synopsys translate_off + generic map (CONFIG_FILE => USER_CONFIG_FILE, + QUAD_MODE => "SINGLE", + CH0_CDR_SRC => "REFCLK_CORE", + PLL_SRC => "REFCLK_CORE" + ) +--synopsys translate_on +port map ( + REFCLKP => fpsc_vlo, + REFCLKN => fpsc_vlo, + +----- CH0 ----- + HDOUTP0 => hdoutp_ch0, + HDOUTN0 => hdoutn_ch0, + HDINP0 => hdinp_ch0, + HDINN0 => hdinn_ch0, + PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, + PCIE_TXCOMPLIANCE_0 => fpsc_vlo, + PCIE_RXPOLARITY_0 => fpsc_vlo, + PCIE_POWERDOWN_0_0 => fpsc_vlo, + PCIE_POWERDOWN_0_1 => fpsc_vlo, + PCIE_RXVALID_0 => open, + PCIE_PHYSTATUS_0 => open, + SCISELCH0 => sci_sel_ch0, + SCIENCH0 => fpsc_vhi, + FF_RXI_CLK_0 => rxiclk_ch0, + FF_TXI_CLK_0 => txiclk_ch0, + FF_EBRD_CLK_0 => fpsc_vlo, + FF_RX_F_CLK_0 => rx_full_clk_ch0, + FF_RX_H_CLK_0 => rx_half_clk_ch0, + FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, + FF_TX_H_CLK_0 => tx_half_clk_ch0, + FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, + FF_TX_D_0_0 => txdata_ch0(0), + FF_TX_D_0_1 => txdata_ch0(1), + FF_TX_D_0_2 => txdata_ch0(2), + FF_TX_D_0_3 => txdata_ch0(3), + FF_TX_D_0_4 => txdata_ch0(4), + FF_TX_D_0_5 => txdata_ch0(5), + FF_TX_D_0_6 => txdata_ch0(6), + FF_TX_D_0_7 => txdata_ch0(7), + FF_TX_D_0_8 => tx_k_ch0(0), + FF_TX_D_0_9 => tx_force_disp_ch0(0), + FF_TX_D_0_10 => tx_disp_sel_ch0(0), + FF_TX_D_0_11 => fpsc_vlo, + FF_TX_D_0_12 => txdata_ch0(8), + FF_TX_D_0_13 => txdata_ch0(9), + FF_TX_D_0_14 => txdata_ch0(10), + FF_TX_D_0_15 => txdata_ch0(11), + FF_TX_D_0_16 => txdata_ch0(12), + FF_TX_D_0_17 => txdata_ch0(13), + FF_TX_D_0_18 => txdata_ch0(14), + FF_TX_D_0_19 => txdata_ch0(15), + FF_TX_D_0_20 => tx_k_ch0(1), + FF_TX_D_0_21 => tx_force_disp_ch0(1), + FF_TX_D_0_22 => tx_disp_sel_ch0(1), + FF_TX_D_0_23 => fpsc_vlo, + FF_RX_D_0_0 => rxdata_ch0(0), + FF_RX_D_0_1 => rxdata_ch0(1), + FF_RX_D_0_2 => rxdata_ch0(2), + FF_RX_D_0_3 => rxdata_ch0(3), + FF_RX_D_0_4 => rxdata_ch0(4), + FF_RX_D_0_5 => rxdata_ch0(5), + FF_RX_D_0_6 => rxdata_ch0(6), + FF_RX_D_0_7 => rxdata_ch0(7), + FF_RX_D_0_8 => rx_k_ch0(0), + FF_RX_D_0_9 => rx_disp_err_ch0(0), + FF_RX_D_0_10 => rx_cv_err_ch0(0), + FF_RX_D_0_11 => open, + FF_RX_D_0_12 => rxdata_ch0(8), + FF_RX_D_0_13 => rxdata_ch0(9), + FF_RX_D_0_14 => rxdata_ch0(10), + FF_RX_D_0_15 => rxdata_ch0(11), + FF_RX_D_0_16 => rxdata_ch0(12), + FF_RX_D_0_17 => rxdata_ch0(13), + FF_RX_D_0_18 => rxdata_ch0(14), + FF_RX_D_0_19 => rxdata_ch0(15), + FF_RX_D_0_20 => rx_k_ch0(1), + FF_RX_D_0_21 => rx_disp_err_ch0(1), + FF_RX_D_0_22 => rx_cv_err_ch0(1), + FF_RX_D_0_23 => open, + + FFC_RRST_0 => rx_serdes_rst_ch0_c, + FFC_SIGNAL_DETECT_0 => fpsc_vlo, + FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, + FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, + FFC_SB_INV_RX_0 => fpsc_vlo, + FFC_PCIE_CT_0 => fpsc_vlo, + FFC_PCI_DET_EN_0 => fpsc_vlo, + FFC_FB_LOOPBACK_0 => fpsc_vlo, + FFC_ENABLE_CGALIGN_0 => fpsc_vlo, + FFC_EI_EN_0 => fpsc_vlo, + FFC_LANE_TX_RST_0 => tx_pcs_rst_ch_c, + FFC_TXPWDNB_0 => tx_pwrup_ch0_c, + FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, + FFC_RXPWDNB_0 => rx_pwrup_ch0_c, + FFS_RLOS_LO_0 => rx_los_low_ch0_sig, + FFS_RLOS_HI_0 => open, + FFS_PCIE_CON_0 => open, + FFS_PCIE_DONE_0 => open, + FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, + FFS_CC_OVERRUN_0 => open, + FFS_CC_UNDERRUN_0 => open, + FFS_SKP_ADDED_0 => open, + FFS_SKP_DELETED_0 => open, + FFS_RLOL_0 => rx_cdr_lol_ch0_sig, + FFS_RXFBFIFO_ERROR_0 => open, + FFS_TXFBFIFO_ERROR_0 => open, + LDR_CORE2TX_0 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, + LDR_RX2CORE_0 => open, + FFS_CDR_TRAIN_DONE_0 => open, + FFC_DIV11_MODE_TX_0 => fpsc_vlo, + FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c, + FFC_DIV11_MODE_RX_0 => fpsc_vlo, + FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c, + +----- CH1 ----- + HDOUTP1 => open, + HDOUTN1 => open, + HDINP1 => fpsc_vlo, + HDINN1 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, + PCIE_TXCOMPLIANCE_1 => fpsc_vlo, + PCIE_RXPOLARITY_1 => fpsc_vlo, + PCIE_POWERDOWN_1_0 => fpsc_vlo, + PCIE_POWERDOWN_1_1 => fpsc_vlo, + PCIE_RXVALID_1 => open, + PCIE_PHYSTATUS_1 => open, + SCISELCH1 => fpsc_vlo, + SCIENCH1 => fpsc_vlo, + FF_RXI_CLK_1 => fpsc_vlo, + FF_TXI_CLK_1 => fpsc_vlo, + FF_EBRD_CLK_1 => fpsc_vlo, + FF_RX_F_CLK_1 => open, + FF_RX_H_CLK_1 => open, + FF_TX_F_CLK_1 => open, + FF_TX_H_CLK_1 => open, + FFC_CK_CORE_RX_1 => fpsc_vlo, + FF_TX_D_1_0 => fpsc_vlo, + FF_TX_D_1_1 => fpsc_vlo, + FF_TX_D_1_2 => fpsc_vlo, + FF_TX_D_1_3 => fpsc_vlo, + FF_TX_D_1_4 => fpsc_vlo, + FF_TX_D_1_5 => fpsc_vlo, + FF_TX_D_1_6 => fpsc_vlo, + FF_TX_D_1_7 => fpsc_vlo, + FF_TX_D_1_8 => fpsc_vlo, + FF_TX_D_1_9 => fpsc_vlo, + FF_TX_D_1_10 => fpsc_vlo, + FF_TX_D_1_11 => fpsc_vlo, + FF_TX_D_1_12 => fpsc_vlo, + FF_TX_D_1_13 => fpsc_vlo, + FF_TX_D_1_14 => fpsc_vlo, + FF_TX_D_1_15 => fpsc_vlo, + FF_TX_D_1_16 => fpsc_vlo, + FF_TX_D_1_17 => fpsc_vlo, + FF_TX_D_1_18 => fpsc_vlo, + FF_TX_D_1_19 => fpsc_vlo, + FF_TX_D_1_20 => fpsc_vlo, + FF_TX_D_1_21 => fpsc_vlo, + FF_TX_D_1_22 => fpsc_vlo, + FF_TX_D_1_23 => fpsc_vlo, + FF_RX_D_1_0 => open, + FF_RX_D_1_1 => open, + FF_RX_D_1_2 => open, + FF_RX_D_1_3 => open, + FF_RX_D_1_4 => open, + FF_RX_D_1_5 => open, + FF_RX_D_1_6 => open, + FF_RX_D_1_7 => open, + FF_RX_D_1_8 => open, + FF_RX_D_1_9 => open, + FF_RX_D_1_10 => open, + FF_RX_D_1_11 => open, + FF_RX_D_1_12 => open, + FF_RX_D_1_13 => open, + FF_RX_D_1_14 => open, + FF_RX_D_1_15 => open, + FF_RX_D_1_16 => open, + FF_RX_D_1_17 => open, + FF_RX_D_1_18 => open, + FF_RX_D_1_19 => open, + FF_RX_D_1_20 => open, + FF_RX_D_1_21 => open, + FF_RX_D_1_22 => open, + FF_RX_D_1_23 => open, + + FFC_RRST_1 => fpsc_vlo, + FFC_SIGNAL_DETECT_1 => fpsc_vlo, + FFC_SB_PFIFO_LP_1 => fpsc_vlo, + FFC_PFIFO_CLR_1 => fpsc_vlo, + FFC_SB_INV_RX_1 => fpsc_vlo, + FFC_PCIE_CT_1 => fpsc_vlo, + FFC_PCI_DET_EN_1 => fpsc_vlo, + FFC_FB_LOOPBACK_1 => fpsc_vlo, + FFC_ENABLE_CGALIGN_1 => fpsc_vlo, + FFC_EI_EN_1 => fpsc_vlo, + FFC_LANE_TX_RST_1 => fpsc_vlo, + FFC_TXPWDNB_1 => fpsc_vlo, + FFC_LANE_RX_RST_1 => fpsc_vlo, + FFC_RXPWDNB_1 => fpsc_vlo, + FFS_RLOS_LO_1 => open, + FFS_RLOS_HI_1 => open, + FFS_PCIE_CON_1 => open, + FFS_PCIE_DONE_1 => open, + FFS_LS_SYNC_STATUS_1 => open, + FFS_CC_OVERRUN_1 => open, + FFS_CC_UNDERRUN_1 => open, + FFS_SKP_ADDED_1 => open, + FFS_SKP_DELETED_1 => open, + FFS_RLOL_1 => open, + FFS_RXFBFIFO_ERROR_1 => open, + FFS_TXFBFIFO_ERROR_1 => open, + LDR_CORE2TX_1 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, + LDR_RX2CORE_1 => open, + FFS_CDR_TRAIN_DONE_1 => open, + FFC_DIV11_MODE_TX_1 => fpsc_vlo, + FFC_RATE_MODE_TX_1 => fpsc_vlo, + FFC_DIV11_MODE_RX_1 => fpsc_vlo, + FFC_RATE_MODE_RX_1 => fpsc_vlo, + +----- CH2 ----- + HDOUTP2 => open, + HDOUTN2 => open, + HDINP2 => fpsc_vlo, + HDINN2 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, + PCIE_TXCOMPLIANCE_2 => fpsc_vlo, + PCIE_RXPOLARITY_2 => fpsc_vlo, + PCIE_POWERDOWN_2_0 => fpsc_vlo, + PCIE_POWERDOWN_2_1 => fpsc_vlo, + PCIE_RXVALID_2 => open, + PCIE_PHYSTATUS_2 => open, + SCISELCH2 => fpsc_vlo, + SCIENCH2 => fpsc_vlo, + FF_RXI_CLK_2 => fpsc_vlo, + FF_TXI_CLK_2 => fpsc_vlo, + FF_EBRD_CLK_2 => fpsc_vlo, + FF_RX_F_CLK_2 => open, + FF_RX_H_CLK_2 => open, + FF_TX_F_CLK_2 => open, + FF_TX_H_CLK_2 => open, + FFC_CK_CORE_RX_2 => fpsc_vlo, + FF_TX_D_2_0 => fpsc_vlo, + FF_TX_D_2_1 => fpsc_vlo, + FF_TX_D_2_2 => fpsc_vlo, + FF_TX_D_2_3 => fpsc_vlo, + FF_TX_D_2_4 => fpsc_vlo, + FF_TX_D_2_5 => fpsc_vlo, + FF_TX_D_2_6 => fpsc_vlo, + FF_TX_D_2_7 => fpsc_vlo, + FF_TX_D_2_8 => fpsc_vlo, + FF_TX_D_2_9 => fpsc_vlo, + FF_TX_D_2_10 => fpsc_vlo, + FF_TX_D_2_11 => fpsc_vlo, + FF_TX_D_2_12 => fpsc_vlo, + FF_TX_D_2_13 => fpsc_vlo, + FF_TX_D_2_14 => fpsc_vlo, + FF_TX_D_2_15 => fpsc_vlo, + FF_TX_D_2_16 => fpsc_vlo, + FF_TX_D_2_17 => fpsc_vlo, + FF_TX_D_2_18 => fpsc_vlo, + FF_TX_D_2_19 => fpsc_vlo, + FF_TX_D_2_20 => fpsc_vlo, + FF_TX_D_2_21 => fpsc_vlo, + FF_TX_D_2_22 => fpsc_vlo, + FF_TX_D_2_23 => fpsc_vlo, + FF_RX_D_2_0 => open, + FF_RX_D_2_1 => open, + FF_RX_D_2_2 => open, + FF_RX_D_2_3 => open, + FF_RX_D_2_4 => open, + FF_RX_D_2_5 => open, + FF_RX_D_2_6 => open, + FF_RX_D_2_7 => open, + FF_RX_D_2_8 => open, + FF_RX_D_2_9 => open, + FF_RX_D_2_10 => open, + FF_RX_D_2_11 => open, + FF_RX_D_2_12 => open, + FF_RX_D_2_13 => open, + FF_RX_D_2_14 => open, + FF_RX_D_2_15 => open, + FF_RX_D_2_16 => open, + FF_RX_D_2_17 => open, + FF_RX_D_2_18 => open, + FF_RX_D_2_19 => open, + FF_RX_D_2_20 => open, + FF_RX_D_2_21 => open, + FF_RX_D_2_22 => open, + FF_RX_D_2_23 => open, + + FFC_RRST_2 => fpsc_vlo, + FFC_SIGNAL_DETECT_2 => fpsc_vlo, + FFC_SB_PFIFO_LP_2 => fpsc_vlo, + FFC_PFIFO_CLR_2 => fpsc_vlo, + FFC_SB_INV_RX_2 => fpsc_vlo, + FFC_PCIE_CT_2 => fpsc_vlo, + FFC_PCI_DET_EN_2 => fpsc_vlo, + FFC_FB_LOOPBACK_2 => fpsc_vlo, + FFC_ENABLE_CGALIGN_2 => fpsc_vlo, + FFC_EI_EN_2 => fpsc_vlo, + FFC_LANE_TX_RST_2 => fpsc_vlo, + FFC_TXPWDNB_2 => fpsc_vlo, + FFC_LANE_RX_RST_2 => fpsc_vlo, + FFC_RXPWDNB_2 => fpsc_vlo, + FFS_RLOS_LO_2 => open, + FFS_RLOS_HI_2 => open, + FFS_PCIE_CON_2 => open, + FFS_PCIE_DONE_2 => open, + FFS_LS_SYNC_STATUS_2 => open, + FFS_CC_OVERRUN_2 => open, + FFS_CC_UNDERRUN_2 => open, + FFS_SKP_ADDED_2 => open, + FFS_SKP_DELETED_2 => open, + FFS_RLOL_2 => open, + FFS_RXFBFIFO_ERROR_2 => open, + FFS_TXFBFIFO_ERROR_2 => open, + LDR_CORE2TX_2 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, + LDR_RX2CORE_2 => open, + FFS_CDR_TRAIN_DONE_2 => open, + FFC_DIV11_MODE_TX_2 => fpsc_vlo, + FFC_RATE_MODE_TX_2 => fpsc_vlo, + FFC_DIV11_MODE_RX_2 => fpsc_vlo, + FFC_RATE_MODE_RX_2 => fpsc_vlo, + +----- CH3 ----- + HDOUTP3 => open, + HDOUTN3 => open, + HDINP3 => fpsc_vlo, + HDINN3 => fpsc_vlo, + PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, + PCIE_TXCOMPLIANCE_3 => fpsc_vlo, + PCIE_RXPOLARITY_3 => fpsc_vlo, + PCIE_POWERDOWN_3_0 => fpsc_vlo, + PCIE_POWERDOWN_3_1 => fpsc_vlo, + PCIE_RXVALID_3 => open, + PCIE_PHYSTATUS_3 => open, + SCISELCH3 => fpsc_vlo, + SCIENCH3 => fpsc_vlo, + FF_RXI_CLK_3 => fpsc_vlo, + FF_TXI_CLK_3 => fpsc_vlo, + FF_EBRD_CLK_3 => fpsc_vlo, + FF_RX_F_CLK_3 => open, + FF_RX_H_CLK_3 => open, + FF_TX_F_CLK_3 => open, + FF_TX_H_CLK_3 => open, + FFC_CK_CORE_RX_3 => fpsc_vlo, + FF_TX_D_3_0 => fpsc_vlo, + FF_TX_D_3_1 => fpsc_vlo, + FF_TX_D_3_2 => fpsc_vlo, + FF_TX_D_3_3 => fpsc_vlo, + FF_TX_D_3_4 => fpsc_vlo, + FF_TX_D_3_5 => fpsc_vlo, + FF_TX_D_3_6 => fpsc_vlo, + FF_TX_D_3_7 => fpsc_vlo, + FF_TX_D_3_8 => fpsc_vlo, + FF_TX_D_3_9 => fpsc_vlo, + FF_TX_D_3_10 => fpsc_vlo, + FF_TX_D_3_11 => fpsc_vlo, + FF_TX_D_3_12 => fpsc_vlo, + FF_TX_D_3_13 => fpsc_vlo, + FF_TX_D_3_14 => fpsc_vlo, + FF_TX_D_3_15 => fpsc_vlo, + FF_TX_D_3_16 => fpsc_vlo, + FF_TX_D_3_17 => fpsc_vlo, + FF_TX_D_3_18 => fpsc_vlo, + FF_TX_D_3_19 => fpsc_vlo, + FF_TX_D_3_20 => fpsc_vlo, + FF_TX_D_3_21 => fpsc_vlo, + FF_TX_D_3_22 => fpsc_vlo, + FF_TX_D_3_23 => fpsc_vlo, + FF_RX_D_3_0 => open, + FF_RX_D_3_1 => open, + FF_RX_D_3_2 => open, + FF_RX_D_3_3 => open, + FF_RX_D_3_4 => open, + FF_RX_D_3_5 => open, + FF_RX_D_3_6 => open, + FF_RX_D_3_7 => open, + FF_RX_D_3_8 => open, + FF_RX_D_3_9 => open, + FF_RX_D_3_10 => open, + FF_RX_D_3_11 => open, + FF_RX_D_3_12 => open, + FF_RX_D_3_13 => open, + FF_RX_D_3_14 => open, + FF_RX_D_3_15 => open, + FF_RX_D_3_16 => open, + FF_RX_D_3_17 => open, + FF_RX_D_3_18 => open, + FF_RX_D_3_19 => open, + FF_RX_D_3_20 => open, + FF_RX_D_3_21 => open, + FF_RX_D_3_22 => open, + FF_RX_D_3_23 => open, + + FFC_RRST_3 => fpsc_vlo, + FFC_SIGNAL_DETECT_3 => fpsc_vlo, + FFC_SB_PFIFO_LP_3 => fpsc_vlo, + FFC_PFIFO_CLR_3 => fpsc_vlo, + FFC_SB_INV_RX_3 => fpsc_vlo, + FFC_PCIE_CT_3 => fpsc_vlo, + FFC_PCI_DET_EN_3 => fpsc_vlo, + FFC_FB_LOOPBACK_3 => fpsc_vlo, + FFC_ENABLE_CGALIGN_3 => fpsc_vlo, + FFC_EI_EN_3 => fpsc_vlo, + FFC_LANE_TX_RST_3 => fpsc_vlo, + FFC_TXPWDNB_3 => fpsc_vlo, + FFC_LANE_RX_RST_3 => fpsc_vlo, + FFC_RXPWDNB_3 => fpsc_vlo, + FFS_RLOS_LO_3 => open, + FFS_RLOS_HI_3 => open, + FFS_PCIE_CON_3 => open, + FFS_PCIE_DONE_3 => open, + FFS_LS_SYNC_STATUS_3 => open, + FFS_CC_OVERRUN_3 => open, + FFS_CC_UNDERRUN_3 => open, + FFS_SKP_ADDED_3 => open, + FFS_SKP_DELETED_3 => open, + FFS_RLOL_3 => open, + FFS_RXFBFIFO_ERROR_3 => open, + FFS_TXFBFIFO_ERROR_3 => open, + LDR_CORE2TX_3 => fpsc_vlo, + FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, + LDR_RX2CORE_3 => open, + FFS_CDR_TRAIN_DONE_3 => open, + FFC_DIV11_MODE_TX_3 => fpsc_vlo, + FFC_RATE_MODE_TX_3 => fpsc_vlo, + FFC_DIV11_MODE_RX_3 => fpsc_vlo, + FFC_RATE_MODE_RX_3 => fpsc_vlo, + +----- Auxilliary ---- + SCIWDATA7 => sci_wrdata(7), + SCIWDATA6 => sci_wrdata(6), + SCIWDATA5 => sci_wrdata(5), + SCIWDATA4 => sci_wrdata(4), + SCIWDATA3 => sci_wrdata(3), + SCIWDATA2 => sci_wrdata(2), + SCIWDATA1 => sci_wrdata(1), + SCIWDATA0 => sci_wrdata(0), + SCIADDR5 => sci_addr(5), + SCIADDR4 => sci_addr(4), + SCIADDR3 => sci_addr(3), + SCIADDR2 => sci_addr(2), + SCIADDR1 => sci_addr(1), + SCIADDR0 => sci_addr(0), + SCIRDATA7 => sci_rddata(7), + SCIRDATA6 => sci_rddata(6), + SCIRDATA5 => sci_rddata(5), + SCIRDATA4 => sci_rddata(4), + SCIRDATA3 => sci_rddata(3), + SCIRDATA2 => sci_rddata(2), + SCIRDATA1 => sci_rddata(1), + SCIRDATA0 => sci_rddata(0), + SCIENAUX => fpsc_vhi, + SCISELAUX => sci_sel_quad, + SCIRD => sci_rd, + SCIWSTN => sci_wrn, + CYAWSTN => fpsc_vlo, + SCIINT => open, + FFC_CK_CORE_TX => fpga_txrefclk, + FFC_MACRO_RST => serdes_rst_qd_c, + FFC_QUAD_RST => rst_qd_c, + FFC_TRST => tx_serdes_rst_c, + FFS_PLOL => tx_pll_lol_qd_sig, + FFC_SYNC_TOGGLE => fpsc_vlo, + REFCK2CORE => refclk2fpga_sig, + CIN0 => fpsc_vlo, + CIN1 => fpsc_vlo, + CIN2 => fpsc_vlo, + CIN3 => fpsc_vlo, + CIN4 => fpsc_vlo, + CIN5 => fpsc_vlo, + CIN6 => fpsc_vlo, + CIN7 => fpsc_vlo, + CIN8 => fpsc_vlo, + CIN9 => fpsc_vlo, + CIN10 => fpsc_vlo, + CIN11 => fpsc_vlo, + COUT0 => open, + COUT1 => open, + COUT2 => open, + COUT3 => open, + COUT4 => open, + COUT5 => open, + COUT6 => open, + COUT7 => open, + COUT8 => open, + COUT9 => open, + COUT10 => open, + COUT11 => open, + COUT12 => open, + COUT13 => open, + COUT14 => open, + COUT15 => open, + COUT16 => open, + COUT17 => open, + COUT18 => open, + COUT19 => open, + REFCLK_FROM_NQ => refclk_from_nq, + REFCLK_TO_NQ => open); + +-- reset sequence for rx + + P1 : PROCESS(fpga_rxrefclk_ch0, rst_n) + BEGIN + IF (rst_n = '0') THEN + refclkdiv2_rx_ch0 <= '0'; + ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN + refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0; + END IF; + END PROCESS; + +rx_reset_sm_ch0 : rx_reset_sm +--synopsys translate_off + generic map (count_index => 4) +--synopsys translate_on +port map ( + refclkdiv2 => refclkdiv2_rx_ch0, + rst_n => rst_n, + rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig, + rx_los_low_ch_s => rx_los_low_ch0_sig, + tx_pll_lol_qd_s => tx_pll_lol_qd_sig, + rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c, + rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c); + + + + + + P5 : PROCESS(fpga_txrefclk, rst_n) + BEGIN + IF (rst_n = '0') THEN + refclkdiv2_tx_ch <= '0'; + ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN + refclkdiv2_tx_ch <= not refclkdiv2_tx_ch; + END IF; + END PROCESS; + +-- reset sequence for tx +tx_reset_sm_ch : tx_reset_sm +--synopsys translate_off + generic map (count_index => 4) +--synopsys translate_on +port map ( + rst_n => rst_n, + refclkdiv2 => refclkdiv2_tx_ch, + tx_pll_lol_qd_s => tx_pll_lol_qd_sig, + rst_qd_c => rst_qd_c, + tx_pcs_rst_ch_c => tx_pcs_rst_ch_c + ); + + +--synopsys translate_off +file_read : PROCESS +VARIABLE open_status : file_open_status; +FILE config : text; +BEGIN + file_open (open_status, config, USER_CONFIG_FILE, read_mode); + IF (open_status = name_error) THEN + report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" + severity ERROR; + END IF; + wait; +END PROCESS; +--synopsys translate_on +end sfp_0_200_int_arch ; diff --git a/media_interfaces/trb_net16_med_ecp3_sfp.vhd b/media_interfaces/trb_net16_med_ecp3_sfp.vhd new file mode 100644 index 0000000..338d36c --- /dev/null +++ b/media_interfaces/trb_net16_med_ecp3_sfp.vhd @@ -0,0 +1,674 @@ +--Media interface for Lattice ECP3 using PCS at 2GHz + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net16_med_ecp3_sfp is + generic( + SERDES_NUM : integer range 0 to 3 := 0; + EXT_CLOCK : integer range 0 to 1 := c_NO; + USE_200_MHZ: integer range 0 to 1 := c_YES + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end entity; + +architecture trb_net16_med_ecp3_sfp_arch of trb_net16_med_ecp3_sfp is + + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_med_ecp3_sfp_arch : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of trb_net16_med_ecp3_sfp_arch : architecture is "off"; + + component sfp_0_200_int + port( + HDINP_CH0 : in std_logic; + HDINN_CH0 : in std_logic; + HDOUTP_CH0 : out std_logic; + HDOUTN_CH0 : out std_logic; + + RXICLK_CH0 : in std_logic; + TXICLK_CH0 : in std_logic; + FPGA_RXREFCLK_CH0 : in std_logic; + FPGA_TXREFCLK : in std_logic; + RX_FULL_CLK_CH0 : out std_logic; + RX_HALF_CLK_CH0 : out std_logic; + TX_FULL_CLK_CH0 : out std_logic; + TX_HALF_CLK_CH0 : out std_logic; + + TXDATA_CH0 : in std_logic_vector(15 downto 0); + TX_K_CH0 : in std_logic_vector(1 downto 0); + TX_FORCE_DISP_CH0 : in std_logic_vector(1 downto 0); + TX_DISP_SEL_CH0 : in std_logic_vector(1 downto 0); + + SB_FELB_CH0_C : in std_logic; + SB_FELB_RST_CH0_C : in std_logic; + + TX_PWRUP_CH0_C : in std_logic; + RX_PWRUP_CH0_C : in std_logic; + TX_DIV2_MODE_CH0_C : in std_logic; + RX_DIV2_MODE_CH0_C : in std_logic; + + SCI_WRDATA : in std_logic_vector(7 downto 0); + SCI_RDDATA : out std_logic_vector(7 downto 0); + SCI_ADDR : in std_logic_vector(5 downto 0); + SCI_SEL_QUAD : in std_logic; + SCI_RD : in std_logic; + SCI_WRN : in std_logic; + SCI_SEL_CH0 : in std_logic; + + TX_SERDES_RST_C : in std_logic; + RST_N : in std_logic; + SERDES_RST_QD_C : in std_logic; + + RXDATA_CH0 : out std_logic_vector(15 downto 0); + RX_K_CH0 : out std_logic_vector(1 downto 0); + RX_DISP_ERR_CH0 : out std_logic_vector(1 downto 0); + RX_CV_ERR_CH0 : out std_logic_vector(1 downto 0); + + RX_LOS_LOW_CH0_S : out std_logic; + LSM_STATUS_CH0_S : out std_logic; + RX_CDR_LOL_CH0_S : out std_logic; + TX_PLL_LOL_QD_S : out std_logic + ); + end component; + + signal refck2core : std_logic; +-- signal clock : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst : std_logic; + signal ffc_lane_rx_rst : std_logic; + --serdes connections + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); -- delayed signals + signal rx_k : std_logic_vector(1 downto 0); -- delayed signals + signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(8 downto 0); + signal ff_txhalfclk : std_logic; + signal ff_rxhalfclk : std_logic; + --rx fifo signals + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; + --tx fifo signals + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; + --rx path + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal buf_med_dataready_out : std_logic; + signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_rx : std_logic_vector(8 downto 0); + signal last_fifo_rx_empty : std_logic; + --tx path + signal last_fifo_tx_empty : std_logic; + --link status + signal rx_k_q : std_logic_vector(1 downto 0); + + signal quad_rst : std_logic; + signal lane_rst : std_logic; + signal tx_allow : std_logic; + signal rx_allow : std_logic; + signal tx_allow_qtx : std_logic; + + signal rx_allow_q : std_logic; -- clock domain changed signal + signal tx_allow_q : std_logic; + signal swap_bytes : std_logic; + signal buf_stat_debug : std_logic_vector(31 downto 0); + + -- status inputs from SFP + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals + + signal buf_STAT_OP : std_logic_vector(15 downto 0); + + signal led_counter : unsigned(16 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; + + + signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion + signal first_idle : std_logic; -- tag the first IDLE2 after data + + signal reset_word_cnt : unsigned(4 downto 0); + signal make_trbnet_reset : std_logic; + signal make_trbnet_reset_q : std_logic; + signal send_reset_words : std_logic; + signal send_reset_words_q : std_logic; + signal send_reset_in : std_logic; + signal send_reset_in_qtx : std_logic; + signal reset_i : std_logic; + signal reset_i_rx : std_logic; + signal pwr_up : std_logic; + signal clear_n : std_logic; + + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + attribute syn_keep of led_counter : signal is true; + attribute syn_keep of send_reset_in : signal is true; + attribute syn_keep of reset_i : signal is true; + attribute syn_preserve of reset_i : signal is true; + +begin + +-------------------------------------------------------------------------- +-- Internal Lane Resets +-------------------------------------------------------------------------- + clear_n <= not clear; + + + PROC_RESET : process(SYSCLK) + begin + if rising_edge(SYSCLK) then + reset_i <= RESET; + send_reset_in <= ctrl_op(15); + pwr_up <= '1'; --not CTRL_OP(i*16+14); + end if; + end process; + +-------------------------------------------------------------------------- +-- Synchronizer stages +-------------------------------------------------------------------------- + +-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP) +THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => sd_prsnt_n_in, + D_IN(1) => sd_los_in, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(0) => sfp_prsnt_n, + D_OUT(1) => sfp_los + ); + + +THE_RX_K_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 4 + ) + port map( + RESET => reset_i, + D_IN(1 downto 0) => comb_rx_k, + D_IN(2) => send_reset_words, + D_IN(3) => make_trbnet_reset, + CLK0 => ff_rxhalfclk, -- CHANGED + CLK1 => sysclk, + D_OUT(1 downto 0) => rx_k_q, + D_OUT(2) => send_reset_words_q, + D_OUT(3) => make_trbnet_reset_q + ); + +THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 16 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_data, + CLK0 => ff_rxhalfclk, + CLK1 => ff_rxhalfclk, + D_OUT => rx_data + ); + +THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_k, + CLK0 => ff_rxhalfclk, + CLK1 => ff_rxhalfclk, + D_OUT => rx_k + ); + +THE_RX_RESET: signal_sync + generic map( + DEPTH => 1, + WIDTH => 1 + ) + port map( + RESET => '0', + D_IN(0) => reset_i, + CLK0 => ff_rxhalfclk, + CLK1 => ff_rxhalfclk, + D_OUT(0) => reset_i_rx + ); + +-- Delay for ALLOW signals +THE_RX_ALLOW_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => reset_i, + D_IN(0) => rx_allow, + D_IN(1) => tx_allow, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(0) => rx_allow_q, + D_OUT(1) => tx_allow_q + ); + +THE_TX_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 2 + ) + port map( + RESET => '0', + D_IN(0) => send_reset_in, + D_IN(1) => tx_allow, + CLK0 => ff_txhalfclk, + CLK1 => ff_txhalfclk, + D_OUT(0) => send_reset_in_qtx, + D_OUT(1) => tx_allow_qtx + ); + + +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- + +THE_SFP_LSM: trb_net16_lsm_sfp + port map( + SYSCLK => sysclk, + RESET => reset_i, + CLEAR => clear, + SFP_MISSING_IN => sfp_prsnt_n, + SFP_LOS_IN => sfp_los, + SD_LINK_OK_IN => link_ok(0), + SD_LOS_IN => link_error(8), + SD_TXCLK_BAD_IN => link_error(5), + SD_RXCLK_BAD_IN => link_error(4), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => rx_k_q, + SD_CV_IN => link_error(7 downto 6), + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + TX_ALLOW_OUT => tx_allow, + RX_ALLOW_OUT => rx_allow, + SWAP_BYTES_OUT => swap_bytes, + STAT_OP => buf_stat_op, + CTRL_OP => ctrl_op, + STAT_DEBUG => buf_stat_debug + ); + +sd_txdis_out <= quad_rst or reset_i; + +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- + +ffc_quad_rst <= quad_rst; +ffc_lane_tx_rst <= lane_rst; +ffc_lane_rx_rst <= lane_rst; + +-- SerDes clock output to FPGA fabric +refclk2core_out <= '0'; + +-- Instantiation of serdes module + + gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate + THE_SERDES: sfp_0_200_int + port map( + HDINP_CH0 => sd_rxd_p_in, + HDINN_CH0 => sd_rxd_n_in, + HDOUTP_CH0 => sd_txd_p_out, + HDOUTN_CH0 => sd_txd_n_out, + + RXICLK_CH0 => ff_rxhalfclk, + TXICLK_CH0 => ff_txhalfclk, + FPGA_RXREFCLK_CH0 => CLK, + FPGA_TXREFCLK => CLK, + RX_FULL_CLK_CH0 => open, + RX_HALF_CLK_CH0 => ff_rxhalfclk, + TX_FULL_CLK_CH0 => open, + TX_HALF_CLK_CH0 => ff_txhalfclk, + + TXDATA_CH0 => tx_data, + TX_K_CH0 => tx_k, + TX_FORCE_DISP_CH0 => tx_correct, + TX_DISP_SEL_CH0 => "00", + + SB_FELB_CH0_C => '0', --loopback enable + SB_FELB_RST_CH0_C => '0', --loopback reset + + TX_PWRUP_CH0_C => '1', --tx power up + RX_PWRUP_CH0_C => '1', --rx power up + TX_DIV2_MODE_CH0_C => '0', --full rate + RX_DIV2_MODE_CH0_C => '0', --full rate + + SCI_WRDATA => (others => '0'), + SCI_RDDATA => open, + SCI_ADDR => (others => '0'), + SCI_SEL_QUAD => '0', + SCI_SEL_CH0 => '0', + SCI_RD => '0', + SCI_WRN => '0', + + TX_SERDES_RST_C => CLEAR, + RST_N => '1', + SERDES_RST_QD_C => ffc_quad_rst, + + RXDATA_CH0 => comb_rx_data, + RX_K_CH0 => comb_rx_k, + RX_DISP_ERR_CH0 => open, + RX_CV_ERR_CH0 => link_error(7 downto 6), + + RX_LOS_LOW_CH0_S => link_error(8), + LSM_STATUS_CH0_S => link_ok(0), + RX_CDR_LOL_CH0_S => link_error(4), + TX_PLL_LOL_QD_S => link_error(5) +-- core_txrefclk => clk, +-- core_rxrefclk => clk, +-- hdinp0 => sd_rxd_p_in, +-- hdinn0 => sd_rxd_n_in, +-- ff_rxiclk_ch0 => sysclk, +-- ff_txiclk_ch0 => sysclk, +-- ff_ebrd_clk_0 => ff_txfullclk, +-- ff_txdata_ch0 => tx_data, +-- ff_tx_k_cntrl_ch0 => tx_k, +-- ff_xmit_ch0 => "00", -- UNKNOWN +-- ff_correct_disp_ch0 => tx_correct, +-- ffc_rrst_ch0 => '0', +-- ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst, +-- ffc_lane_rx_rst_ch0 => ffc_lane_tx_rst, +-- ffc_txpwdnb_ch0 => '1', +-- ffc_rxpwdnb_ch0 => '1', +-- ffc_macro_rst => '0', +-- ffc_quad_rst => ffc_quad_rst, +-- ffc_trst => '0', +-- hdoutp0 => sd_txd_p_out, +-- hdoutn0 => sd_txd_n_out, +-- ff_rxdata_ch0 => comb_rx_data, +-- ff_rx_k_cntrl_ch0 => comb_rx_k, +-- ff_rxfullclk_ch0 => open, +-- ff_rxhalfclk_ch0 => open, +-- ff_disp_err_ch0 => open, +-- ff_cv_ch0 => link_error(7 downto 6), +-- ff_rx_even_ch0 => open, +-- ffs_rlos_lo_ch0 => link_error(8), +-- ffs_ls_sync_status_ch0 => link_ok(0), +-- ffs_cc_underrun_ch0 => link_error(0), +-- ffs_cc_overrun_ch0 => link_error(1), +-- ffs_txfbfifo_error_ch0 => link_error(2), +-- ffs_rxfbfifo_error_ch0 => link_error(3), +-- ffs_rlol_ch0 => link_error(4), +-- oob_out_ch0 => open, +-- ff_txfullclk => ff_txfullclk, +-- ff_txhalfclk => ff_txhalfclk, +-- refck2core => refck2core, +-- ffs_plol => link_error(5) + ); + end generate; + +------------------------------------------------------------------------- +-- RX Fifo & Data output +------------------------------------------------------------------------- +THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => sysclk, + write_clock_in => ff_rxhalfclk, -- CHANGED + read_enable_in => fifo_rx_rd_en, + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty + ); + +fifo_rx_reset <= reset_i or not rx_allow_q; +fifo_rx_rd_en <= not fifo_rx_empty; + +-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path +THE_BYTE_SWAP_PROC: process + begin + wait until rising_edge(ff_rxhalfclk); --CHANGED + last_rx <= rx_k(1) & rx_data(15 downto 8); + if( swap_bytes = '0' ) then + fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); + fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); + else + fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + end if; + end process THE_BYTE_SWAP_PROC; + +buf_med_data_out <= fifo_rx_dout(15 downto 0); +buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q; +buf_med_packet_num_out <= rx_counter; +med_read_out <= tx_allow_q; + + +THE_CNT_RESET_PROC : process + begin + wait until rising_edge(ff_rxhalfclk); --CHANGED + if reset_i_rx = '1' then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if fifo_rx_din = "11" & x"FEFE" then + if reset_word_cnt(4) = '0' then + reset_word_cnt <= reset_word_cnt + to_unsigned(1,1); + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end process; + + +THE_SYNC_PROC: process + begin + wait until rising_edge(sysclk); + med_dataready_out <= buf_med_dataready_out; + med_data_out <= buf_med_data_out; + med_packet_num_out <= buf_med_packet_num_out; + if reset_i = '1' then + med_dataready_out <= '0'; + end if; + end process; + + +--rx packet counter +--------------------- +THE_RX_PACKETS_PROC: process( sysclk ) + begin + if( rising_edge(sysclk) ) then + last_fifo_rx_empty <= fifo_rx_empty; + if reset_i = '1' or rx_allow_q = '0' then + rx_counter <= c_H0; + else + if( buf_med_dataready_out = '1' ) then + if( rx_counter = c_max_word_number ) then + rx_counter <= (others => '0'); + else + rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1)); + end if; + end if; + end if; + end if; + end process; + +--TX Fifo & Data output to Serdes +--------------------- +THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( read_clock_in => ff_txhalfclk, + write_clock_in => sysclk, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty + ); + +fifo_tx_reset <= reset_i or not tx_allow_q; +fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in; +fifo_tx_wr_en <= med_dataready_in and tx_allow_q; +fifo_tx_rd_en <= tx_allow_qtx; + + +THE_SERDES_INPUT_PROC: process( ff_txhalfclk ) + begin + if( rising_edge(ff_txhalfclk) ) then + last_fifo_tx_empty <= fifo_tx_empty; + first_idle <= not last_fifo_tx_empty and fifo_tx_empty; + if send_reset_in = '1' then + tx_data <= x"FEFE"; + tx_k <= "11"; + elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then + tx_data <= x"50bc"; + tx_k <= "01"; + tx_correct <= first_idle & '0'; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + tx_correct <= "00"; + end if; + end if; + end process THE_SERDES_INPUT_PROC; + + +--Generate LED signals +---------------------- +process( sysclk ) + begin + if rising_edge(sysclk) then + led_counter <= led_counter + to_unsigned(1,1); + + if buf_med_dataready_out = '1' then + rx_led <= '1'; + elsif led_counter = 0 then + rx_led <= '0'; + end if; + + if tx_k(0) = '0' then + tx_led <= '1'; + elsif led_counter = 0 then + tx_led <= '0'; + end if; + + end if; + end process; + +stat_op(15) <= send_reset_words_q; +stat_op(14) <= buf_stat_op(14); +stat_op(13) <= make_trbnet_reset_q; +stat_op(12) <= '0'; +stat_op(11) <= tx_led; --tx led +stat_op(10) <= rx_led; --rx led +stat_op(9 downto 0) <= buf_stat_op(9 downto 0); + +-- Debug output +stat_debug(15 downto 0) <= rx_data; +stat_debug(17 downto 16) <= rx_k; +stat_debug(19 downto 18) <= (others => '0'); +stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0); +stat_debug(24) <= fifo_rx_rd_en; +stat_debug(25) <= fifo_rx_wr_en; +stat_debug(26) <= fifo_rx_reset; +stat_debug(27) <= fifo_rx_empty; +stat_debug(28) <= fifo_rx_full; +stat_debug(29) <= last_rx(8); +stat_debug(30) <= rx_allow_q; +stat_debug(41 downto 31) <= (others => '0'); +stat_debug(42) <= sysclk; +stat_debug(43) <= sysclk; +stat_debug(59 downto 44) <= (others => '0'); +stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); + +--stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits +--stat_debug(4) <= buf_stat_debug(4); -- alignme +--stat_debug(5) <= sfp_prsnt_n; +--stat_debug(6) <= tx_k(0); +--stat_debug(7) <= tx_k(1); +--stat_debug(8) <= rx_k_q(0); +--stat_debug(9) <= rx_k_q(1); +--stat_debug(18 downto 10) <= link_error; +--stat_debug(19) <= '0'; +--stat_debug(20) <= link_ok(0); +--stat_debug(38 downto 21) <= fifo_rx_din; +--stat_debug(39) <= swap_bytes; +--stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in +--stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in +--stat_debug(42) <= buf_stat_debug(6); -- resync +--stat_debug(59 downto 43) <= (others => '0'); +--stat_debug(63 downto 60) <= link_error(3 downto 0); + +end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd b/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd new file mode 100644 index 0000000..c0a2d82 --- /dev/null +++ b/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd @@ -0,0 +1,795 @@ +--Media interface for Lattice ECP3 using PCS at 2GHz, RX clock == TX clock + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +entity trb_net16_med_ecp3_sfp_4_onboard is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (64*4-1 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end entity; + +architecture arch_ecp3_sfp_4_onboard of trb_net16_med_ecp3_sfp_4_onboard is + + component serdes_onboard_full + port( + hdinp_ch0 : in std_logic; + hdinn_ch0 : in std_logic; + hdinp_ch1 : in std_logic; + hdinn_ch1 : in std_logic; + hdinp_ch2 : in std_logic; + hdinn_ch2 : in std_logic; + hdinp_ch3 : in std_logic; + hdinn_ch3 : in std_logic; + hdoutp_ch0 : out std_logic; + hdoutn_ch0 : out std_logic; + hdoutp_ch1 : out std_logic; + hdoutn_ch1 : out std_logic; + hdoutp_ch2 : out std_logic; + hdoutn_ch2 : out std_logic; + hdoutp_ch3 : out std_logic; + hdoutn_ch3 : out std_logic; + + rxiclk_ch0 : in std_logic; + txiclk_ch0 : in std_logic; + rxiclk_ch1 : in std_logic; + txiclk_ch1 : in std_logic; + rxiclk_ch2 : in std_logic; + txiclk_ch2 : in std_logic; + rxiclk_ch3 : in std_logic; + txiclk_ch3 : in std_logic; + fpga_rxrefclk_ch0 : in std_logic; + fpga_rxrefclk_ch1 : in std_logic; + fpga_rxrefclk_ch2 : in std_logic; + fpga_rxrefclk_ch3 : in std_logic; + rx_full_clk_ch0 : out std_logic; + rx_half_clk_ch0 : out std_logic; + tx_full_clk_ch0 : out std_logic; + tx_half_clk_ch0 : out std_logic; + rx_full_clk_ch1 : out std_logic; + rx_half_clk_ch1 : out std_logic; + tx_full_clk_ch1 : out std_logic; + tx_half_clk_ch1 : out std_logic; + rx_full_clk_ch2 : out std_logic; + rx_half_clk_ch2 : out std_logic; + tx_full_clk_ch2 : out std_logic; + tx_half_clk_ch2 : out std_logic; + rx_full_clk_ch3 : out std_logic; + rx_half_clk_ch3 : out std_logic; + tx_full_clk_ch3 : out std_logic; + tx_half_clk_ch3 : out std_logic; + + txdata_ch0 : in std_logic_vector(15 downto 0); + txdata_ch1 : in std_logic_vector(15 downto 0); + txdata_ch2 : in std_logic_vector(15 downto 0); + txdata_ch3 : in std_logic_vector(15 downto 0); + tx_k_ch0 : in std_logic_vector(1 downto 0); + tx_k_ch1 : in std_logic_vector(1 downto 0); + tx_k_ch2 : in std_logic_vector(1 downto 0); + tx_k_ch3 : in std_logic_vector(1 downto 0); + tx_force_disp_ch0 : in std_logic_vector(1 downto 0); + tx_force_disp_ch1 : in std_logic_vector(1 downto 0); + tx_force_disp_ch2 : in std_logic_vector(1 downto 0); + tx_force_disp_ch3 : in std_logic_vector(1 downto 0); + tx_disp_sel_ch0 : in std_logic_vector(1 downto 0); + tx_disp_sel_ch1 : in std_logic_vector(1 downto 0); + tx_disp_sel_ch2 : in std_logic_vector(1 downto 0); + tx_disp_sel_ch3 : in std_logic_vector(1 downto 0); + + sb_felb_ch0_c : in std_logic; + sb_felb_ch1_c : in std_logic; + sb_felb_ch2_c : in std_logic; + sb_felb_ch3_c : in std_logic; + sb_felb_rst_ch0_c : in std_logic; + sb_felb_rst_ch1_c : in std_logic; + sb_felb_rst_ch2_c : in std_logic; + sb_felb_rst_ch3_c : in std_logic; + + tx_pwrup_ch0_c : in std_logic; + rx_pwrup_ch0_c : in std_logic; + tx_pwrup_ch1_c : in std_logic; + rx_pwrup_ch1_c : in std_logic; + tx_pwrup_ch2_c : in std_logic; + rx_pwrup_ch2_c : in std_logic; + tx_pwrup_ch3_c : in std_logic; + rx_pwrup_ch3_c : in std_logic; + tx_div2_mode_ch0_c : in std_logic; + rx_div2_mode_ch0_c : in std_logic; + tx_div2_mode_ch1_c : in std_logic; + rx_div2_mode_ch1_c : in std_logic; + tx_div2_mode_ch2_c : in std_logic; + rx_div2_mode_ch2_c : in std_logic; + tx_div2_mode_ch3_c : in std_logic; + rx_div2_mode_ch3_c : in std_logic; + + rxdata_ch0 : out std_logic_vector(15 downto 0); + rxdata_ch1 : out std_logic_vector(15 downto 0); + rxdata_ch2 : out std_logic_vector(15 downto 0); + rxdata_ch3 : out std_logic_vector(15 downto 0); + rx_k_ch0 : out std_logic_vector(1 downto 0); + rx_k_ch1 : out std_logic_vector(1 downto 0); + rx_k_ch2 : out std_logic_vector(1 downto 0); + rx_k_ch3 : out std_logic_vector(1 downto 0); + rx_disp_err_ch0 : out std_logic_vector(1 downto 0); + rx_disp_err_ch1 : out std_logic_vector(1 downto 0); + rx_disp_err_ch2 : out std_logic_vector(1 downto 0); + rx_disp_err_ch3 : out std_logic_vector(1 downto 0); + rx_cv_err_ch0 : out std_logic_vector(1 downto 0); + rx_cv_err_ch1 : out std_logic_vector(1 downto 0); + rx_cv_err_ch2 : out std_logic_vector(1 downto 0); + rx_cv_err_ch3 : out std_logic_vector(1 downto 0); + + rx_los_low_ch0_s : out std_logic; + rx_los_low_ch1_s : out std_logic; + rx_los_low_ch2_s : out std_logic; + rx_los_low_ch3_s : out std_logic; + lsm_status_ch0_s : out std_logic; + lsm_status_ch1_s : out std_logic; + lsm_status_ch2_s : out std_logic; + lsm_status_ch3_s : out std_logic; + rx_cdr_lol_ch0_s : out std_logic; + rx_cdr_lol_ch1_s : out std_logic; + rx_cdr_lol_ch2_s : out std_logic; + rx_cdr_lol_ch3_s : out std_logic; + + fpga_txrefclk : in std_logic; + tx_serdes_rst_c : in std_logic; + tx_sync_qd_c : in std_logic; + tx_pll_lol_qd_s : out std_logic; + rst_n : in std_logic; + serdes_rst_qd_c : in std_logic; + refclk2fpga : out std_logic; + + sci_sel_ch0 : in std_logic; + sci_sel_ch1 : in std_logic; + sci_sel_ch2 : in std_logic; + sci_sel_ch3 : in std_logic; + sci_wrdata : in std_logic_vector(7 downto 0); + sci_addr : in std_logic_vector(5 downto 0); + sci_sel_quad : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + sci_rddata : out std_logic_vector(7 downto 0) + + ); + end component; + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of arch_ecp3_sfp_4_onboard : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of arch_ecp3_sfp_4_onboard : architecture is "off"; + + + signal refck2core : std_logic; + --reset signals + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst : std_logic_vector(3 downto 0); + signal ffc_lane_rx_rst : std_logic_vector(3 downto 0); + --serdes connections + signal tx_data : std_logic_vector(4*16-1 downto 0); + signal tx_k : std_logic_vector(4*2-1 downto 0); + signal rx_data : std_logic_vector(4*16-1 downto 0); -- delayed signals + signal rx_k : std_logic_vector(4*2-1 downto 0); -- delayed signals + signal comb_rx_data : std_logic_vector(4*16-1 downto 0); -- original signals from SFP + signal comb_rx_k : std_logic_vector(4*2-1 downto 0); -- original signals from SFP + signal link_ok : std_logic_vector(4*1-1 downto 0); + signal link_error : std_logic_vector(4*9-1 downto 0); + signal ff_txhalfclk : std_logic_vector(4*1-1 downto 0); + signal ff_rxhalfclk : std_logic_vector(4*1-1 downto 0); + --rx fifo signals + signal fifo_rx_rd_en : std_logic_vector(4*1-1 downto 0); + signal fifo_rx_wr_en : std_logic_vector(4*1-1 downto 0); + signal fifo_rx_reset : std_logic_vector(4*1-1 downto 0); + signal fifo_rx_din : std_logic_vector(4*18-1 downto 0); + signal fifo_rx_dout : std_logic_vector(4*18-1 downto 0); + signal fifo_rx_full : std_logic_vector(4*1-1 downto 0); + signal fifo_rx_empty : std_logic_vector(4*1-1 downto 0); + --tx fifo signals + signal fifo_tx_rd_en : std_logic_vector(4*1-1 downto 0); + signal fifo_tx_wr_en : std_logic_vector(4*1-1 downto 0); + signal fifo_tx_reset : std_logic_vector(4*1-1 downto 0); + signal fifo_tx_din : std_logic_vector(4*18-1 downto 0); + signal fifo_tx_dout : std_logic_vector(4*18-1 downto 0); + signal fifo_tx_full : std_logic_vector(4*1-1 downto 0); + signal fifo_tx_empty : std_logic_vector(4*1-1 downto 0); + --rx path + signal rx_counter : std_logic_vector(4*3-1 downto 0); + signal buf_med_dataready_out : std_logic_vector(4*1-1 downto 0); + signal buf_med_data_out : std_logic_vector(4*16-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(4*3-1 downto 0); + signal last_rx : std_logic_vector(4*9-1 downto 0); + signal last_fifo_rx_empty : std_logic_vector(4*1-1 downto 0); + --tx path + signal last_fifo_tx_empty : std_logic_vector(4*1-1 downto 0); + --link status + signal rx_k_q : std_logic_vector(4*2-1 downto 0); + + signal quad_rst : std_logic_vector(4*1-1 downto 0); + signal lane_rst : std_logic_vector(4*1-1 downto 0); + signal tx_allow : std_logic_vector(4*1-1 downto 0); + signal rx_allow : std_logic_vector(4*1-1 downto 0); + signal tx_allow_qtx : std_logic_vector(4*1-1 downto 0); + + signal rx_allow_q : std_logic_vector(4*1-1 downto 0); -- clock domain changed signal + signal tx_allow_q : std_logic_vector(4*1-1 downto 0); + signal swap_bytes : std_logic_vector(4*1-1 downto 0); + signal buf_stat_debug : std_logic_vector(4*32-1 downto 0); + + -- status inputs from SFP + signal sfp_prsnt_n : std_logic_vector(4*1-1 downto 0); + signal sfp_los : std_logic_vector(4*1-1 downto 0); + + signal buf_STAT_OP : std_logic_vector(4*16-1 downto 0); + + signal led_counter : unsigned(16 downto 0); + signal rx_led : std_logic_vector(4*1-1 downto 0); + signal tx_led : std_logic_vector(4*1-1 downto 0); + + + signal tx_correct : std_logic_vector(4*2-1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion + signal first_idle : std_logic_vector(4*1-1 downto 0); -- tag the first IDLE2 after data + + type arr5_t is array (0 to 3) of unsigned(4 downto 0); + signal reset_word_cnt : arr5_t; + signal make_trbnet_reset : std_logic_vector(4*1-1 downto 0); + signal make_trbnet_reset_q : std_logic_vector(4*1-1 downto 0); + signal send_reset_words : std_logic_vector(4*1-1 downto 0); + signal send_reset_words_q : std_logic_vector(4*1-1 downto 0); + signal send_reset_in : std_logic_vector(4*1-1 downto 0); + signal send_reset_in_qtx : std_logic_vector(4*1-1 downto 0); + signal reset_i : std_logic; + signal reset_i_rx : std_logic; + signal pwr_up : std_logic_vector(4*1-1 downto 0); + signal clear_n : std_logic; + + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + attribute syn_keep of led_counter : signal is true; + attribute syn_keep of send_reset_in : signal is true; + attribute syn_keep of reset_i : signal is true; + attribute syn_preserve of reset_i : signal is true; + +begin + +-------------------------------------------------------------------------- +-- Internal Lane Resets +-------------------------------------------------------------------------- + clear_n <= not clear; + + + PROC_RESET : process(SYSCLK) + begin + if rising_edge(SYSCLK) then + reset_i <= RESET; + send_reset_in(0) <= ctrl_op(15); + send_reset_in(1) <= ctrl_op(15+16); + send_reset_in(2) <= ctrl_op(15+32); + send_reset_in(3) <= ctrl_op(15+48); + pwr_up <= x"F"; --not CTRL_OP(i*16+14); + end if; + end process; + +-------------------------------------------------------------------------- +-- Synchronizer stages +-------------------------------------------------------------------------- + +-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP) +THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 8 + ) + port map( + RESET => '0', + D_IN(3 downto 0) => SD_PRSNT_N_IN, + D_IN(7 downto 4) => SD_LOS_IN, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(3 downto 0) => sfp_prsnt_n, + D_OUT(7 downto 4) => sfp_los + ); + + +rx_k_q <= rx_k; +send_reset_words_q <= send_reset_words; +make_trbnet_reset_q <= make_trbnet_reset; +reset_i_rx <= reset_i; + +THE_RX_DATA_DELAY: signal_sync + generic map( + DEPTH => 1, + WIDTH => 64 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_data, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT => rx_data + ); + +THE_RX_K_DELAY: signal_sync + generic map( + DEPTH => 2, + WIDTH => 8 + ) + port map( + RESET => reset_i, + D_IN => comb_rx_k, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT => rx_k + ); + +-- Delay for ALLOW signals +THE_RX_ALLOW_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 8 + ) + port map( + RESET => reset_i, + D_IN(3 downto 0) => rx_allow, + D_IN(7 downto 4) => tx_allow, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(3 downto 0) => rx_allow_q, + D_OUT(7 downto 4) => tx_allow_q + ); + +THE_TX_SYNC: signal_sync + generic map( + DEPTH => 1, + WIDTH => 8 + ) + port map( + RESET => '0', + D_IN(3 downto 0) => send_reset_in, + D_IN(7 downto 4) => tx_allow, + CLK0 => sysclk, + CLK1 => sysclk, + D_OUT(3 downto 0) => send_reset_in_qtx, + D_OUT(7 downto 4) => tx_allow_qtx + ); + + +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- +gen_LSM : for i in 0 to 3 generate + THE_SFP_LSM: trb_net16_lsm_sfp + port map( + SYSCLK => sysclk, + RESET => reset_i, + CLEAR => clear, + SFP_MISSING_IN => sfp_prsnt_n(i), + SFP_LOS_IN => sfp_los(i), + SD_LINK_OK_IN => link_ok(i), + SD_LOS_IN => link_error(i*9+8), + SD_TXCLK_BAD_IN => link_error(5), + SD_RXCLK_BAD_IN => link_error(i*9+4), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => rx_k_q(i*2+1 downto i*2), + SD_CV_IN => link_error(i*8+7 downto i*8+6), + FULL_RESET_OUT => quad_rst(i), + LANE_RESET_OUT => lane_rst(i), + TX_ALLOW_OUT => tx_allow(i), + RX_ALLOW_OUT => rx_allow(i), + SWAP_BYTES_OUT => swap_bytes(i), + STAT_OP => buf_stat_op(i*16+15 downto i*16), + CTRL_OP => ctrl_op(i*16+15 downto i*16), + STAT_DEBUG => buf_stat_debug(i*32+31 downto i*32) + ); + + sd_txdis_out(i) <= quad_rst(i) or reset_i; + + ffc_quad_rst <= quad_rst(0); + ffc_lane_tx_rst(i) <= lane_rst(i); + ffc_lane_rx_rst(i) <= lane_rst(i); + +end generate; + +-- Instantiation of serdes module +THE_SERDES: serdes_onboard_full + port map( + HDINP_CH0 => sd_rxd_p_in(0), + HDINN_CH0 => sd_rxd_n_in(0), + HDINP_CH1 => sd_rxd_p_in(1), + HDINN_CH1 => sd_rxd_n_in(1), + HDINP_CH2 => sd_rxd_p_in(2), + HDINN_CH2 => sd_rxd_n_in(2), + HDINP_CH3 => sd_rxd_p_in(3), + HDINN_CH3 => sd_rxd_n_in(3), + HDOUTP_CH0 => sd_txd_p_out(0), + HDOUTN_CH0 => sd_txd_n_out(0), + HDOUTP_CH1 => sd_txd_p_out(1), + HDOUTN_CH1 => sd_txd_n_out(1), + HDOUTP_CH2 => sd_txd_p_out(2), + HDOUTN_CH2 => sd_txd_n_out(2), + HDOUTP_CH3 => sd_txd_p_out(3), + HDOUTN_CH3 => sd_txd_n_out(3), + + RXICLK_CH0 => sysclk, + TXICLK_CH0 => sysclk, + RXICLK_CH1 => sysclk, + TXICLK_CH1 => sysclk, + RXICLK_CH2 => sysclk, + TXICLK_CH2 => sysclk, + RXICLK_CH3 => sysclk, + TXICLK_CH3 => sysclk, + FPGA_RXREFCLK_CH0 => CLK, + FPGA_RXREFCLK_CH1 => CLK, + FPGA_RXREFCLK_CH2 => CLK, + FPGA_RXREFCLK_CH3 => CLK, + FPGA_TXREFCLK => CLK, + RX_FULL_CLK_CH0 => open, + RX_HALF_CLK_CH0 => open, + TX_FULL_CLK_CH0 => open, + TX_HALF_CLK_CH0 => open, + RX_FULL_CLK_CH1 => open, + RX_HALF_CLK_CH1 => open, + TX_FULL_CLK_CH1 => open, + TX_HALF_CLK_CH1 => open, + RX_FULL_CLK_CH2 => open, + RX_HALF_CLK_CH2 => open, + TX_FULL_CLK_CH2 => open, + TX_HALF_CLK_CH2 => open, + RX_FULL_CLK_CH3 => open, + RX_HALF_CLK_CH3 => open, + TX_FULL_CLK_CH3 => open, + TX_HALF_CLK_CH3 => open, + + TXDATA_CH0 => tx_data(15 downto 0), + TXDATA_CH1 => tx_data(31 downto 16), + TXDATA_CH2 => tx_data(47 downto 32), + TXDATA_CH3 => tx_data(63 downto 48), + TX_K_CH0 => tx_k(1 downto 0), + TX_K_CH1 => tx_k(3 downto 2), + TX_K_CH2 => tx_k(5 downto 4), + TX_K_CH3 => tx_k(7 downto 6), + TX_FORCE_DISP_CH0 => tx_correct(1 downto 0), + TX_FORCE_DISP_CH1 => tx_correct(3 downto 2), + TX_FORCE_DISP_CH2 => tx_correct(5 downto 4), + TX_FORCE_DISP_CH3 => tx_correct(7 downto 6), + TX_DISP_SEL_CH0 => "00", + TX_DISP_SEL_CH1 => "00", + TX_DISP_SEL_CH2 => "00", + TX_DISP_SEL_CH3 => "00", + + SB_FELB_CH0_C => '0', --loopback enable + SB_FELB_CH1_C => '0', --loopback enable + SB_FELB_CH2_C => '0', --loopback enable + SB_FELB_CH3_C => '0', --loopback enable + SB_FELB_RST_CH0_C => '0', --loopback reset + SB_FELB_RST_CH1_C => '0', --loopback reset + SB_FELB_RST_CH2_C => '0', --loopback reset + SB_FELB_RST_CH3_C => '0', --loopback reset + + TX_PWRUP_CH0_C => '1', --tx power up + RX_PWRUP_CH0_C => '1', --rx power up + TX_PWRUP_CH1_C => '1', --tx power up + RX_PWRUP_CH1_C => '1', --rx power up + TX_PWRUP_CH2_C => '1', --tx power up + RX_PWRUP_CH2_C => '1', --rx power up + TX_PWRUP_CH3_C => '1', --tx power up + RX_PWRUP_CH3_C => '1', --rx power up + TX_DIV2_MODE_CH0_C => '0', --full rate + RX_DIV2_MODE_CH0_C => '0', --full rate + TX_DIV2_MODE_CH1_C => '0', --full rate + RX_DIV2_MODE_CH1_C => '0', --full rate + TX_DIV2_MODE_CH2_C => '0', --full rate + RX_DIV2_MODE_CH2_C => '0', --full rate + TX_DIV2_MODE_CH3_C => '0', --full rate + RX_DIV2_MODE_CH3_C => '0', --full rate + + SCI_WRDATA => (others => '0'), + SCI_RDDATA => open, + SCI_ADDR => (others => '0'), + SCI_SEL_QUAD => '0', + SCI_SEL_CH0 => '0', + SCI_SEL_CH1 => '0', + SCI_SEL_CH2 => '0', + SCI_SEL_CH3 => '0', + SCI_RD => '0', + SCI_WRN => '0', + + TX_SERDES_RST_C => CLEAR, + TX_SYNC_QD_C => '0', + RST_N => '1', + SERDES_RST_QD_C => ffc_quad_rst, + + RXDATA_CH0 => comb_rx_data(15 downto 0), + RXDATA_CH1 => comb_rx_data(31 downto 16), + RXDATA_CH2 => comb_rx_data(47 downto 32), + RXDATA_CH3 => comb_rx_data(63 downto 48), + RX_K_CH0 => comb_rx_k(1 downto 0), + RX_K_CH1 => comb_rx_k(3 downto 2), + RX_K_CH2 => comb_rx_k(5 downto 4), + RX_K_CH3 => comb_rx_k(7 downto 6), + + RX_DISP_ERR_CH0 => open, + RX_DISP_ERR_CH1 => open, + RX_DISP_ERR_CH2 => open, + RX_DISP_ERR_CH3 => open, + RX_CV_ERR_CH0 => link_error(0*9+7 downto 0*9+6), + RX_CV_ERR_CH1 => link_error(1*9+7 downto 1*9+6), + RX_CV_ERR_CH2 => link_error(2*9+7 downto 2*9+6), + RX_CV_ERR_CH3 => link_error(3*9+7 downto 3*9+6), + + RX_LOS_LOW_CH0_S => link_error(0*9+8), + RX_LOS_LOW_CH1_S => link_error(1*9+8), + RX_LOS_LOW_CH2_S => link_error(2*9+8), + RX_LOS_LOW_CH3_S => link_error(3*9+8), + LSM_STATUS_CH0_S => link_ok(0), + LSM_STATUS_CH1_S => link_ok(1), + LSM_STATUS_CH2_S => link_ok(2), + LSM_STATUS_CH3_S => link_ok(3), + RX_CDR_LOL_CH0_S => link_error(0*9+4), + RX_CDR_LOL_CH1_S => link_error(1*9+4), + RX_CDR_LOL_CH2_S => link_error(2*9+4), + RX_CDR_LOL_CH3_S => link_error(3*9+4), + TX_PLL_LOL_QD_S => link_error(5) + + ); + +------------------------------------------------------------------------- +-- RX Fifo & Data output +------------------------------------------------------------------------- +gen_logic : for i in 0 to 3 generate + + THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( read_clock_in => sysclk, + write_clock_in => sysclk, -- CHANGED + read_enable_in => fifo_rx_rd_en(i), + write_enable_in => fifo_rx_wr_en(i), + fifo_gsr_in => fifo_rx_reset(i), + write_data_in => fifo_rx_din(i*18+17 downto i*18), + read_data_out => fifo_rx_dout(i*18+17 downto i*18), + full_out => fifo_rx_full(i), + empty_out => fifo_rx_empty(i) + ); + + fifo_rx_reset(i) <= reset_i or not rx_allow_q(i); + fifo_rx_rd_en(i) <= not fifo_rx_empty(i); + + -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path + THE_BYTE_SWAP_PROC: process + begin + wait until rising_edge(sysclk); --CHANGED + last_rx(i*9+8 downto i*9) <= rx_k(i*2+1) & rx_data(i*16+15 downto i*16+8); + if( swap_bytes(i) = '0' ) then + fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+1) & rx_k(i*2+0) + & rx_data(i*16+15 downto i*16+8) & rx_data(i*16+7 downto i*16+0); + fifo_rx_wr_en(i) <= not rx_k(i*2+0) and rx_allow(i) and link_ok(i); + else + fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+0) & last_rx(i*9+8) + & rx_data(i*16+7 downto i*16+0) & last_rx(i*9+7 downto i*9+0); + fifo_rx_wr_en(i) <= not last_rx(i*9+8) and rx_allow(i) and link_ok(i); + end if; + end process THE_BYTE_SWAP_PROC; + + buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18); + buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16) + and not last_fifo_rx_empty(i) and rx_allow_q(i); + buf_med_packet_num_out(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3); + med_read_out(i) <= tx_allow_q(i); + + + THE_CNT_RESET_PROC : process + begin + wait until rising_edge(sysclk); --CHANGED + if reset_i_rx = '1' then + send_reset_words(i) <= '0'; + make_trbnet_reset(i) <= '0'; + reset_word_cnt(i) <= (others => '0'); + else + send_reset_words(i) <= '0'; + make_trbnet_reset(i) <= '0'; + if fifo_rx_din(i*18+17 downto i*18) = "11" & x"FEFE" then + if reset_word_cnt(i)(4) = '0' then + reset_word_cnt(i) <= reset_word_cnt(i) + to_unsigned(1,1); + else + send_reset_words(i) <= '1'; + end if; + else + reset_word_cnt(i) <= (others => '0'); + make_trbnet_reset(i) <= reset_word_cnt(i)(4); + end if; + end if; + end process; + + + THE_SYNC_PROC: process + begin + wait until rising_edge(sysclk); + med_dataready_out(i) <= buf_med_dataready_out(i); + med_data_out(i*16+15 downto i*16) <= buf_med_data_out(i*16+15 downto i*16); + med_packet_num_out(i*3+2 downto i*3) <= buf_med_packet_num_out(i*3+2 downto i*3); + if reset_i = '1' then + med_dataready_out(i) <= '0'; + end if; + end process; + + + --rx packet counter + --------------------- + THE_RX_PACKETS_PROC: process( sysclk ) + begin + if( rising_edge(sysclk) ) then + last_fifo_rx_empty(i) <= fifo_rx_empty(i); + if reset_i = '1' or rx_allow_q(i) = '0' then + rx_counter(i*3+2 downto i*3) <= c_H0; + else + if( buf_med_dataready_out(i) = '1' ) then + if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then + rx_counter(i*3+2 downto i*3) <= (others => '0'); + else + rx_counter(i*3+2 downto i*3) <= std_logic_vector(unsigned(rx_counter(i*3+2 downto i*3)) + to_unsigned(1,1)); + end if; + end if; + end if; + end if; + end process; + + --TX Fifo & Data output to Serdes + --------------------- + THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( read_clock_in => sysclk, + write_clock_in => sysclk, + read_enable_in => fifo_tx_rd_en(i), + write_enable_in => fifo_tx_wr_en(i), + fifo_gsr_in => fifo_tx_reset(i), + write_data_in => fifo_tx_din(i*18+17 downto i*18), + read_data_out => fifo_tx_dout(i*18+17 downto i*18), + full_out => fifo_tx_full(i), + empty_out => fifo_tx_empty(i) + ); + + fifo_tx_reset(i) <= reset_i or not tx_allow_q(i); + fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0) & med_data_in(i*16+15 downto i*16); + fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow_q(i); + fifo_tx_rd_en(i) <= tx_allow_qtx(i); + + + THE_SERDES_INPUT_PROC: process( sysclk ) + begin + if( rising_edge(sysclk) ) then + last_fifo_tx_empty(i) <= fifo_tx_empty(i); + first_idle(i) <= not last_fifo_tx_empty(i) and fifo_tx_empty(i); + if send_reset_in(i) = '1' then + tx_data(i*16+15 downto i*16) <= x"FEFE"; + tx_k(i*2+1 downto i*2) <= "11"; + elsif( (last_fifo_tx_empty(i) = '1') or (tx_allow_qtx(i) = '0') ) then + tx_data(i*16+15 downto i*16) <= x"50bc"; + tx_k(i*2+1 downto i*2) <= "01"; + tx_correct(i*2+1 downto i*2) <= first_idle(i) & '0'; + else + tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18); + tx_k(i*2+1 downto i*2) <= "00"; + tx_correct(i*2+1 downto i*2) <= "00"; + end if; + end if; + end process THE_SERDES_INPUT_PROC; + +end generate; +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- + +-- SerDes clock output to FPGA fabric +refclk2core_out <= '0'; +--Generate LED signals +---------------------- +process( sysclk ) + begin + if rising_edge(sysclk) then + led_counter <= led_counter + to_unsigned(1,1); + + if led_counter = 0 then + rx_led <= x"0"; + else + rx_led <= rx_led or buf_med_dataready_out; + end if; + + if led_counter = 0 then + tx_led <= x"0"; + else + tx_led <= tx_led or (tx_k(6) & tx_k(4) & tx_k(2) & tx_k(0)); + end if; + + end if; + end process; + +gen_outputs : for i in 0 to 3 generate + stat_op(i*16+15) <= send_reset_words_q(i); + stat_op(i*16+14) <= buf_stat_op(i*16+14); + stat_op(i*16+13) <= make_trbnet_reset_q(i); + stat_op(i*16+12) <= '0'; + stat_op(i*16+11) <= tx_led(i); --tx led + stat_op(i*16+10) <= rx_led(I); --rx led + stat_op(i*16+9 downto i*16+0) <= buf_stat_op(i*16+9 downto i*16+0); + + -- Debug output + stat_debug(i*64+15 downto i*64+0) <= rx_data(i*16+15 downto i*16); + stat_debug(i*64+17 downto i*64+16) <= rx_k(i*2+1 downto i*2); + stat_debug(i*64+19 downto i*64+18) <= (others => '0'); + stat_debug(i*64+23 downto i*64+20) <= buf_stat_debug(i*16+3 downto i*16+0); + stat_debug(i*64+24) <= fifo_rx_rd_en(i); + stat_debug(i*64+25) <= fifo_rx_wr_en(i); + stat_debug(i*64+26) <= fifo_rx_reset(i); + stat_debug(i*64+27) <= fifo_rx_empty(i); + stat_debug(i*64+28) <= fifo_rx_full(i); + stat_debug(i*64+29) <= last_rx(i*9+8); + stat_debug(i*64+30) <= rx_allow_q(i); + stat_debug(i*64+41 downto i*64+31) <= (others => '0'); + stat_debug(i*64+42) <= sysclk; + stat_debug(i*64+43) <= sysclk; + stat_debug(i*64+59 downto i*64+44) <= (others => '0'); + stat_debug(i*64+63 downto i*64+60) <= buf_stat_debug(i*16+3 downto i*16+0); +end generate; + +--stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits +--stat_debug(4) <= buf_stat_debug(4); -- alignme +--stat_debug(5) <= sfp_prsnt_n; +--stat_debug(6) <= tx_k(0); +--stat_debug(7) <= tx_k(1); +--stat_debug(8) <= rx_k_q(0); +--stat_debug(9) <= rx_k_q(1); +--stat_debug(18 downto 10) <= link_error; +--stat_debug(19) <= '0'; +--stat_debug(20) <= link_ok(0); +--stat_debug(38 downto 21) <= fifo_rx_din; +--stat_debug(39) <= swap_bytes; +--stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in +--stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in +--stat_debug(42) <= buf_stat_debug(6); -- resync +--stat_debug(59 downto 43) <= (others => '0'); +--stat_debug(63 downto 60) <= link_error(3 downto 0); + +end architecture; \ No newline at end of file diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index c2231e2..31b621f 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -161,15 +161,12 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is begin ---------------------------------- ---Reset Signals +--Sync input Signals ---------------------------------- - SYNC_RESET : process(CLK) - begin - if rising_edge(CLK) then - reset_i <= RESET; - end if; - end process; + reset_i <= RESET when rising_edge(CLK); + timer_us_tick <= CTRL_TIMER_TICK(0) when rising_edge(CLK); + timer_ms_tick <= CTRL_TIMER_TICK(1) when rising_edge(CLK); ---------------------------------- @@ -216,16 +213,16 @@ begin SYN_READ_IN => INIT_POOL_READ ); - process(CLK) - begin - if rising_edge(CLK) then - if reset_i = '1' then - INIT_muxed_READ <= '0'; - else - INIT_muxed_READ <= comb_INIT_next_read; - end if; - end if; - end process; +-- process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if reset_i = '1' then +-- INIT_muxed_READ <= '0'; +-- else + INIT_muxed_READ <= comb_INIT_next_read and not reset_i when rising_edge(CLK); +-- end if; +-- end if; +-- end process; ---------------------------------- --choosing init point @@ -370,32 +367,32 @@ INIT_DATAREADY_OUT <= buf_INIT_DATAREADY_OUT; end if; end if; end process; - current_INIT_TYPE <= INIT_muxed_DATA(2 downto 0) when INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_H0 - else saved_INIT_TYPE; - - save_REPLY_TYPE : process(CLK) - begin - if rising_edge(CLK) then - if reset_i = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_F3) then - saved_REPLY_TYPE <= TYPE_ILLEGAL; - elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 then - saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0); - end if; - end if; - end process; - current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 - else saved_REPLY_TYPE; - - save_SEQ_NR : process(CLK) - begin - if rising_edge(CLK) then - if reset_i = '1' then - SEQ_NR <= (others => '0'); - elsif INIT_POOL_PACKET_NUM = c_F3 and current_INIT_TYPE = TYPE_HDR then - SEQ_NR <= INIT_POOL_DATA(11 downto 4); - end if; - end if; - end process; +-- current_INIT_TYPE <= INIT_muxed_DATA(2 downto 0) when INIT_muxed_DATAREADY = '1' and INIT_muxed_PACKET_NUM = c_H0 +-- else saved_INIT_TYPE; + +-- save_REPLY_TYPE : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if reset_i = '1' or (REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_F3) then +-- saved_REPLY_TYPE <= TYPE_ILLEGAL; +-- elsif REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 then +-- saved_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0); +-- end if; +-- end if; +-- end process; +-- current_REPLY_TYPE <= REPLY_POOL_DATA(2 downto 0) when REPLY_POOL_DATAREADY = '1' and REPLY_POOL_PACKET_NUM = c_H0 +-- else saved_REPLY_TYPE; + +-- save_SEQ_NR : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if reset_i = '1' then +-- SEQ_NR <= (others => '0'); +-- elsif INIT_POOL_PACKET_NUM = c_F3 and current_INIT_TYPE = TYPE_HDR then +-- SEQ_NR <= INIT_POOL_DATA(11 downto 4); +-- end if; +-- end if; +-- end process; ---------------------------------- --REPLY reading and merging TRM @@ -435,15 +432,6 @@ INIT_DATAREADY_OUT <= buf_INIT_DATAREADY_OUT; and REPLY_reading_trm(i) = '1' and reply_dataready_in_i(i) = '1' else '0'; reading_trmF3(i) <= '1' when reply_packet_num_in_i(i*c_NUM_WIDTH+2 downto i*c_NUM_WIDTH) = c_F3 and REPLY_reading_trm(i) = '1' and reply_dataready_in_i(i) = '1' else '0'; - --- not reply_packet_num_in_i(i*c_NUM_WIDTH+1) and not reply_packet_num_in_i(i*c_NUM_WIDTH) --- and not reply_packet_num_in_i(i*c_NUM_WIDTH+2) and REPLY_reading_trm(i) and reply_dataready_in_i(i); --- reading_trmF1(i) <= not reply_packet_num_in_i(i*c_NUM_WIDTH+1) and reply_packet_num_in_i(i*c_NUM_WIDTH) --- and REPLY_reading_trm(i) and reply_dataready_in_i(i); --- reading_trmF2(i) <= reply_packet_num_in_i(i*c_NUM_WIDTH+1) and not reply_packet_num_in_i(i*c_NUM_WIDTH) --- and REPLY_reading_trm(i) and reply_dataready_in_i(i); --- reading_trmF3(i) <= reply_packet_num_in_i(i*c_NUM_WIDTH+1) and reply_packet_num_in_i(i*c_NUM_WIDTH) --- and REPLY_reading_trm(i) and reply_dataready_in_i(i); end generate; gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate @@ -536,25 +524,13 @@ INIT_DATAREADY_OUT <= buf_INIT_DATAREADY_OUT; - reg_timer_ticks : process(CLK) - begin - if rising_edge(CLK) then - timer_us_tick <= CTRL_TIMER_TICK(0); - timer_ms_tick <= CTRL_TIMER_TICK(1); - end if; - end process; - ---------------------------------- --Check for Timeouts ---------------------------------- - proc_reg_setting : process (CLK) - begin - if rising_edge(CLK) then - reg_CTRL_TIMEOUT_TIME <= unsigned(CTRL_TIMEOUT_TIME); - timeout_found <= or_all(connection_timed_out); - end if; - end process; + reg_CTRL_TIMEOUT_TIME <= unsigned(CTRL_TIMEOUT_TIME) when rising_edge(CLK); + timeout_found <= or_all(connection_timed_out) when rising_edge(CLK); + -- proc_timeout_counters : process (CLK) -- begin diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 3d50a50..9eb5f85 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2003,193 +2003,269 @@ end component; end component; +component trb_net16_med_ecp3_sfp is + generic( + SERDES_NUM : integer range 0 to 3 := 0; + EXT_CLOCK : integer range 0 to 1 := c_NO; + USE_200_MHZ: integer range 0 to 1 := c_YES + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end component; +component trb_net16_med_ecp3_sfp_4_onboard is + generic( + REVERSE_ORDER : integer range 0 to 1 := c_NO + -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" + ); + port( + CLK : in std_logic; -- SerDes clock + SYSCLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(3 downto 0); + MED_READ_OUT : out std_logic_vector(3 downto 0); + MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); + MED_READ_IN : in std_logic_vector(3 downto 0); + REFCLK2CORE_OUT : out std_logic; + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(3 downto 0); + SD_RXD_N_IN : in std_logic_vector(3 downto 0); + SD_TXD_P_OUT : out std_logic_vector(3 downto 0); + SD_TXD_N_OUT : out std_logic_vector(3 downto 0); + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + -- Status and control port + STAT_OP : out std_logic_vector (4*16-1 downto 0); + CTRL_OP : in std_logic_vector (4*16-1 downto 0); + STAT_DEBUG : out std_logic_vector (64*4-1 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); +end component; +component trb_net16_med_16_CC is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; - component trb_net16_med_16_CC is - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_VALID_OUT : out std_logic; - DATA_CTRL_OUT : out std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_CTRL_IN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(63 downto 0) - ); - end component; + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) + ); +end component; - component trb_net16_med_16_IC is - generic( - DATA_CLK_OUT_PHASE : std_logic := '1' - ); - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; +component trb_net16_med_16_IC is +generic( + DATA_CLK_OUT_PHASE : std_logic := '1' +); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_VALID_OUT : out std_logic; - DATA_CTRL_OUT : out std_logic; - DATA_CLK_OUT : out std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_VALID_IN : in std_logic; - DATA_CTRL_IN : in std_logic; - DATA_CLK_IN : in std_logic; + --Internal Connection + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; - STAT_OP : out std_logic_vector(15 downto 0); - CTRL_OP : in std_logic_vector(15 downto 0); - STAT_DEBUG : out std_logic_vector(63 downto 0) - ); - end component; + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_CLK_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + DATA_CLK_IN : in std_logic; + + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) + ); +end component; - component trb_net16_med_tlk is - port ( - RESET : in std_logic; - CLK : in std_logic; - TLK_CLK : in std_logic; - TLK_ENABLE : out std_logic; - TLK_LCKREFN : out std_logic; - TLK_LOOPEN : out std_logic; - TLK_PRBSEN : out std_logic; - TLK_RXD : in std_logic_vector(15 downto 0); - TLK_RX_CLK : in std_logic; - TLK_RX_DV : in std_logic; - TLK_RX_ER : in std_logic; - TLK_TXD : out std_logic_vector(15 downto 0); - TLK_TX_EN : out std_logic; - TLK_TX_ER : out std_logic; - SFP_LOS : in std_logic; - SFP_TX_DIS : out std_logic; - MED_DATAREADY_IN : in std_logic; - MED_READ_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - STAT : out std_logic_vector (63 downto 0); - STAT_MONITOR : out std_logic_vector ( 100 downto 0); - STAT_OP : out std_logic_vector (15 downto 0); - CTRL_OP : in std_logic_vector (15 downto 0) - --connect STAT(0) to LED - ); - end component; +component trb_net16_med_tlk is + port ( + RESET : in std_logic; + CLK : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + MED_DATAREADY_IN : in std_logic; + MED_READ_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + STAT : out std_logic_vector (63 downto 0); + STAT_MONITOR : out std_logic_vector ( 100 downto 0); + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0) + --connect STAT(0) to LED + ); +end component; - component trb_net_onewire is - generic( - USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; - CLK_PERIOD : integer := 10 --clk period in ns - ); - port( - CLK : in std_logic; - RESET : in std_logic; - READOUT_ENABLE_IN : in std_logic := '1'; - --connection to 1-wire interface - ONEWIRE : inout std_logic; - MONITOR_OUT : out std_logic; - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - ID_OUT : out std_logic_vector(63 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; +component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic := '1'; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + MONITOR_OUT : out std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); +end component; - component trb_net_onewire_listener is - port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - MONITOR_IN : in std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(2 downto 0); - WRITE_OUT: out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - ID_OUT : out std_logic_vector(63 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; +component trb_net_onewire_listener is + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + MONITOR_IN : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); +end component; - component trb_net16_obuf is - generic ( - DATA_COUNT_WIDTH : integer := 5; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - -- Internal direction port - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - -- Status and control port - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0); - CTRL_SETTINGS : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (31 downto 0); - TIMER_TICKS_IN : in std_logic_vector (1 downto 0) - ); - end component; +component trb_net16_obuf is + generic ( + DATA_COUNT_WIDTH : integer := 5; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 6 := std_SBUF_VERSION + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + -- Status and control port + STAT_BUFFER: out std_logic_vector (31 downto 0); + CTRL_BUFFER: in std_logic_vector (31 downto 0); + CTRL_SETTINGS : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0); + TIMER_TICKS_IN : in std_logic_vector (1 downto 0) + ); +end component; @@ -2198,925 +2274,925 @@ end component; - component trb_net16_obuf_nodata is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_OUT: out std_logic; - MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_IN: in std_logic; - --STAT - STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0); - STAT_DEBUG : out std_logic_vector (31 downto 0) - ); - end component; +component trb_net16_obuf_nodata is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + --STAT + STAT_BUFFER: out std_logic_vector (31 downto 0); + CTRL_BUFFER: in std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0) + ); +end component; - component pll_in100_out100 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - LOCK: out std_logic - ); - end component; +component pll_in100_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic + ); +end component; - component pll_in100_out20 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic - ); - end component; +component pll_in100_out20 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); +end component; - component pll_in200_out100 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - LOCK: out std_logic - ); - end component; +component pll_in200_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic + ); +end component; - component pll_in100_out25 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic - ); - end component; +component pll_in100_out25 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); +end component; - component pll25 is - port( - CLK : in std_logic; - RESET : in std_logic; - CLKOP : out std_logic; - CLKOK : out std_logic; - LOCK : out std_logic - ); - end component; +component pll25 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + CLKOK : out std_logic; + LOCK : out std_logic + ); +end component; - component pll_in25_out100 is - port ( - CLK: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic - ); - end component; +component pll_in25_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); +end component; - component trb_net_pattern_gen is - generic ( - WIDTH : integer := 6 - ); - port( - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) - ); - end component; +component trb_net_pattern_gen is + generic ( + WIDTH : integer := 6 + ); + port( + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0) + ); +end component; - component trb_net_priority_arbiter is - generic ( - WIDTH : integer := 2 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL: in STD_LOGIC_VECTOR (9 downto 0) - ); - end component; - - - - component pulse_sync is - port( - CLK_A_IN : in std_logic; - RESET_A_IN : in std_logic; - PULSE_A_IN : in std_logic; - CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; - PULSE_B_OUT : out std_logic +component trb_net_priority_arbiter is + generic ( + WIDTH : integer := 2 ); - end component; + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); + RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); + ENABLE : in std_logic; + CTRL: in STD_LOGIC_VECTOR (9 downto 0) + ); +end component; - component ram_dp is - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - dout1 : out std_logic_vector(width-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); - end component; +component pulse_sync is + port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); +end component; +component ram_dp is + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + dout1 : out std_logic_vector(width-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); +end component; - component ram_dp_rw - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); - end component; +component ram_dp_rw + generic( + depth : integer := 3; + width : integer := 16 + ); + port( + CLK : in std_logic; + wr1 : in std_logic; + a1 : in std_logic_vector(depth-1 downto 0); + din1 : in std_logic_vector(width-1 downto 0); + a2 : in std_logic_vector(depth-1 downto 0); + dout2 : out std_logic_vector(width-1 downto 0) + ); +end component; - component trb_net16_regIO is - generic ( - NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers - NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers - --standard values for output registers - INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); - --set to 0 for unused ctrl registers to save resources - USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); - --set to 0 for each unused bit in a register - USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; - HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - CLOCK_FREQ : integer range 1 to 200 := 100 --MHz - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - --Port to write Unique ID (-> 1-wire) - IDRAM_DATA_IN : in std_logic_vector(15 downto 0); - IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); - IDRAM_WR_IN : in std_logic; - - --Informations - MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); - TRIGGER_MONITOR : in std_logic; - GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds - LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency - TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger - TIMER_US_TICK : out std_logic; --1 tick every microsecond - TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds - - --Common Register in / out - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); - --Custom Register in / out - REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); - REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); - COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0); - COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0); - STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); - CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); - --Internal Data Port - DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - DAT_READ_ENABLE_OUT : out std_logic; - DAT_WRITE_ENABLE_OUT: out std_logic; - DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); - DAT_DATAREADY_IN : in std_logic; - DAT_NO_MORE_DATA_IN : in std_logic; - DAT_WRITE_ACK_IN : in std_logic; - DAT_UNKNOWN_ADDR_IN : in std_logic; - DAT_TIMEOUT_OUT : out std_logic; - - --Additional write access to ctrl registers - STAT : out std_logic_vector(31 downto 0); - STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) - ); - end component; +component trb_net16_regIO is + generic ( + NUM_STAT_REGS : integer range 0 to 6 := 4; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQ : integer range 1 to 200 := 100 --MHz + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + + --Port to write Unique ID (-> 1-wire) + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + + --Informations + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + TRIGGER_MONITOR : in std_logic; + GLOBAL_TIME : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_US_TICK : out std_logic; --1 tick every microsecond + TIMER_MS_TICK : out std_logic; --1 tick every 1024 microseconds + + --Common Register in / out + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); + --Custom Register in / out + REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector((std_COMSTATREG)-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector((std_COMCTRLREG)-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0); + --Internal Data Port + DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + DAT_NO_MORE_DATA_IN : in std_logic; + DAT_WRITE_ACK_IN : in std_logic; + DAT_UNKNOWN_ADDR_IN : in std_logic; + DAT_TIMEOUT_OUT : out std_logic; + + --Additional write access to ctrl registers + STAT : out std_logic_vector(31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector(15 downto 0) + ); +end component; - component trb_net16_regio_bus_handler is - generic( - PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3; - PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); - PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) - ); - port( - CLK : in std_logic; - RESET : in std_logic; - DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - DAT_READ_ENABLE_IN : in std_logic; -- read pulse - DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse - DAT_TIMEOUT_IN : in std_logic; -- access timed out - DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested - DAT_WRITE_ACK_OUT : out std_logic; -- data accepted - DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - - BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); - BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); - BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); - - BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0); - BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); - - STAT_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; +component trb_net16_regio_bus_handler is + generic( + PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3; + PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0')); + PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0) + ); + port( + CLK : in std_logic; + RESET : in std_logic; + DAT_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + DAT_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + DAT_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + DAT_READ_ENABLE_IN : in std_logic; -- read pulse + DAT_WRITE_ENABLE_IN : in std_logic; -- write pulse + DAT_TIMEOUT_IN : in std_logic; -- access timed out + DAT_DATAREADY_OUT : out std_logic; -- your data, master, as requested + DAT_WRITE_ACK_OUT : out std_logic; -- data accepted + DAT_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + DAT_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + + BUS_ADDR_OUT : out std_logic_vector(PORT_NUMBER*16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(PORT_NUMBER*32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ENABLE_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_TIMEOUT_OUT : out std_logic_vector(PORT_NUMBER-1 downto 0); + + BUS_DATA_IN : in std_logic_vector(32*PORT_NUMBER-1 downto 0); + BUS_DATAREADY_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_WRITE_ACK_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_NO_MORE_DATA_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + BUS_UNKNOWN_ADDR_IN : in std_logic_vector(PORT_NUMBER-1 downto 0); + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); +end component; - component trb_net_reset_handler is - generic( - RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff" - ); - port( - CLEAR_IN : in std_logic; -- reset input (high active, async) - CLEAR_N_IN : in std_logic; -- reset input (low active, async) - CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock - PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async) - RESET_IN : in std_logic; -- general reset signal (SYSCLK) - TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK) - CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE! - RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK) - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; +component trb_net_reset_handler is + generic( + RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff" + ); + port( + CLEAR_IN : in std_logic; -- reset input (high active, async) + CLEAR_N_IN : in std_logic; -- reset input (low active, async) + CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock + PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async) + RESET_IN : in std_logic; -- general reset signal (SYSCLK) + TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK) + CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE! + RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK) + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; - component rom_16x8 is - generic( - INIT0 : std_logic_vector(15 downto 0) := x"0000"; - INIT1 : std_logic_vector(15 downto 0) := x"0000"; - INIT2 : std_logic_vector(15 downto 0) := x"0000"; - INIT3 : std_logic_vector(15 downto 0) := x"0000"; - INIT4 : std_logic_vector(15 downto 0) := x"0000"; - INIT5 : std_logic_vector(15 downto 0) := x"0000"; - INIT6 : std_logic_vector(15 downto 0) := x"0000"; - INIT7 : std_logic_vector(15 downto 0) := x"0000" - ); - port( - CLK : in std_logic; - a : in std_logic_vector(2 downto 0); - dout : out std_logic_vector(15 downto 0) - ); - end component; +component rom_16x8 is + generic( + INIT0 : std_logic_vector(15 downto 0) := x"0000"; + INIT1 : std_logic_vector(15 downto 0) := x"0000"; + INIT2 : std_logic_vector(15 downto 0) := x"0000"; + INIT3 : std_logic_vector(15 downto 0) := x"0000"; + INIT4 : std_logic_vector(15 downto 0) := x"0000"; + INIT5 : std_logic_vector(15 downto 0) := x"0000"; + INIT6 : std_logic_vector(15 downto 0) := x"0000"; + INIT7 : std_logic_vector(15 downto 0) := x"0000" + ); + port( + CLK : in std_logic; + a : in std_logic_vector(2 downto 0); + dout : out std_logic_vector(15 downto 0) + ); +end component; - component trb_net16_rx_control is - port( - RESET_IN : in std_logic; - QUAD_RST_IN : in std_logic; - -- raw data from SerDes receive path - CLK_IN : in std_logic; - RX_DATA_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; - RX_CV_IN : in std_logic; - RX_DISP_ERR_IN : in std_logic; - RX_ALLOW_IN : in std_logic; - -- media interface - SYSCLK_IN : in std_logic; -- 100MHz master clock - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - -- request retransmission in case of error while receiving - REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse - REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); - -- command decoding - START_RETRANSMIT_OUT : out std_logic; - START_POSITION_OUT : out std_logic_vector( 7 downto 0); - -- reset handling - SEND_RESET_WORDS_OUT : out std_logic; - MAKE_TRBNET_RESET_OUT : out std_logic; - -- Status signals - PACKET_TIMEOUT_OUT : out std_logic; - ENABLE_CORRECTION_IN : in std_logic; - -- Debugging - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(95 downto 0) - ); - end component; +component trb_net16_rx_control is + port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse + REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- command decoding + START_RETRANSMIT_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + ENABLE_CORRECTION_IN : in std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(95 downto 0) + ); +end component; - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - DEBUG_OUT : out std_logic_vector(15 downto 0); - STAT_BUFFER : out STD_LOGIC - ); - end component; +component trb_net16_sbuf is + generic ( + VERSION : integer := 0 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN : in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); + -- Port to synchronous output. + SYN_DATAREADY_OUT : out STD_LOGIC; + SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0); + SYN_READ_IN : in STD_LOGIC; + -- Status and control port + DEBUG_OUT : out std_logic_vector(15 downto 0); + STAT_BUFFER : out STD_LOGIC + ); +end component; - component trb_net_sbuf is - generic ( - DATA_WIDTH : integer := 18; - VERSION: integer := std_SBUF_VERSION); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - DEBUG_OUT : out std_logic_vector(15 downto 0); - STAT_BUFFER: out STD_LOGIC - ); - end component; - component trb_net_sbuf2 is - generic ( - DATA_WIDTH : integer := 18 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; +component trb_net_sbuf is + generic ( + DATA_WIDTH : integer := 18; + VERSION: integer := std_SBUF_VERSION); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + DEBUG_OUT : out std_logic_vector(15 downto 0); + STAT_BUFFER: out STD_LOGIC + ); +end component; - component trb_net_sbuf3 is - generic ( - DATA_WIDTH : integer := 18 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - component trb_net_sbuf4 is - generic ( - DATA_WIDTH : integer := 18 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; +component trb_net_sbuf2 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); +end component; - component trb_net_sbuf5 is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- input - COMB_DATAREADY_IN : in std_logic; - COMB_next_READ_OUT : out std_logic; - COMB_DATA_IN : in std_logic_vector(18 downto 0); - -- output - SYN_DATAREADY_OUT : out std_logic; - SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word - SYN_READ_IN : in std_logic; - -- Status and control port - DEBUG : out std_logic_vector(7 downto 0); - DEBUG_BSM : out std_logic_vector(3 downto 0); - DEBUG_WCNT : out std_logic_vector(4 downto 0); - STAT_BUFFER : out std_logic +component trb_net_sbuf3 is + generic ( + DATA_WIDTH : integer := 18 ); - end component; + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); +end component; - component trb_net_sbuf6 is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- input - COMB_DATAREADY_IN : in std_logic; - COMB_next_READ_OUT : out std_logic; - COMB_DATA_IN : in std_logic_vector(18 downto 0); - -- output - SYN_DATAREADY_OUT : out std_logic; - SYN_DATA_OUT : out std_logic_vector(18 downto 0); - SYN_READ_IN : in std_logic; - -- Status and control port - DEBUG : out std_logic_vector(7 downto 0); - DEBUG_BSM : out std_logic_vector(3 downto 0); - DEBUG_WCNT : out std_logic_vector(4 downto 0); - STAT_BUFFER : out std_logic +component trb_net_sbuf4 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC ); - end component; +end component; - component slv_mac_memory is - port( - CLK : in std_logic; - RESET : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(7 downto 0); - MEM_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +component trb_net_sbuf5 is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- input + COMB_DATAREADY_IN : in std_logic; + COMB_next_READ_OUT : out std_logic; + COMB_DATA_IN : in std_logic_vector(18 downto 0); + -- output + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word + SYN_READ_IN : in std_logic; + -- Status and control port + DEBUG : out std_logic_vector(7 downto 0); + DEBUG_BSM : out std_logic_vector(3 downto 0); + DEBUG_WCNT : out std_logic_vector(4 downto 0); + STAT_BUFFER : out std_logic + ); +end component; + +component trb_net_sbuf6 is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- input + COMB_DATAREADY_IN : in std_logic; + COMB_next_READ_OUT : out std_logic; + COMB_DATA_IN : in std_logic_vector(18 downto 0); + -- output + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector(18 downto 0); + SYN_READ_IN : in std_logic; + -- Status and control port + DEBUG : out std_logic_vector(7 downto 0); + DEBUG_BSM : out std_logic_vector(3 downto 0); + DEBUG_WCNT : out std_logic_vector(4 downto 0); + STAT_BUFFER : out std_logic + ); end component; +component slv_mac_memory is + port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end component; - component slv_register is - generic( - RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; +component slv_register is + generic( + RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end component; - component spi_databus_memory is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - BUS_ADDR_IN : in std_logic_vector(5 downto 0); - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - BUS_ACK_OUT : out std_logic; - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - -- state machine connections - BRAM_ADDR_IN : in std_logic_vector(7 downto 0); - BRAM_WR_D_OUT : out std_logic_vector(7 downto 0); - BRAM_RD_D_IN : in std_logic_vector(7 downto 0); - BRAM_WE_IN : in std_logic; - -- Status lines - STAT : out std_logic_vector(63 downto 0) -- DEBUG - ); - end component; +component spi_databus_memory is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_ADDR_IN : in std_logic_vector(5 downto 0); + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- state machine connections + BRAM_ADDR_IN : in std_logic_vector(7 downto 0); + BRAM_WR_D_OUT : out std_logic_vector(7 downto 0); + BRAM_RD_D_IN : in std_logic_vector(7 downto 0); + BRAM_WE_IN : in std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG + ); +end component; - component spi_dpram_32_to_8 is - port ( - DataInA: in std_logic_vector(31 downto 0); - DataInB: in std_logic_vector(7 downto 0); - AddressA: in std_logic_vector(5 downto 0); - AddressB: in std_logic_vector(7 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(31 downto 0); - QB: out std_logic_vector(7 downto 0)); - end component; +component spi_dpram_32_to_8 is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(7 downto 0); + AddressA: in std_logic_vector(5 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(7 downto 0)); +end component; - component spi_slim is - port( - SYSCLK : in std_logic; -- 100MHz sysclock - RESET : in std_logic; -- synchronous reset - -- Command interface - START_IN : in std_logic; -- one start pulse - BUSY_OUT : out std_logic; -- SPI transactions are ongoing - CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte - ADL_IN : in std_logic_vector(7 downto 0); -- low address byte - ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte - ADH_IN : in std_logic_vector(7 downto 0); -- high address byte - MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD) - TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next - TX_RD_OUT : out std_logic; - RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte - RX_WR_OUT : out std_logic; - TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD - -- SPI interface - SPI_SCK_OUT : out std_logic; - SPI_CS_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - -- DEBUG - CLK_EN_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - end component; +component spi_slim is + port( + SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + ADL_IN : in std_logic_vector(7 downto 0); -- low address byte + ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte + ADH_IN : in std_logic_vector(7 downto 0); -- high address byte + MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD) + TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next + TX_RD_OUT : out std_logic; + RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte + RX_WR_OUT : out std_logic; + TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end component; - component spi_master is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - BUS_READ_IN : in std_logic; - BUS_WRITE_IN : in std_logic; - BUS_BUSY_OUT : out std_logic; - BUS_ACK_OUT : out std_logic; - BUS_ADDR_IN : in std_logic_vector(0 downto 0); - BUS_DATA_IN : in std_logic_vector(31 downto 0); - BUS_DATA_OUT : out std_logic_vector(31 downto 0); - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - -- BRAM for read/write data - BRAM_A_OUT : out std_logic_vector(7 downto 0); - BRAM_WR_D_IN : in std_logic_vector(7 downto 0); - BRAM_RD_D_OUT : out std_logic_vector(7 downto 0); - BRAM_WE_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; +component spi_master is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + BUS_READ_IN : in std_logic; + BUS_WRITE_IN : in std_logic; + BUS_BUSY_OUT : out std_logic; + BUS_ACK_OUT : out std_logic; + BUS_ADDR_IN : in std_logic_vector(0 downto 0); + BUS_DATA_IN : in std_logic_vector(31 downto 0); + BUS_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- BRAM for read/write data + BRAM_A_OUT : out std_logic_vector(7 downto 0); + BRAM_WR_D_IN : in std_logic_vector(7 downto 0); + BRAM_RD_D_OUT : out std_logic_vector(7 downto 0); + BRAM_WE_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); +end component; - component signal_sync is - generic( - WIDTH : integer := 1; -- - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output - ); - end component; +component signal_sync is + generic( + WIDTH : integer := 1; -- + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + ); +end component; - component trb_net16_term is - generic ( - USE_APL_PORT : integer range 0 to 1 := c_YES; - --even when 0, ERROR_PACKET_IN is used for automatic replys - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these need to be available while relase_trg is high - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN : in std_logic; +component trb_net16_term is + generic ( + USE_APL_PORT : integer range 0 to 1 := c_YES; + --even when 0, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN : in std_logic; + + INT_DATAREADY_IN : in std_logic; + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT : out std_logic; + APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) + ); +end component; - INT_DATAREADY_IN : in std_logic; - INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT : out std_logic; - APL_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) - ); - end component; +component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic + ); +end component; - component trb_net16_term_buf is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic - ); - end component; +component trb_net16_term_ibuf is + generic( + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + -- Internal direction port + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + INT_ERROR_OUT: out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER: out std_logic_vector (31 downto 0) + ); +end component; - component trb_net16_term_ibuf is - generic( - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN: in std_logic; - MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT: out std_logic; - MED_ERROR_IN: in std_logic_vector (2 downto 0); - -- Internal direction port - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - INT_ERROR_OUT: out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER: out std_logic_vector (31 downto 0) - ); - end component; +component trb_net16_trigger is + generic ( + USE_TRG_PORT : integer range 0 to 1 := c_YES; + --even when NO, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high only + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + + -- Trigger information output + TRG_TYPE_OUT : out std_logic_vector (3 downto 0); + TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); + TRG_CODE_OUT : out std_logic_vector (7 downto 0); + TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0); + TRG_RECEIVED_OUT : out std_logic; + TRG_RELEASE_IN : in std_logic; + TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) + ); +end component; - component trb_net16_trigger is - generic ( - USE_TRG_PORT : integer range 0 to 1 := c_YES; - --even when NO, ERROR_PACKET_IN is used for automatic replys - SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE - --if secure_mode is not used, apl must provide error pattern and dtype until - --next trigger comes in. In secure mode these need to be available while relase_trg is high only - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INT_DATAREADY_OUT: out std_logic; - INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_IN: in std_logic; - - INT_DATAREADY_IN: in std_logic; - INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_READ_OUT: out std_logic; - - -- Trigger information output - TRG_TYPE_OUT : out std_logic_vector (3 downto 0); - TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); - TRG_CODE_OUT : out std_logic_vector (7 downto 0); - TRG_INFORMATION_OUT : out std_logic_vector (23 downto 0); - TRG_RECEIVED_OUT : out std_logic; - TRG_RELEASE_IN : in std_logic; - TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) - ); - end component; +component trb_net16_tx_control is + port( + TXCLK_IN : in std_logic; + RXCLK_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; - component trb_net16_tx_control is - port( - TXCLK_IN : in std_logic; - RXCLK_IN : in std_logic; - SYSCLK_IN : in std_logic; - RESET_IN : in std_logic; + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; - TX_DATA_IN : in std_logic_vector(15 downto 0); - TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); - TX_WRITE_IN : in std_logic; - TX_READ_OUT : out std_logic; + REQUEST_RETRANSMIT_IN : in std_logic; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); - TX_DATA_OUT : out std_logic_vector( 7 downto 0); - TX_K_OUT : out std_logic; + START_RETRANSMIT_IN : in std_logic; + START_POSITION_IN : in std_logic_vector( 7 downto 0); - REQUEST_RETRANSMIT_IN : in std_logic; - REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); + SEND_LINK_RESET_IN : in std_logic; + TX_ALLOW_IN : in std_logic; - START_RETRANSMIT_IN : in std_logic; - START_POSITION_IN : in std_logic_vector( 7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) + ); +end component; - SEND_LINK_RESET_IN : in std_logic; - TX_ALLOW_IN : in std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0); - STAT_REG_OUT : out std_logic_vector(31 downto 0) - ); - end component; +component wide_adder_17x16 is + generic( + SIZE : integer := 16; + WORDS: integer := 17 --fixed + ); + port( + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); + START_IN : in std_logic; + VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); + RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); + OVERFLOW_OUT : out std_logic; + READY_OUT : out std_logic + ); +end component; - component wide_adder_17x16 is - generic( - SIZE : integer := 16; - WORDS: integer := 17 --fixed - ); +component trb_net_bridge_etrax_apl is port( - CLK : in std_logic; - CLK_EN : in std_logic; - RESET : in std_logic; - INPUT_IN : in std_logic_vector(SIZE*WORDS-1 downto 0); - START_IN : in std_logic; - VAL_ENABLE_IN: in std_logic_vector(WORDS-1 downto 0); - RESULT_OUT : out std_logic_vector(SIZE-1 downto 0); - OVERFLOW_OUT : out std_logic; - READY_OUT : out std_logic + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); + APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); + CPU_READ : in STD_LOGIC; + CPU_WRITE : in STD_LOGIC; + CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); + CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); + CPU_DATAREADY_OUT : out std_logic; + CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0); + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) ); - end component; - - - component trb_net_bridge_etrax_apl is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0); - APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0); - APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0); - APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0); - APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0); - APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0); - APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0); - CPU_READ : in STD_LOGIC; - CPU_WRITE : in STD_LOGIC; - CPU_DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0); - CPU_DATA_IN : in STD_LOGIC_VECTOR (31 downto 0); - CPU_DATAREADY_OUT : out std_logic; - CPU_ADDRESS : in STD_LOGIC_VECTOR (15 downto 0); - STAT : out std_logic_vector (31 downto 0); - CTRL : in std_logic_vector (31 downto 0) - ); - end component; +end component; end package; \ No newline at end of file -- 2.43.0