From 6e9a93bd08a969e73de49483fd1dbf80b3bf2cb5 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 5 Oct 2010 09:35:59 +0000 Subject: [PATCH] *** empty log message *** --- gbe_ecp2m/tb_gbe_buf.vhd | 171 +-------- gbe_ecp2m/trb_net16_gbe_buf.vhd | 431 ++++++++++++++-------- gbe_ecp2m/trb_net16_gbe_frame_constr.vhd | 28 +- gbe_ecp2m/trb_net16_gbe_frame_trans.vhd | 10 +- gbe_ecp2m/trb_net16_gbe_packet_constr.vhd | 31 +- gbe_ecp2m/trb_net16_gbe_setup.vhd | 56 ++- gbe_ecp2m/trb_net16_ipu2gbe.vhd | 29 +- 7 files changed, 390 insertions(+), 366 deletions(-) diff --git a/gbe_ecp2m/tb_gbe_buf.vhd b/gbe_ecp2m/tb_gbe_buf.vhd index 78db3be..8347c02 100755 --- a/gbe_ecp2m/tb_gbe_buf.vhd +++ b/gbe_ecp2m/tb_gbe_buf.vhd @@ -13,11 +13,10 @@ ARCHITECTURE behavior OF testbench IS USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 ); port( - CLK : in std_logic; - TEST_CLK : in std_logic; -- only for simulation! - CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - RESET : IN std_logic; + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode +RESET : IN std_logic; GSR_N : IN std_logic; STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0); ------------------------ @@ -76,85 +75,7 @@ ARCHITECTURE behavior OF testbench IS SFP_TXD_P_OUT : OUT std_logic; SFP_TXD_N_OUT : OUT std_logic; SFP_TXDIS_OUT : OUT std_logic; - IG_CTS_CTR_TST : OUT std_logic_vector(2 downto 0); - IG_REM_CTR_TST : OUT std_logic_vector(3 downto 0); - IG_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0); - IG_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0); - IG_DATA_TST : OUT std_logic_vector(15 downto 0); - IG_WCNT_TST : OUT std_logic_vector(15 downto 0); - IG_RCNT_TST : OUT std_logic_vector(16 downto 0); - IG_RD_EN_TST : OUT std_logic; - IG_WR_EN_TST : OUT std_logic; - IG_EMPTY_TST : OUT std_logic; - IG_AEMPTY_TST : OUT std_logic; - IG_FULL_TST : OUT std_logic; - IG_AFULL_TST : OUT std_logic; - PC_WR_EN_TST : OUT std_logic; - PC_DATA_TST : OUT std_logic_vector(7 downto 0); - PC_READY_TST : OUT std_logic; - PC_START_OF_SUB_TST : OUT std_logic; - PC_END_OF_DATA_TST : OUT std_logic; - PC_ALL_CTR_TST : OUT std_logic_vector(4 downto 0); - PC_SUB_CTR_TST : OUT std_logic_vector(4 downto 0); - PC_SUB_SIZE_TST : OUT std_logic_vector(31 downto 0); - PC_TRIG_NR_TST : OUT std_logic_vector(31 downto 0); - PC_PADDING_TST : OUT std_logic; - PC_DECODING_TST : OUT std_logic_vector(31 downto 0); - PC_EVENT_ID_TST : OUT std_logic_vector(31 downto 0); - PC_QUEUE_DEC_TST : OUT std_logic_vector(31 downto 0); - PC_BSM_CONSTR_TST : OUT std_logic_vector(3 downto 0); - PC_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0); - PC_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0); - PC_SHF_EMPTY_TST : OUT std_logic; - PC_SHF_FULL_TST : OUT std_logic; - PC_SHF_WR_EN_TST : OUT std_logic; - PC_SHF_RD_EN_TST : OUT std_logic; - PC_SHF_Q_TST : OUT std_logic_vector(7 downto 0); - PC_DF_EMPTY_TST : OUT std_logic; - PC_DF_FULL_TST : OUT std_logic; - PC_DF_WR_EN_TST : OUT std_logic; - PC_DF_RD_EN_TST : OUT std_logic; - PC_DF_Q_TST : OUT std_logic_vector(7 downto 0); - PC_BYTES_LOADED_TST : OUT std_logic_vector(15 downto 0); - PC_SIZE_LEFT_TST : OUT std_logic_vector(31 downto 0); - PC_SUB_SIZE_TO_SAVE_TST : OUT std_logic_vector(31 downto 0); - PC_SUB_SIZE_LOADED_TST : OUT std_logic_vector(31 downto 0); - PC_SUB_BYTES_LOADED_TST : OUT std_logic_vector(31 downto 0); - PC_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0); - PC_ACT_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0); - FC_WR_EN_TST : OUT std_logic; - FC_DATA_TST : OUT std_logic_vector(7 downto 0); - FC_H_READY_TST : OUT std_logic; - FC_READY_TST : OUT std_logic; - FC_IP_SIZE_TST : OUT std_logic_vector(15 downto 0); - FC_UDP_SIZE_TST : OUT std_logic_vector(15 downto 0); - FC_IDENT_TST : OUT std_logic_vector(15 downto 0); - FC_FLAGS_OFFSET_TST : OUT std_logic_vector(15 downto 0); - FC_SOD_TST : OUT std_logic; - FC_EOD_TST : OUT std_logic; - FC_BSM_CONSTR_TST : OUT std_logic_vector(7 downto 0); - FC_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0); - FT_DATA_TST : OUT std_logic_vector(8 downto 0); - FT_TX_EMPTY_TST : OUT std_logic; - FT_START_OF_PACKET_TST : OUT std_logic; - FT_BSM_INIT_TST : OUT std_logic_vector(3 downto 0); - FT_BSM_MAC_TST : OUT std_logic_vector(3 downto 0); - FT_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0); - MAC_HADDR_TST : OUT std_logic_vector(7 downto 0); - MAC_HDATA_TST : OUT std_logic_vector(7 downto 0); - MAC_HCS_TST : OUT std_logic; - MAC_HWRITE_TST : OUT std_logic; - MAC_HREAD_TST : OUT std_logic; - MAC_HREADY_TST : OUT std_logic; - MAC_HDATA_EN_TST : OUT std_logic; - MAC_FIFOAVAIL_TST : OUT std_logic; - MAC_FIFOEOF_TST : OUT std_logic; - MAC_FIFOEMPTY_TST : OUT std_logic; - MAC_TX_READ_TST : OUT std_logic; - MAC_TX_DONE_TST : OUT std_logic; - PCS_AN_LP_ABILITY_TST : OUT std_logic_vector(15 downto 0); - PCS_AN_COMPLETE_TST : OUT std_logic; - PCS_AN_PAGE_RX_TST : OUT std_logic; + ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0) ); END COMPONENT; @@ -295,8 +216,7 @@ BEGIN GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 ) PORT MAP( CLK => CLK, - CLK_125_TX_IN => '0', - CLK_125_RX_IN => '0', + CLK_125_IN => '0', TEST_CLK => TEST_CLK, RESET => RESET, GSR_N => GSR_N, @@ -356,85 +276,6 @@ BEGIN SFP_PRSNT_N_IN => SFP_PRSNT_N_IN, SFP_LOS_IN => SFP_LOS_IN, SFP_TXDIS_OUT => SFP_TXDIS_OUT, - IG_CTS_CTR_TST => IG_CTS_CTR_TST, - IG_REM_CTR_TST => IG_REM_CTR_TST, - IG_BSM_LOAD_TST => IG_BSM_LOAD_TST, - IG_BSM_SAVE_TST => IG_BSM_SAVE_TST, - IG_DATA_TST => IG_DATA_TST, - IG_WCNT_TST => IG_WCNT_TST, - IG_RCNT_TST => IG_RCNT_TST, - IG_RD_EN_TST => IG_RD_EN_TST, - IG_WR_EN_TST => IG_WR_EN_TST, - IG_EMPTY_TST => IG_EMPTY_TST, - IG_AEMPTY_TST => IG_AEMPTY_TST, - IG_FULL_TST => IG_FULL_TST, - IG_AFULL_TST => IG_AFULL_TST, - PC_WR_EN_TST => PC_WR_EN_TST, - PC_DATA_TST => PC_DATA_TST, - PC_READY_TST => PC_READY_TST, - PC_START_OF_SUB_TST => PC_START_OF_SUB_TST, - PC_END_OF_DATA_TST => PC_END_OF_DATA_TST, - PC_SUB_SIZE_TST => PC_SUB_SIZE_TST, - PC_TRIG_NR_TST => PC_TRIG_NR_TST, - PC_PADDING_TST => PC_PADDING_TST, - PC_DECODING_TST => PC_DECODING_TST, - PC_EVENT_ID_TST => PC_EVENT_ID_TST, - PC_QUEUE_DEC_TST => PC_QUEUE_DEC_TST, - PC_BSM_CONSTR_TST => PC_BSM_CONSTR_TST, - PC_BSM_LOAD_TST => PC_BSM_LOAD_TST, - PC_BSM_SAVE_TST => PC_BSM_SAVE_TST, - PC_SHF_EMPTY_TST => PC_SHF_EMPTY_TST, - PC_SHF_FULL_TST => PC_SHF_FULL_TST, - PC_SHF_WR_EN_TST => PC_SHF_WR_EN_TST, - PC_SHF_RD_EN_TST => PC_SHF_RD_EN_TST, - PC_SHF_Q_TST => PC_SHF_Q_TST, - PC_DF_EMPTY_TST => PC_DF_EMPTY_TST, - PC_DF_FULL_TST => PC_DF_FULL_TST, - PC_DF_WR_EN_TST => PC_DF_WR_EN_TST, - PC_DF_RD_EN_TST => PC_DF_RD_EN_TST, - PC_DF_Q_TST => PC_DF_Q_TST, - PC_ALL_CTR_TST => PC_ALL_CTR_TST, - PC_SUB_CTR_TST => PC_SUB_CTR_TST, - PC_BYTES_LOADED_TST => PC_BYTES_LOADED_TST, - PC_SIZE_LEFT_TST => PC_SIZE_LEFT_TST, - PC_SUB_SIZE_TO_SAVE_TST => PC_SUB_SIZE_TO_SAVE_TST, - PC_SUB_SIZE_LOADED_TST => PC_SUB_SIZE_LOADED_TST, - PC_SUB_BYTES_LOADED_TST => PC_SUB_BYTES_LOADED_TST, - PC_QUEUE_SIZE_TST => PC_QUEUE_SIZE_TST, - PC_ACT_QUEUE_SIZE_TST => PC_ACT_QUEUE_SIZE_TST, - FC_WR_EN_TST => FC_WR_EN_TST, - FC_DATA_TST => FC_DATA_TST, - FC_H_READY_TST => FC_H_READY_TST, - FC_READY_TST => FC_READY_TST, - FC_IP_SIZE_TST => FC_IP_SIZE_TST, - FC_UDP_SIZE_TST => FC_UDP_SIZE_TST, - FC_IDENT_TST => FC_IDENT_TST, - FC_FLAGS_OFFSET_TST => FC_FLAGS_OFFSET_TST, - FC_SOD_TST => FC_SOD_TST, - FC_EOD_TST => FC_EOD_TST, - FC_BSM_CONSTR_TST => FC_BSM_CONSTR_TST, - FC_BSM_TRANS_TST => FC_BSM_TRANS_TST, - FT_DATA_TST => FT_DATA_TST, - FT_TX_EMPTY_TST => FT_TX_EMPTY_TST, - FT_START_OF_PACKET_TST => FT_START_OF_PACKET_TST, - FT_BSM_INIT_TST => FT_BSM_INIT_TST, - FT_BSM_MAC_TST => FT_BSM_MAC_TST, - FT_BSM_TRANS_TST => FT_BSM_TRANS_TST, - MAC_HADDR_TST => MAC_HADDR_TST, - MAC_HDATA_TST => MAC_HDATA_TST, - MAC_HCS_TST => MAC_HCS_TST, - MAC_HWRITE_TST => MAC_HWRITE_TST, - MAC_HREAD_TST => MAC_HREAD_TST, - MAC_HREADY_TST => MAC_HREADY_TST, - MAC_HDATA_EN_TST => MAC_HDATA_EN_TST, - MAC_FIFOAVAIL_TST => MAC_FIFOAVAIL_TST, - MAC_FIFOEOF_TST => MAC_FIFOEOF_TST, - MAC_FIFOEMPTY_TST => MAC_FIFOEMPTY_TST, - MAC_TX_READ_TST => MAC_TX_READ_TST, - MAC_TX_DONE_TST => MAC_TX_DONE_TST, - PCS_AN_LP_ABILITY_TST => PCS_AN_LP_ABILITY_TST, - PCS_AN_COMPLETE_TST => PCS_AN_COMPLETE_TST, - PCS_AN_PAGE_RX_TST => PCS_AN_PAGE_RX_TST, ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT ); diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd index 7dee1b2..46eb018 100755 --- a/gbe_ecp2m/trb_net16_gbe_buf.vhd +++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd @@ -7,7 +7,7 @@ use IEEE.std_logic_arith.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.trb_net16_hub_func.all; +--use work.trb_net16_hub_func.all; use work.trb_net_gbe_components.all; --use work.version.all; @@ -94,6 +94,7 @@ attribute HGROUP : string; -- for whole architecture attribute HGROUP of trb_net16_gbe_buf : architecture is "GBE_BUF_group"; + component tsmac3 port( --------------- clock and reset port declarations ------------------ @@ -423,9 +424,6 @@ signal dbg_q : std_logic_vector(15 downto 0); -- gk 21.07.10 signal allow_large : std_logic; --- gk 23.07.10 -signal reset_fifo : std_logic; - -- gk 28.07.10 signal bytes_sent_ctr : std_logic_vector(31 downto 0); signal monitor_sent : std_logic_vector(31 downto 0); @@ -440,13 +438,32 @@ signal monitor_discfrm : std_logic_vector(31 downto 0); -- gk 02.08.10 signal discfrm_ctr : std_logic_vector(31 downto 0); +-- gk 28.09.10 +signal dbg_reset_fifo : std_logic; +signal db_fifo_rst : std_logic; + +-- gk 30.09.10 +signal fc_rd_en : std_logic; +signal link_ok : std_logic; +signal link_ok_timeout_ctr : std_logic_vector(15 downto 0); + +type linkStates is (ACTIVE, INACTIVE, TIMEOUT, FINALIZE); +signal link_current_state, link_next_state : linkStates; + +signal link_down_ctr : std_logic_vector(15 downto 0); +signal link_down_ctr_lock : std_logic; + +signal link_state : std_logic_vector(3 downto 0); + +signal monitor_empty : std_logic_vector(31 downto 0); + begin stage_ctrl_regs <= STAGE_CTRL_REGS_IN; -- gk 23.04.10 LED_PACKET_SENT_OUT <= pc_ready; -LED_AN_DONE_N_OUT <= not pcs_an_complete; +LED_AN_DONE_N_OUT <= not link_ok; --not pcs_an_complete; -- gk 22.04.10 moved to gbe_setup entity -- PacketConstructor fixed magic values @@ -501,6 +518,12 @@ port map( MONITOR_HDR_IN => monitor_hr, MONITOR_FIFOS_IN => monitor_fifos_q, MONITOR_DISCFRM_IN => monitor_discfrm, + MONITOR_EMPTY_IN => monitor_empty, + MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10 + MONITOR_LINK_DWN_IN(19 downto 16) => link_state, + MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans, + MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans, + MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'), -- gk 01.06.10 DBG_IPU2GBE1_IN => dbg_ipu2gbe1, DBG_IPU2GBE2_IN => dbg_ipu2gbe2, @@ -521,7 +544,8 @@ port map( DBG_FT1_IN => dbg_ft1, DBG_FT2_IN => dbg_ft2, DBG_FIFO_RD_EN_OUT => dbg_rd_en, - DBG_FIFO_Q_IN => dbg_q + DBG_FIFO_Q_IN => dbg_q, + DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10 ); -- IP configurator: allows IP config to change for each event builder @@ -573,28 +597,28 @@ port map( -- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS THE_IPU_INTERFACE: trb_net16_ipu2gbe port map( - CLK => CLK, - RESET => RESET, + CLK => CLK, + RESET => RESET, --Event information coming from CTS - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, --Information sent to CTS --status data, equipped with DHDR CTS_DATA_OUT => cts_data, CTS_DATAREADY_OUT => cts_dataready, - CTS_READOUT_FINISHED_OUT => cts_readout_finished, - CTS_READ_IN => CTS_READ_IN, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => CTS_READ_IN, CTS_LENGTH_OUT => cts_length, - CTS_ERROR_PATTERN_OUT => cts_error_pattern, + CTS_ERROR_PATTERN_OUT => cts_error_pattern, -- Data from Frontends - FEE_DATA_IN => FEE_DATA_IN, + FEE_DATA_IN => FEE_DATA_IN, FEE_DATAREADY_IN => FEE_DATAREADY_IN, FEE_READ_OUT => fee_read, FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, + FEE_BUSY_IN => FEE_BUSY_IN, -- slow control interface START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10 BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10 @@ -622,6 +646,7 @@ port map( MONITOR_OUT(127 downto 96) => monitor_sm, MONITOR_OUT(159 downto 128) => monitor_lr, MONITOR_OUT(191 downto 160) => monitor_fifos, + MONITOR_OUT(223 downto 192) => monitor_empty, DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1, DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2, DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3, @@ -640,10 +665,10 @@ port map( PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr port map( -- ports for user logic - RESET => RESET, - CLK => CLK, - PC_WR_EN_IN => pc_wr_en, - PC_DATA_IN => pc_data, + RESET => RESET, + CLK => CLK, + PC_WR_EN_IN => pc_wr_en, + PC_DATA_IN => pc_data, PC_READY_OUT => pc_ready, PC_START_OF_SUB_IN => pc_sos, PC_END_OF_DATA_IN => pc_eod, @@ -658,15 +683,15 @@ port map( PC_DELAY_IN => pc_delay, -- gk 28.04.10 -- NEW PORTS FC_WR_EN_OUT => fc_wr_en, - FC_DATA_OUT => fc_data, + FC_DATA_OUT => fc_data, FC_H_READY_IN => fc_h_ready, - FC_READY_IN => fc_ready, + FC_READY_IN => fc_ready, FC_IP_SIZE_OUT => fc_ip_size, FC_UDP_SIZE_OUT => fc_udp_size, FC_IDENT_OUT => fc_ident, FC_FLAGS_OFFSET_OUT => fc_flags_offset, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, + FC_SOD_OUT => fc_sod, + FC_EOD_OUT => fc_eod, DEBUG_OUT(31 downto 0) => dbg_pc1, DEBUG_OUT(63 downto 32) => dbg_pc2 ); @@ -675,21 +700,21 @@ port map( MON_PROC : process(CLK) begin if rising_edge(CLK) then - monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0); + monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0); if (dbg_pc1(28) = '1') then - monitor_fifos_q(5 downto 4) <= b"11"; + monitor_fifos_q(5 downto 4) <= b"11"; else - monitor_fifos_q(5 downto 4) <= b"00"; + monitor_fifos_q(5 downto 4) <= b"00"; end if; if (dbg_pc1(30) = '1') then - monitor_fifos_q(7 downto 6) <= b"11"; + monitor_fifos_q(7 downto 6) <= b"11"; else - monitor_fifos_q(7 downto 6) <= b"00"; + monitor_fifos_q(7 downto 6) <= b"00"; end if; if (dbg_fc1(28) = '1') then - monitor_fifos_q(11 downto 8) <= b"1111"; + monitor_fifos_q(11 downto 8) <= b"1111"; else - monitor_fifos_q(11 downto 8) <= b"0000"; + monitor_fifos_q(11 downto 8) <= b"0000"; end if; if (pcs_an_complete = '0') then monitor_fifos_q(15 downto 12) <= b"1111"; @@ -705,7 +730,7 @@ port map( -- ports for user logic RESET => RESET, CLK => CLK, - LINK_OK_IN => pcs_an_complete, -- gk 03.08.10 + LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10 -- WR_EN_IN => fc_wr_en, DATA_IN => fc_data, @@ -733,7 +758,7 @@ port map( FT_DATA_OUT => ft_data, --FT_EOD_OUT => ft_eod, -- gk 04.05.10 FT_TX_EMPTY_OUT => ft_tx_empty, - FT_TX_RD_EN_IN => mac_tx_read, + FT_TX_RD_EN_IN => fc_rd_en, --mac_tx_read, -- gk 30.09.10 FT_START_OF_PACKET_OUT => ft_start_of_packet, FT_TX_DONE_IN => mac_tx_done, FT_TX_DISCFRM_IN => mac_tx_discfrm, @@ -744,11 +769,125 @@ port map( DEBUG_OUT(63 downto 32) => dbg_fc2 ); +--*********************** +-- LINK STATE CONTROL +--*********************** + +-- gk 30.09.10 +fc_rd_en <= '1' when ((link_ok = '1') and (mac_tx_read = '1')) + or (link_ok = '0') + else '0'; + +-- gk 30.09.10 +LINK_STATE_MACHINE_PROC : process(serdes_clk_125) +begin + if rising_edge(serdes_clk_125) then + if (RESET = '1') or (dbg_reset_fifo = '1') then + link_current_state <= INACTIVE; + else + link_current_state <= link_next_state; + end if; + end if; +end process; + +-- gk 30.09.10 +LINK_STATE_MACHINE : process(serdes_clk_125) +begin + case link_current_state is + + when ACTIVE => + link_state <= x"1"; + if (pcs_an_complete = '0') then + link_next_state <= INACTIVE; + else + link_next_state <= link_current_state; + end if; + + when INACTIVE => + link_state <= x"2"; + if (pcs_an_complete = '1') then + link_next_state <= TIMEOUT; + else + link_next_state <= link_current_state; + end if; + + when TIMEOUT => + link_state <= x"3"; + if (pcs_an_complete = '0') then + link_next_state <= INACTIVE; + else + if (link_ok_timeout_ctr = x"ffff") then + link_next_state <= FINALIZE; + else + link_next_state <= link_current_state; + end if; + end if; + + when FINALIZE => + link_state <= x"4"; + if (pcs_an_complete = '0') then + link_next_state <= INACTIVE; + else + if (pc_ready = '1') then + link_next_state <= ACTIVE; + else + link_next_state <= link_current_state; + end if; + end if; + + end case; +end process LINK_STATE_MACHINE; + +-- gk 30.09.10 +LINK_OK_CTR_PROC : process(serdes_clk_125) +begin + if rising_edge(serdes_clk_125) then + if (RESET = '1') or (link_current_state /= TIMEOUT) then + link_ok_timeout_ctr <= (others => '0'); + elsif (link_current_state = TIMEOUT) then + link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1"; + end if; + end if; +end process LINK_OK_CTR_PROC; + +-- gk 30.09.10 +LINK_OK_PROC : process(serdes_clk_125) +begin + if rising_edge(serdes_clk_125) then + if (RESET = '1') then + link_ok <= '0'; + elsif (link_current_state = ACTIVE) then + link_ok <= '1'; + else + link_ok <= '0'; + end if; + end if; +end process LINK_OK_PROC; + +-- gk 30.09.10 +LINK_DOWN_CTR_PROC : process(serdes_clk_125) +begin + if rising_edge(serdes_clk_125) then + if (RESET = '1') then + link_down_ctr <= (others => '0'); + link_down_ctr_lock <= '0'; + elsif (pcs_an_complete = '1') then + link_down_ctr_lock <= '0'; + elsif ((pcs_an_complete = '0') and (link_down_ctr_lock = '0')) then + link_down_ctr <= link_down_ctr + x"1"; + link_down_ctr_lock <= '1'; + end if; + end if; +end process LINK_DOWN_CTR_PROC; + + + + FRAME_TRANSMITTER: trb_net16_gbe_frame_trans port map( CLK => CLK, RESET => RESET, - LINK_OK_IN => pcs_an_complete, -- gk 03.08.10 + LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10 TX_MAC_CLK => serdes_clk_125, TX_EMPTY_IN => ft_tx_empty, START_OF_PACKET_IN => ft_start_of_packet, @@ -794,14 +933,14 @@ imp_gen: if (DO_SIMULATION = 0) generate txmac_clk => serdes_clk_125, rxmac_clk => serdes_clk_125, reset_n => GSR_N, - txmac_clk_en => mac_tx_clk_en, - rxmac_clk_en => mac_rx_clk_en, + txmac_clk_en => mac_tx_clk_en, + rxmac_clk_en => mac_rx_clk_en, ------------------- Input signals to the GMII ---------------- NOT USED - rxd => x"00", + rxd => x"00", rx_dv => '0', rx_er => '0', - col => mac_col, - crs => mac_crs, + col => mac_col, + crs => mac_crs, -------------------- Input signals to the CPU I/F ------------------- haddr => mac_haddr, hdatain => mac_hdataout, @@ -810,24 +949,24 @@ imp_gen: if (DO_SIMULATION = 0) generate hread_n => mac_hread, ---------------- Input signals to the Tx MAC FIFO I/F --------------- tx_fifodata => ft_data(7 downto 0), - tx_fifoavail => mac_fifoavail, + tx_fifoavail => mac_fifoavail, tx_fifoeof => mac_fifoeof, - tx_fifoempty => mac_fifoempty, - tx_sndpaustim => x"0000", - tx_sndpausreq => '0', + tx_fifoempty => mac_fifoempty, + tx_sndpaustim => x"0000", + tx_sndpausreq => '0', tx_fifoctrl => '0', -- always data frame ---------------- Input signals to the Rx MAC FIFO I/F --------------- - rx_fifo_full => '0', + rx_fifo_full => '0', ignore_pkt => '0', ---------------- Output signals from the GMII ----------------------- - txd => pcs_txd, + txd => pcs_txd, tx_en => pcs_tx_en, tx_er => pcs_tx_er, ----------------- Output signals from the CPU I/F ------------------- hdataout => open, - hdataout_en_n => mac_hdata_en, + hdataout_en_n => mac_hdata_en, hready_n => mac_hready, - cpu_if_gbit_en => open, + cpu_if_gbit_en => open, ------------- Output signals from the Tx MAC FIFO I/F --------------- tx_macread => mac_tx_read, tx_discfrm => mac_tx_discfrm, @@ -835,8 +974,8 @@ imp_gen: if (DO_SIMULATION = 0) generate tx_statvec => mac_tx_statevec, -- gk 08.06.10 tx_done => mac_tx_done, ------------- Output signals from the Rx MAC FIFO I/F --------------- - rx_fifo_error => open, - rx_stat_vector => open, + rx_fifo_error => open, + rx_stat_vector => open, rx_dbout => open, rx_write => open, rx_stat_en => open, @@ -849,10 +988,10 @@ imp_gen: if (DO_SIMULATION = 0) generate begin if rising_edge(serdes_clk_125) then if (RESET = '1') then - dbg_ft1 <= (others => '0'); + dbg_ft1 <= (others => '0'); elsif (mac_tx_staten = '1') then dbg_ft1(30 downto 0) <= mac_tx_statevec; - dbg_ft1(31) <= mac_tx_discfrm; + dbg_ft1(31) <= mac_tx_discfrm; end if; end if; end process dbg_statevec_proc; @@ -863,45 +1002,45 @@ imp_gen: if (DO_SIMULATION = 0) generate -- PHY part PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b generic map( - USE_125MHZ_EXTCLK => 0 + USE_125MHZ_EXTCLK => 0 ) port map( - RESET => RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_125_IN => CLK_125_IN, - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd, - FT_TX_EN_IN => pcs_tx_en, - FT_TX_ER_IN => pcs_tx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" + RESET => RESET, + GSR_N => GSR_N, + CLK_125_OUT => serdes_clk_125, + CLK_125_IN => CLK_125_IN, + FT_TX_CLK_EN_OUT => mac_tx_clk_en, + FT_RX_CLK_EN_OUT => mac_rx_clk_en, + --connection to frame transmitter (tsmac) + FT_COL_OUT => mac_col, + FT_CRS_OUT => mac_crs, + FT_TXD_IN => pcs_txd, + FT_TX_EN_IN => pcs_tx_en, + FT_TX_ER_IN => pcs_tx_er, + --SFP Connection + SD_RXD_P_IN => SFP_RXD_P_IN, + SD_RXD_N_IN => SFP_RXD_N_IN, + SD_TXD_P_OUT => SFP_TXD_P_OUT, + SD_TXD_N_OUT => SFP_TXD_N_OUT, + SD_REFCLK_P_IN => SFP_REFCLK_P_IN, + SD_REFCLK_N_IN => SFP_REFCLK_N_IN, + SD_PRSNT_N_IN => SFP_PRSNT_N_IN, + SD_LOS_IN => SFP_LOS_IN, + SD_TXDIS_OUT => SFP_TXDIS_OUT, + -- Autonegotiation stuff + MR_ADV_ABILITY_IN => x"0020", -- full duplex only + MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, + MR_AN_PAGE_RX_OUT => pcs_an_page_rx, + MR_AN_COMPLETE_OUT => pcs_an_complete, + MR_RESET_IN => MR_RESET_IN, + MR_MODE_IN => MR_MODE_IN, + MR_AN_ENABLE_IN => '1', -- do autonegotiation + MR_RESTART_AN_IN => MR_RESTART_IN, + -- Status and control port + STAT_OP => open, + CTRL_OP => x"0000", + STAT_DEBUG => pcs_stat_debug, --open, + CTRL_DEBUG => x"0000_0000_0000_0000" ); end generate serdes_intclk_gen; @@ -909,51 +1048,53 @@ imp_gen: if (DO_SIMULATION = 0) generate -- PHY part PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b generic map( - USE_125MHZ_EXTCLK => 1 + USE_125MHZ_EXTCLK => 1 ) - port map( RESET => RESET, - GSR_N => GSR_N, - CLK_125_OUT => serdes_clk_125, - CLK_125_IN => '0', -- not used - FT_TX_CLK_EN_OUT => mac_tx_clk_en, - FT_RX_CLK_EN_OUT => mac_rx_clk_en, - --connection to frame transmitter (tsmac) - FT_COL_OUT => mac_col, - FT_CRS_OUT => mac_crs, - FT_TXD_IN => pcs_txd, - FT_TX_EN_IN => pcs_tx_en, - FT_TX_ER_IN => pcs_tx_er, - --SFP Connection - SD_RXD_P_IN => SFP_RXD_P_IN, - SD_RXD_N_IN => SFP_RXD_N_IN, - SD_TXD_P_OUT => SFP_TXD_P_OUT, - SD_TXD_N_OUT => SFP_TXD_N_OUT, - SD_REFCLK_P_IN => SFP_REFCLK_P_IN, - SD_REFCLK_N_IN => SFP_REFCLK_N_IN, - SD_PRSNT_N_IN => SFP_PRSNT_N_IN, - SD_LOS_IN => SFP_LOS_IN, - SD_TXDIS_OUT => SFP_TXDIS_OUT, - -- Autonegotiation stuff - MR_ADV_ABILITY_IN => x"0020", -- full duplex only - MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, - MR_AN_PAGE_RX_OUT => pcs_an_page_rx, - MR_AN_COMPLETE_OUT => pcs_an_complete, - MR_RESET_IN => MR_RESET_IN, - MR_MODE_IN => MR_MODE_IN, - MR_AN_ENABLE_IN => '1', -- do autonegotiation - MR_RESTART_AN_IN => MR_RESTART_IN, - -- Status and control port - STAT_OP => open, - CTRL_OP => x"0000", - STAT_DEBUG => pcs_stat_debug, --open, - CTRL_DEBUG => x"0000_0000_0000_0000" + port map( + RESET => RESET, + GSR_N => GSR_N, + CLK_125_OUT => serdes_clk_125, + CLK_125_IN => '0', -- not used + FT_TX_CLK_EN_OUT => mac_tx_clk_en, + FT_RX_CLK_EN_OUT => mac_rx_clk_en, + --connection to frame transmitter (tsmac) + FT_COL_OUT => mac_col, + FT_CRS_OUT => mac_crs, + FT_TXD_IN => pcs_txd, + FT_TX_EN_IN => pcs_tx_en, + FT_TX_ER_IN => pcs_tx_er, + --SFP Connection + SD_RXD_P_IN => SFP_RXD_P_IN, + SD_RXD_N_IN => SFP_RXD_N_IN, + SD_TXD_P_OUT => SFP_TXD_P_OUT, + SD_TXD_N_OUT => SFP_TXD_N_OUT, + SD_REFCLK_P_IN => SFP_REFCLK_P_IN, + SD_REFCLK_N_IN => SFP_REFCLK_N_IN, + SD_PRSNT_N_IN => SFP_PRSNT_N_IN, + SD_LOS_IN => SFP_LOS_IN, + SD_TXDIS_OUT => SFP_TXDIS_OUT, + -- Autonegotiation stuff + MR_ADV_ABILITY_IN => x"0020", -- full duplex only + MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability, + MR_AN_PAGE_RX_OUT => pcs_an_page_rx, + MR_AN_COMPLETE_OUT => pcs_an_complete, + MR_RESET_IN => MR_RESET_IN, + MR_MODE_IN => MR_MODE_IN, + MR_AN_ENABLE_IN => '1', -- do autonegotiation + MR_RESTART_AN_IN => MR_RESTART_IN, + -- Status and control port + STAT_OP => open, + CTRL_OP => x"0000", + STAT_DEBUG => pcs_stat_debug, --open, + CTRL_DEBUG => x"0000_0000_0000_0000" ); end generate serdes_extclk_gen; stage_stat_regs(31 downto 28) <= x"e"; stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link s-tatus stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm - stage_stat_regs(19 downto 18) <= (others => '0'); + stage_stat_regs(19) <= '0'; + stage_stat_regs(18) <= link_ok; -- gk 30.09.10 stage_stat_regs(17) <= pcs_an_complete; stage_stat_regs(16) <= pcs_an_page_rx; stage_stat_regs(15 downto 0) <= pcs_an_lp_ability; @@ -1083,23 +1224,25 @@ discfrm_sync : signal_sync D_OUT => monitor_discfrm ); +-- gk 29.09.10 +-- debug fifo saves each sent frame, but drops it after receiving information that everything went fine +-- otherwise, the frame will be kept to readout via slow control +db_fifo_rst <= '1' when ((RESET = '1') or ((mac_tx_done = '1') and (discfrm_ctr = x"00000000"))) else '0'; --- reset_fifo <= '1' when RESET = '1' or pc_sos = '1' else '0'; --- --- debug_fifo : fifo_4096x9 --- port map( --- Data(7 downto 0) => pcs_txd, --- Data(8) => '0', --- WrClock => serdes_clk_125, --- RdClock => CLK, --- WrEn => pcs_tx_en, --- RdEn => dbg_rd_en, --- Reset => reset_fifo, --- RPReset => reset_fifo, --- Q => dbg_q(8 downto 0), --- Empty => open, --- Full => open --- ); +debug_fifo : fifo_4096x9 +port map( + Data(7 downto 0) => pcs_txd, + Data(8) => '0', + WrClock => serdes_clk_125, + RdClock => CLK, + WrEn => pcs_tx_en, + RdEn => dbg_rd_en, + Reset => db_fifo_rst, + RPReset => db_fifo_rst, + Q => dbg_q(8 downto 0), + Empty => open, + Full => open +); ------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd index d4a7ddf..5d554d9 100755 --- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd @@ -108,8 +108,10 @@ signal headers_ready : std_logic; signal cur_max : integer range 0 to 10; -signal ready_frames_ctr_q : std_logic_vector(15 downto 0); -signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 +signal ready_frames_ctr_q : std_logic_vector(15 downto 0); +signal ip_cs_temp_right : std_logic_vector(15 downto 0); -- gk 29.03.10 + +signal fpf_reset : std_logic; -- gk 01.01.01 begin @@ -344,9 +346,9 @@ begin end process putUdpHeadersProc; -fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET) +fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET, LINK_OK_IN) begin - if (RESET = '1') then -- gk 31.05.10 + if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 fpf_wr_en <= '0'; elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) then fpf_wr_en <= '1'; @@ -391,7 +393,7 @@ end process fpfDataProc; readyFramesCtrProc: process( CLK ) begin if rising_edge(CLK) then - if (RESET = '1') then + if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 ready_frames_ctr <= (others => '0'); elsif (constructCurrentState = CLEANUP) then ready_frames_ctr <= ready_frames_ctr + 1; @@ -399,6 +401,8 @@ begin end if; end process readyFramesCtrProc; +fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0'; -- gk 01.10.10 + FINAL_PACKET_FIFO: fifo_4096x9 port map( Data(7 downto 0) => fpf_data, @@ -407,8 +411,8 @@ port map( RdClock => RD_CLK, WrEn => fpf_wr_en, RdEn => FT_TX_RD_EN_IN, - Reset => RESET, - RPReset => RESET, + Reset => fpf_reset, + RPReset => fpf_reset, Q => fpf_q, Empty => fpf_empty, Full => fpf_full @@ -430,7 +434,7 @@ transferToRdClock : signal_sync transmitMachineProc: process( RD_CLK ) begin if( rising_edge(RD_CLK) ) then - if( RESET = '1' ) then + if( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10 transmitCurrentState <= T_IDLE; else transmitCurrentState <= transmitNextState; @@ -458,7 +462,7 @@ begin when T_TRANSMIT => bsm_trans <= x"2"; -- gk 03.08.10 - if (LINK_OK_IN = '1') and ((ft_tx_done_in = '1') or (FT_TX_DISCFRM_IN = '1'))then + if ((LINK_OK_IN = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then transmitNextState <= T_CLEANUP; elsif (LINK_OK_IN = '0') then transmitNextState <= T_PAUSE; @@ -481,7 +485,7 @@ end process transmitMachine; sopProc: process( RD_CLK ) begin if rising_edge(RD_CLK) then - if ( RESET = '1' ) then + if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10 ft_sop <= '0'; elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then ft_sop <= '1'; @@ -494,10 +498,10 @@ end process sopProc; sentFramesCtrProc: process( RD_CLK ) begin if rising_edge(RD_CLK) then - if ( RESET = '1' ) then + if ( RESET = '1' ) or (LINK_OK_IN = '0') then -- gk 01.10.10 sent_frames_ctr <= (others => '0'); -- gk 03.08.10 - elsif( ft_tx_done_in = '1' ) or (transmitCurrentState = T_PAUSE) or (FT_TX_DISCFRM_IN = '1') then + elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then sent_frames_ctr <= sent_frames_ctr + 1; end if; end if; diff --git a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd index c8220fb..ca58728 100755 --- a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd +++ b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd @@ -107,7 +107,7 @@ debug <= (others => '0'); TransmitStateMachineProc : process (TX_MAC_CLK) begin if rising_edge(TX_MAC_CLK) then - if RESET = '1' then + if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 transmitCurrentState <= T_IDLE; else transmitCurrentState <= transmitNextState; @@ -134,7 +134,7 @@ begin end if; when T_WAITFORFIFO => bsm_trans <= x"2"; - if (TX_DONE_IN = '1') or (LINK_OK_IN = '0') or (TX_DISCFRM_IN = '1') then -- gk 03.08.10 + if (TX_DONE_IN = '1') then --or (TX_DISCFRM_IN = '1') then transmitNextState <= T_IDLE; else transmitNextState <= T_WAITFORFIFO; @@ -148,7 +148,7 @@ end process TransmitStateMachine; FifoAvailProc : process (TX_MAC_CLK) begin if rising_edge(TX_MAC_CLK) then - if RESET = '1' then + if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 tx_fifoavail_i <= '0'; elsif (transmitCurrentState = T_TRANSMIT) then tx_fifoavail_i <= '1'; @@ -160,7 +160,7 @@ end process FifoAvailProc; FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, RESET) begin - if (RESET = '1') then -- gk 31.05.10 + if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10 FifoEmpty <= '1'; elsif (transmitCurrentState = T_WAITFORFIFO) then FifoEmpty <= '1'; @@ -284,7 +284,7 @@ begin macInitNextState <= I_WRITE; else macInitNextState <= I_PAUSE3; - end if; + end if; when I_ENDED => bsm_init <= x"7"; macInitNextState <= I_ENDED; diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd index d69d976..2b03703 100755 --- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd +++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd @@ -186,18 +186,18 @@ end process; -- gk 26.07.10 DATA_FIFO : fifo_64kx9 port map( - Data(7 downto 0) => PC_DATA_IN, - Data(8) => PC_END_OF_DATA_IN, - WrClock => CLK, - RdClock => CLK, - WrEn => df_wr_en, - RdEn => df_rd_en, - Reset => RESET, - RPReset => RESET, - Q(7 downto 0) => df_q, - Q(8) => load_eod, - Empty => df_empty, - Full => df_full + Data(7 downto 0) => PC_DATA_IN, + Data(8) => PC_END_OF_DATA_IN, + WrClock => CLK, + RdClock => CLK, + WrEn => df_wr_en, + RdEn => df_rd_en, + Reset => RESET, + RPReset => RESET, + Q(7 downto 0) => df_q, + Q(8) => load_eod, + Empty => df_empty, + Full => df_full ); LOAD_EOD_PROC : process(CLK) @@ -505,7 +505,7 @@ begin end process allIntCtrProc; dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, - sub_size_loaded, all_int_ctr, RESET) + sub_size_loaded, all_int_ctr, RESET, load_eod, load_eod_q) begin if (RESET = '1') then -- gk 31.05.10 df_rd_en <= '0'; @@ -517,7 +517,8 @@ begin if (bytes_loaded = max_frame_size - x"1") then df_rd_en <= '0'; -- gk 26.07.10 - elsif (load_eod = '1') or (load_eod_q = '1') then + --elsif (load_eod = '1') or (load_eod_q = '1') then + elsif (load_eod_q = '1') then df_rd_en <= '0'; -- elsif (sub_bytes_loaded = sub_size_loaded) then -- df_rd_en <= '0'; @@ -930,8 +931,6 @@ begin end if; end process subIntProc; - - debug(3 downto 0) <= constr_state; debug(7 downto 4) <= save_state; debug(11 downto 8) <= load_state; diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd index 92076fc..04545df 100644 --- a/gbe_ecp2m/trb_net16_gbe_setup.vhd +++ b/gbe_ecp2m/trb_net16_gbe_setup.vhd @@ -50,6 +50,8 @@ port( MONITOR_HDR_IN : in std_logic_vector(31 downto 0); MONITOR_FIFOS_IN : in std_logic_vector(31 downto 0); MONITOR_DISCFRM_IN : in std_logic_vector(31 downto 0); + MONITOR_LINK_DWN_IN : in std_logic_vector(31 downto 0); -- gk 30.09.10 + MONITOR_EMPTY_IN : in std_logic_vector(31 downto 0); -- gk 01.10.10 -- gk 01.06.10 DBG_IPU2GBE1_IN : in std_logic_vector(31 downto 0); DBG_IPU2GBE2_IN : in std_logic_vector(31 downto 0); @@ -70,7 +72,8 @@ port( DBG_FT1_IN : in std_logic_vector(31 downto 0); DBG_FT2_IN : in std_logic_vector(31 downto 0); DBG_FIFO_RD_EN_OUT : out std_logic; - DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0) + DBG_FIFO_Q_IN : in std_logic_vector(15 downto 0); + DBG_RESET_FIFO_OUT : out std_logic -- gk 28.09.10 ); end entity; @@ -99,6 +102,7 @@ signal ack_q : std_logic; -- gk 26.04.10 signal data_out : std_logic_vector(31 downto 0); -- gk 26.04.10 signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10 signal allow_large : std_logic; -- gk 21.07.10 +signal reset_fifo : std_logic; -- gk 28.09.10 begin @@ -121,6 +125,7 @@ begin BUS_DATA_OUT <= data_out; -- gk 26.04.10 GBE_DELAY_OUT <= delay; -- gk 28.04.10 GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10 + DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10 end if; end process OUT_PROC; @@ -148,7 +153,7 @@ begin subevent_dec <= x"0002_0001"; queue_dec <= x"0003_0062"; max_packet <= x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester - min_packet <= x"0000_0008"; -- gk 20.07.10 + min_packet <= x"0000_0007"; -- gk 20.07.10 max_frame <= x"0578"; use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured use_trbnet <= '0'; @@ -159,6 +164,7 @@ begin delay <= x"0000_0000"; -- gk 28.04.10 DBG_FIFO_RD_EN_OUT <= '0'; allow_large <= '0'; -- gk 21.07.10 + reset_fifo <= '0'; -- gk 28.09.10 elsif (BUS_WRITE_EN_IN = '1') then case BUS_ADDR_IN is @@ -223,6 +229,14 @@ begin allow_large <= '1'; end if; + -- gk 28.09.10 + when x"fe" => + if (BUS_DATA_IN = x"ffff_ffff") then + reset_fifo <= '1'; + else + reset_fifo <= '0'; + end if; + when x"ff" => if (BUS_DATA_IN = x"ffff_ffff") then reset_values <= '1'; @@ -231,25 +245,27 @@ begin end if; when others => - subevent_id <= subevent_id; - subevent_dec <= subevent_dec; - queue_dec <= queue_dec; - max_packet <= max_packet; - min_packet <= min_packet; - max_frame <= max_frame; - use_gbe <= use_gbe; - use_trbnet <= use_trbnet; - use_multievents <= use_multievents; - reset_values <= reset_values; - readout_ctr <= readout_ctr; -- gk 26.04.10 - readout_ctr_valid <= readout_ctr_valid; -- gk 26.04.10 - delay <= delay; -- gk 28.04.10 + subevent_id <= subevent_id; + subevent_dec <= subevent_dec; + queue_dec <= queue_dec; + max_packet <= max_packet; + min_packet <= min_packet; + max_frame <= max_frame; + use_gbe <= use_gbe; + use_trbnet <= use_trbnet; + use_multievents <= use_multievents; + reset_values <= reset_values; + readout_ctr <= readout_ctr; -- gk 26.04.10 + readout_ctr_valid <= readout_ctr_valid; -- gk 26.04.10 + delay <= delay; -- gk 28.04.10 DBG_FIFO_RD_EN_OUT <= '0'; - allow_large <= allow_large; + allow_large <= allow_large; + reset_fifo <= reset_fifo; -- gk 28.09.10 end case; else - reset_values <= '0'; + reset_values <= '0'; readout_ctr_valid <= '0'; -- gk 26.04.10 + --reset_fifo <= '0'; -- gk 28.09.10 end if; end if; end process WRITE_PROC; @@ -400,6 +416,12 @@ begin when x"fa" => data_out <= MONITOR_DISCFRM_IN; + when x"fb" => + data_out <= MONITOR_LINK_DWN_IN; + + when x"fc" => + data_out <= MONITOR_EMPTY_IN; + when others => data_out <= (others => '0'); end case; diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd index 71ed59d..ee61bdc 100755 --- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd +++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd @@ -49,7 +49,7 @@ port( PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0); PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0); PC_PADDING_OUT : out std_logic; - MONITOR_OUT : out std_logic_vector(191 downto 0); + MONITOR_OUT : out std_logic_vector(223 downto 0); DEBUG_OUT : out std_logic_vector(383 downto 0) ); end entity; @@ -247,10 +247,13 @@ signal read_size_q : std_logic_vector(17 downto 0); -- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked signal sf_real_wr_en : std_logic; +-- gk 01.10.10 +signal found_empty_evt : std_logic; +signal found_empty_evt_comb : std_logic; +signal found_empty_evt_ctr : std_logic_vector(31 downto 0); + begin --- Fake signals ---START_CONFIG_OUT <= '0'; -- gk 27.03.10 BANK_SELECT_OUT <= bank_select; -- gk 27.03.10 START_CONFIG_OUT <= start_config; -- gk 27.03.10 config_done <= CONFIG_DONE_IN; -- gk 29.03.10 @@ -325,6 +328,9 @@ sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or - (add_sub_state = '1') -- gk 29.03.10 save the subsubevent else '0'; +-- gk 06.08.10 +sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; + -- gk 27.03.10 do not count evt builder address as saved ipu bytes --ce_saved_ctr <= sf_wr_en; ce_saved_ctr <= '0' when addr_saved = '1' else sf_wr_en; @@ -598,8 +604,6 @@ port map( Full => sf_full, AlmostFull => sf_afull ); --- gk 06.08.10 -sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0'; ------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------ @@ -677,6 +681,7 @@ begin drop_large <= '0'; -- gk 25.07.10 drop_headers <= '0'; -- gk 25.07.10 inc_trg_ctr <= '0'; -- gk 26.07.10 + found_empty_evt <= '0'; -- gk 01.10.10 else loadCurrentState <= loadNextState; rst_rem_ctr <= rst_rem_ctr_comb; @@ -695,6 +700,7 @@ begin drop_large <= drop_large_comb; -- gk 25.07.10 drop_headers <= drop_headers_comb; -- gk 25.07.10 inc_trg_ctr <= inc_trg_ctr_comb; -- gk 26.07.10 + found_empty_evt <= found_empty_evt_comb; -- gk 01.10.10 end if; end if; end process loadMachineProc; @@ -718,6 +724,7 @@ begin drop_large_comb <= '0'; -- gk 25.07.10 drop_headers_comb <= '0'; -- gk 25.07.10 inc_trg_ctr_comb <= '0'; -- gk 26.07.10 + found_empty_evt_comb <= '0'; -- gk 01.10.10 case loadCurrentState is when LIDLE => state2 <= x"0"; @@ -752,7 +759,10 @@ begin if (pc_sub_size >= MAX_MESSAGE_SIZE_IN) then loadNextState <= PAUSE_BEFORE_DROP1; drop_large_comb <= '1'; - elsif (pc_sub_size <= MIN_MESSAGE_SIZE_IN) then + elsif (pc_sub_size = b"0000_0000_0000_00") then -- gk 01.10.10 + loadNextState <= CALCA; + found_empty_evt_comb <= '1'; + elsif (pc_sub_size < MIN_MESSAGE_SIZE_IN) then loadNextState <= PAUSE_BEFORE_DROP1; drop_small_comb <= '1'; elsif (pc_trig_nr + x"1" /= first_run_trg) then @@ -876,6 +886,7 @@ begin headers_invalid_ctr <= (others => '0'); dropped_ctr <= (others => '0'); invalid_hsize_ctr <= (others => '0'); + found_empty_evt_ctr <= (others => '0'); -- gk 01.10.10 elsif (rst_regs = '1') then invalid_hsize_lock <= '0'; elsif (drop_small = '1') then @@ -890,6 +901,9 @@ begin elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ?? invalid_hsize_ctr <= invalid_hsize_ctr + x"1"; invalid_hsize_lock <= '1'; + -- gk 01.10.10 + elsif (found_empty_evt = '1') then + found_empty_evt_ctr <= found_empty_evt_ctr + x"1"; end if; end if; end process INVALID_STATS_PROC; @@ -1197,7 +1211,7 @@ begin if rising_edge(CLK) then if (RESET = '1') then debug(81 downto 64) <= (others => '0'); - elsif (pc_sos = '1') then + elsif (loadCurrentState = DECIDE) then debug(81 downto 64) <= pc_sub_size; end if; end if; @@ -1277,6 +1291,7 @@ MONITOR_OUT(127 downto 96) <= dropped_sm_events_ctr; MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr; MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000"; MONITOR_OUT(191 downto 164) <= (others => '0'); +MONITOR_OUT(223 downto 192) <= found_empty_evt_ctr; -- gk 01.10.10 -- Outputs FEE_READ_OUT <= fee_read; -- 2.43.0