From 6eb4b90ba45b2d023e7d6db5b3c5e22ef840144f Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 13 Jun 2012 17:56:36 +0000 Subject: [PATCH] *** empty log message *** --- media_interfaces/trb_net16_med_ecp3_sfp.vhd | 4 +- media_interfaces/trb_net16_med_ecp3_sfp_4.vhd | 60 +++++++++++++++---- special/spi_ltc2600.vhd | 6 +- trb_net_components.vhd | 7 +++ 4 files changed, 62 insertions(+), 15 deletions(-) diff --git a/media_interfaces/trb_net16_med_ecp3_sfp.vhd b/media_interfaces/trb_net16_med_ecp3_sfp.vhd index faa05ce..61d19d4 100644 --- a/media_interfaces/trb_net16_med_ecp3_sfp.vhd +++ b/media_interfaces/trb_net16_med_ecp3_sfp.vhd @@ -605,7 +605,7 @@ refclk2core_out <= '0'; ); end generate; - gen_serdes_1_200 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate + gen_serdes_1_200 : if SERDES_NUM = 1 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES and USE_CTC = c_NO generate THE_SERDES: sfp_1_200_int port map( HDINP_CH1 => sd_rxd_p_in, @@ -620,7 +620,7 @@ refclk2core_out <= '0'; RX_FULL_CLK_CH1 => open, RX_HALF_CLK_CH1 => ff_rxhalfclk, TX_FULL_CLK_CH1 => open, - TX_HALF_CLK_CH1 => clk_tx, + TX_HALF_CLK_CH1 => ff_txhalfclk, TXDATA_CH1 => tx_data, TX_K_CH1 => tx_k, diff --git a/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd b/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd index c01f1c9..ee8c5a3 100644 --- a/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd +++ b/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd @@ -42,7 +42,14 @@ entity trb_net16_med_ecp3_sfp_4 is SD_REFCLK_N_IN : in std_logic; SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; -- Status and control port STAT_OP : out std_logic_vector (4*16-1 downto 0); CTRL_OP : in std_logic_vector (4*16-1 downto 0); @@ -292,7 +299,17 @@ architecture arch_ecp3_sfp_4 of trb_net16_med_ecp3_sfp_4 is signal clk_tx : std_logic; signal clk_rx : std_logic; signal clk_ref : std_logic; - + + signal sci_ch_i : std_logic_vector(3 downto 0); + signal sci_addr_i : std_logic_vector(8 downto 0); + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal sci_read_i : std_logic; + signal sci_write_i : std_logic; + signal sci_write_shift_i : std_logic_vector(2 downto 0); + signal sci_read_shift_i : std_logic_vector(2 downto 0); + + attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_keep of led_counter : signal is true; @@ -399,6 +416,25 @@ gen_LSM : for i in 0 to 3 generate end generate; + PROC_SCI : process begin + wait until rising_edge(clk_sys); + if SCI_READ = '1' or SCI_WRITE = '1' then + sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and (SCI_READ or SCI_WRITE); + sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and (SCI_READ or SCI_WRITE); + sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and (SCI_READ or SCI_WRITE); + sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and (SCI_READ or SCI_WRITE); + sci_addr_i <= SCI_ADDR; + sci_data_in_i <= SCI_DATA_IN; + end if; + sci_read_shift_i <= sci_read_shift_i(1 downto 0) & SCI_READ; + sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE; + SCI_DATA_OUT <= sci_data_out_i; + end process; + + sci_write_i <= or_all(sci_write_shift_i); + sci_read_i <= or_all(sci_read_shift_i); + SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2); + -- Instantiation of serdes module gen_serdes_200 : if FREQUENCY = 200 generate THE_SERDES: serdes_full_ctc @@ -493,16 +529,16 @@ gen_serdes_200 : if FREQUENCY = 200 generate TX_DIV2_MODE_CH3_C => '0', --full rate RX_DIV2_MODE_CH3_C => '0', --full rate - SCI_WRDATA => (others => '0'), - SCI_RDDATA => open, - SCI_ADDR => (others => '0'), - SCI_SEL_QUAD => '0', - SCI_SEL_CH0 => '0', - SCI_SEL_CH1 => '0', - SCI_SEL_CH2 => '0', - SCI_SEL_CH3 => '0', - SCI_RD => '0', - SCI_WRN => '0', + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i(5 downto 0), + SCI_SEL_QUAD => sci_addr_i(8), + SCI_SEL_CH0 => sci_ch_i(0), + SCI_SEL_CH1 => sci_ch_i(1), + SCI_SEL_CH2 => sci_ch_i(2), + SCI_SEL_CH3 => sci_ch_i(3), + SCI_RD => sci_read_i, + SCI_WRN => sci_write_i, TX_SERDES_RST_C => CLEAR, TX_SYNC_QD_C => '0', diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd index 5fb53c5..f3c317c 100644 --- a/special/spi_ltc2600.vhd +++ b/special/spi_ltc2600.vhd @@ -38,7 +38,7 @@ architecture spi_ltc2600_arch of spi_ltc2600 is signal spi_sck : std_logic; signal spi_sd : std_logic; - signal word_count : integer range 0 to 15; + signal word_count : integer range 0 to 31; signal bit_count : integer range 0 to 31; signal time_count : integer range 0 to 7; @@ -100,6 +100,7 @@ begin time_count <= 7; fsm_state <= WAIT_STATE; spi_cs <= '0'; + spi_sck <= '1'; else spi_cs <= '1'; spi_sck <= '1'; @@ -142,6 +143,9 @@ begin time_count <= time_count - 1; end if; end case; + if RESET_IN = '1' then + fsm_state <= IDLE; + end if; end process; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index dde31fd..8d6658c 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2130,6 +2130,13 @@ component trb_net16_med_ecp3_sfp_4 is SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + --Control Interface + SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); + SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0'); + SCI_READ : in std_logic := '0'; + SCI_WRITE : in std_logic := '0'; + SCI_ACK : out std_logic := '0'; -- Status and control port STAT_OP : out std_logic_vector (4*16-1 downto 0); CTRL_OP : in std_logic_vector (4*16-1 downto 0); -- 2.43.0