From 6ec03ba45650ddd56bc717ece1a7e71613ae337b Mon Sep 17 00:00:00 2001 From: Your Name Date: Thu, 23 Mar 2017 17:40:57 +0100 Subject: [PATCH] updated gbe registers in trb3doc --- gbe.tex | 66 ++++++++++++------------- trb3/GbeDataReadout.tex | 106 +++++++++++++--------------------------- 2 files changed, 65 insertions(+), 107 deletions(-) diff --git a/gbe.tex b/gbe.tex index 4f9a5b0..08e015a 100644 --- a/gbe.tex +++ b/gbe.tex @@ -21,19 +21,16 @@ The GbE interface itself has two registers to control the link status, available \hline \textbf{Address} & \textbf{Name} & \textbf{Description} \\ \hline\hline -0x8300 & SubEventID & The ID is written in each SubEventHeader to identify the source of data (default: x"0000_00cf") \\ -0x8301 & SubEventDecoding & Information sent in the SubEventHeader (default: x"0002_0001") \\ -0x8302 & QueueDecoding & Information sent in the HadesTuQueue (default: x"0003_0062") \\ -0x8304 & MaxFrameSize & Maximum size of a Ethernet packet (default: 1400) \\ -0x8305 & UseGbE & Enable sending data over GbE (default: 0) \\ +0x8300 & SubEventID & The ID is written in each SubEventHeader to identify the source of data \\ +0x8301 & SubEventDecoding & Information sent in the SubEventHeader \\ +0x8302 & QueueDecoding & Information sent in the HadesTuQueue \\ +0x8303 & MaxPacketSize & Maximum size of the UDP packet (default: 0xFDE8 = 65000) \\ +0x8304 & MaxFrameSize & Maximum size of a Ethernet packet (default: 0x578 = 1400) \\ +0x8305 & UseGbE & Enable sending data over GbE (default: 1) \\ +0x8306 & UseTrbNet & Forward data over TrbNet (default: 0) \\ 0x8307 & MultiEventQueue & Enable packing several events into one event queue (default: 0) \\ 0x8308 & TriggerCounter & The internal, 24bit trigger counter used for the SubEventHeader (default: 0) \\ -0x8309 & EnableRX & Enables/disables reception of frames (default: 1)\\ -0x830B & IncludeTType & Include Trigger Type in decoding field (default: 0)\\ -0x830C & MaxSubSize & Max Subevent size, larger are discarded (default: 59800)\\ -0x830E & MaxSubsInQueue & Max number of Subevents in one Queue (default: 200)\\ -0x830F & MaxSubSizeInQ & Max Subevent size, after which the Queue is closed immediately (default: 32000)\\ -0x8310 & MaxQueueSize & Max size of a Queue (default: 60000) \\ +0x8309 & DelayCounter & Microseconds delay between sending two UDP packets \\ 0x83FF & ResetDefault & When written to 0xFFFFFFFF: all values are reset to default \\ \hline \end{tabularx} @@ -54,11 +51,11 @@ The GbE interface itself has two registers to control the link status, available 0x81S1 & DestMacMsb & Bit 15..0: Higher 16 bit of the destination MAC, Bit 31..16: reserved\\ 0x81S2 & DestIP & Destination IP \\ 0x81S3 & DestUdpPort & Bit 15..0: Destination UDP port, Bit 31..16: reserved \\ -0x81S4 & SrcMacLsb & OBSOLETE (address automatically generated) \\ -0x81S5 & SrcMacMsb & OBSOLETE (address automatically generated) \\ -0x81S6 & SrcIP & OBSOLETE (address aacquired from DHCP) \\ +0x81S4 & SrcMacLsb & Lower 32 bits of the source MAC address \\ +0x81S5 & SrcMacMsb & Bit 15..0: Higher 16 bit of the source MAC, Bit 31..16: reserved \\ +0x81S6 & SrcIP & Source IP address \\ 0x81S7 & SrcUdpPort & Bit 15..0: Source UDP port, Bit 31..16: reserved \\ -0x81S8 & MtuSize & OBSOLETE (switched to control register 0x8304) \\ +0x81S8 & MtuSize & Bit 15..0: MTU size, Bit 31..16: reserved \\ \hline \end{tabularx} \caption{Memory map for GbE Ethernet settings. The third digit is the EventBuilder number, allowing to stor 16 different settings that are selected by the IPU request information word.} @@ -66,27 +63,24 @@ The GbE interface itself has two registers to control the link status, available \end{center} \end{table} -- Status registers: - -\begin{table}[hbtp] -\begin{center} -\begin{tabularx}{\textwidth}{|l|l|X|} -\hline -\textbf{Address} & \textbf{Name} & \textbf{Description} \\ -\hline\hline -0x83E0 & RxBytes & Received bytes counter \\ -0x83E1 & RxFrames & Received frames counter \\ -0x83E2 & TxBytes & Transmitted bytes counter \\ -0x83E3 & TxFrames & Transmitted frames counter \\ -0x83E4 & TxPackets & Transmitted packets counter \\ -0x83E5 & RxDropped & Dropped RX frames counter \\ -\hline -\end{tabularx} -\caption{Memory map for GbE Ethernet status registers.} -\label{GbEEBSettings} -\end{center} -\end{table} - +- Link control + +\begin{description} + \item[0x8000: Control Register] PHY control register. Each of the bits has to be reset manually after use + \begin{description} + \item[Bit 0]Restart Autonegotiation + \item[Bit 1]PHY mode (must be 0) + \item[Bit 3]PHY reset + \end{description} + \item[0x8200: Status Register] GbE link status register (detailed explanation: t.b.d.) + \begin{description} + \item[Bit 15..0] Link partner page + \item[Bit 16] Link partner page received (strobe signal) + \item[Bit 17] Autonegotiation completed + \item[Bit 23..20] Reset state machine status + \item[Bit 27..24] Link status + \end{description} +\end{description} \begin{figure} \centering diff --git a/trb3/GbeDataReadout.tex b/trb3/GbeDataReadout.tex index eb96426..b5a9379 100644 --- a/trb3/GbeDataReadout.tex +++ b/trb3/GbeDataReadout.tex @@ -32,15 +32,17 @@ Each TRB3 board has a unique MAC address which is constructed in following way: \begin{center} \begin{tabular}{|l|l|} \hline - 0x81X0 + offset & Description \\ \hline - 0 & destination MAC address 32 lower bits \\ \hline - 1 & destination MAC address 16 upper bits \\ \hline - 2 & destination IP address \\ \hline - 3 & destination UDP port \\ \hline - 4 & source MAC address 32 lower bits \\ \hline - 5 & source MAC address 16 upper bits \\ \hline - 6 & source IP address \\ \hline - 7 & source UDP port \\ \hline + Address & Name & Description \\ \hline + + 0x81X0 & DestMacLsb & Lower 32 bits of the destination MAC address \\ + 0x81X1 & DestMacMsb & Bit 15..0: Higher 16 bit of the destination MAC, Bit 31..16: reserved\\ + 0x81X2 & DestIP & Destination IP \\ + 0x81X3 & DestUdpPort & Bit 15..0: Destination UDP port, Bit 31..16: reserved \\ + 0x81X4 & SrcMacLsb & OBSOLETE (address automatically generated) \\ + 0x81X5 & SrcMacMsb & OBSOLETE (address automatically generated) \\ + 0x81X6 & SrcIP & OBSOLETE (address aacquired from DHCP) \\ + 0x81X7 & SrcUdpPort & Bit 15..0: Source UDP port, Bit 31..16: reserved \\ + 0x81X8 & MtuSize & OBSOLETE (switched to control register 0x8304) \\ \end{tabular} \caption[Addressing registers map]{Addressing registers map} \end{center} @@ -56,18 +58,23 @@ Some header values as well as operation mechanics can be changed and adjusted, h \begin{center} \begin{tabular}{|l|l|l|} \hline - 0x8300 + offset & Description & Default value\\ \hline - 0 & Subevent ID value for the header field & 0x000000cf \\ \hline - 1 & Subevent decoding value for the header field & 0x00020001 \\ \hline - 2 & Queue decoding value for the header field & 0x00030064 \\ \hline - 4 & Max Ethernet frame size (MTU) can be set up to 4kB & 0x00000578 \\ \hline - 5 & Enable GbE data transport & 0x0 (DISABLED BY DEFAULT) \\ \hline - 7 & Enable multi-event mode & 0x0 \\ \hline - 8 & Update readout counter value & 0x000000 \\ \hline - 9 & Enable RX channel & 0x1 \\ \hline - A & Include additional SlowControl data header & 0x1 \\ \hline - B & Include trigger type in the decoding field & 0x0 \\ \hline - FF & Reset value the their default values & 0x0 \\ \hline + Address & Name & Description\\ \hline + + 0x8300 & SubEventID & The ID is written in each SubEventHeader to identify the source of data (default: x"0000_00cf") \\ + 0x8301 & SubEventDecoding & Information sent in the SubEventHeader (default: x"0002_0001") \\ + 0x8302 & QueueDecoding & Information sent in the HadesTuQueue (default: x"0003_0062") \\ + 0x8304 & MaxFrameSize & Maximum size of a Ethernet packet (default: 1400) \\ + 0x8305 & UseGbE & Enable sending data over GbE (default: 0) \\ + 0x8307 & MultiEventQueue & Enable packing several events into one event queue (default: 0) \\ + 0x8308 & TriggerCounter & The internal, 24bit trigger counter used for the SubEventHeader (default: 0) \\ + 0x8309 & EnableRX & Enables/disables reception of frames (default: 1)\\ + 0x830B & IncludeTType & Include Trigger Type in decoding field (default: 0)\\ + 0x830C & MaxSubSize & Max Subevent size, larger are discarded (default: 59800)\\ + 0x830E & MaxSubsInQueue & Max number of Subevents in one Queue (default: 200)\\ + 0x830F & MaxSubSizeInQ & Max Subevent size, after which the Queue is closed immediately (default: 32000)\\ + 0x8310 & MaxQueueSize & Max size of a Queue (default: 60000) \\ + 0x83FF & ResetDefault & When written to 0xFFFFFFFF: all values are reset to default \\ + \end{tabular} \caption[Control registers map]{Control registers map} \end{center} @@ -83,59 +90,16 @@ The operation of the entire GbE module as well as individual protocols can be mo \begin{center} \begin{tabular}{|l|l|} \hline - 0x8300 + offset & Description \\ \hline - e0 & Received bytes counter \\ \hline - e1 & Received Eth frames counter \\ \hline - e2 & Transmitted bytes counter \\ \hline - e3 & Transmitted Eth frames counter \\ \hline - e4 & Transmitted packets counter \\ \hline - e5 & Dropped RX frames counter \\ \hline - a0 & SlowControl received frames counter \\ \hline - a1 & SlowControl received bytes counter \\ \hline - a2 & SlowControl transmitted frames counter \\ \hline - a3 & SlowControl transmitted bytes counter \\ \hline - a4[0] & SlowControl rx fifo full \\ \hline - a4[1] & SlowControl rx fifo empty \\ \hline - a4[2] & SlowControl tx fifo full \\ \hline - a4[3] & SlowControl tx fifo empty \\ \hline - a4[7:4] & SlowControl state machine \\ \hline - b0 & TrbNetData received frames counter = 0 \\ \hline - b1 & TrbNetData received bytes counter = 0 \\ \hline - b2 & TrbNetData transmitted frames counter \\ \hline - b3 & TrbNetData transmitted bytes counter \\ \hline - b4[3:0] & IpuInterface receiving state machine \\ \hline - b4[7:4] & IpuInterface loading state machine \\ \hline - b4[8] & Split fifo empty flag \\ \hline - b4[9] & Split fifo almost empty flag \\ \hline - b4[10] & Split fifo full flag \\ \hline - b4[11] & Split fifo almost full flag \\ \hline - b5[3:0] & Packet constructor constructing state machine \\ \hline - b5[7:4] & Packet constructor loading state machine \\ \hline - b5[11:8] & Packet constructor headers state machine \\ \hline - b5[12] & Data fifo full flag \\ \hline - b5[13] & Data fifo empty flag \\ \hline - b5[14] & Headers fifo full flag \\ \hline - b5[15] & Headers fifo empty flag \\ \hline - f3 & Same as e2 for backwards compatibility \\ \hline - f4 & Same as e3 for backwards compatibility \\ \hline + Address & Name & Description\\ \hline + 0x83E0 & RxBytes & Received bytes counter \\ + 0x83E1 & RxFrames & Received frames counter \\ + 0x83E2 & TxBytes & Transmitted bytes counter \\ + 0x83E3 & TxFrames & Transmitted frames counter \\ + 0x83E4 & TxPackets & Transmitted packets counter \\ + 0x83E5 & RxDropped & Dropped RX frames counter \\ \end{tabular} \caption[Monitoring registers map]{Monitoring registers map} \end{center} \end{table} -\newpage - -Additionally there are two register groups, one for SlowControl and another for TrbNetData that can be used for monitoring of outgoing packet sizes. Each group consists of 32 x 32bits registers, where each register represents a counter of packets with size within a specified range. The size difference between two registers is 2kB, so the first register is a counter for packets with sizes from 0 to 2kB and so on. - -\begin{table}[!htbp] -\begin{center} - \begin{tabular}{|l|l|} - \hline - Register block base & Description \\ \hline - 0x8360 & Start of the 32 registers block for SlowControl packet histograming \\ \hline - 0x8380 & Start of the 32 registers block for TrbNetData packet histograming \\ \hline - \end{tabular} - \caption[Histograming registers map]{Histograming registers map} -\end{center} -\end{table} -- 2.43.0