From 6f19c6e2bfe4b4e59c5cec8843a05687200008ca Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Wed, 14 Jun 2017 16:19:18 +0200
Subject: [PATCH] Add configuration registers for ADCuc

---
 atmega32u4/adcuc/main.c | 43 +++++++++++++++++++++++++----------------
 1 file changed, 26 insertions(+), 17 deletions(-)

diff --git a/atmega32u4/adcuc/main.c b/atmega32u4/adcuc/main.c
index 8892663..f6139ab 100644
--- a/atmega32u4/adcuc/main.c
+++ b/atmega32u4/adcuc/main.c
@@ -80,9 +80,9 @@ void send_answer_hex(uint16_t v) {
   }
     
     
-//Buttons 0 1 2 3:  PD1, PD0, PB7, PB3
+
 ISR(TIMER0_OVF_vect) {
-	time++;
+  time++;
   asm volatile("wdr");
   }  
 
@@ -115,34 +115,43 @@ __attribute__((naked)) int main(void) {
   CLKPR = (1 << CLKPS0); // prescaler 2
   usb_init(); 
   
-//Channels 0 1 2 3: PD4, PB6, PF6, PF1
-//Buttons 0 1 2 3:  PD1, PD0, PB7, PB3
-//ADC ref:          PF0(0,0)
-//Sense 0 1 2 3:    PD6(9,3+MUX5), PD7(10,4+MUX5), PF7(7,7), PF4(4,4) (channel, ADMUX value)
-//LED 0 1:          PB2, PB1
-//Select:           PD5
 
+  
  // Configure ports
-    
+ //LED:     PF6, PF5
+ //Switch:  PF4, PF7
+ //IO: PD4, PD6, PD7, PB5, PB6, PC6, PC7, PE2
+ //UART: RX PD2, TX PD3
+ //SPI: out: PB2, PB1 ; in: PB3
+ //CS: PB7, PB0
+  
   MCUCR |= (1<<JTD);
   MCUCR |= (1<<JTD);  //yes, twice
   
-  PORTB = 0b10001110;
-  DDRB  = 0b01000110;
+  PORTB = 0b11011001;
+  DDRB  = 0b10000111;
 
-  PORTD = 0b00001111;
-  DDRD  = 0b00110000;
+  PORTD = 0b11110111;
+  DDRD  = 0b00001000;
 
-  PORTF = 0b00000000;
-  DDRF  = 0b01000010;
+  PORTF = 0b11010011;
+  DDRF  = 0b01100000;
 
+  PORTC = 0b11000000;
+  DDRC  = 0b00000000;
+
+  PORTE = 0b01000100;
+  DDRE  = 0b00000000;
   
   //limit[3]  |= eeprom_read_byte((uint8_t*)0x26);  
   
-  //Timer0 at ~122 Hz overflow for ADC control and buttons
-  TCCR0B = (4 << CS00);
+  //Timer0 at ~488 Hz overflow for ADC control and buttons
+  TCCR0B = (1 << CS01) | (1 << CS00);
   TIMSK0 = (1 << TOIE0); //Overflow interrupt`
 
+  
+  //SPI  2 MHz, Master, mode 1, no interrupts
+  SPCR = (1 << SPE) | (1 << MSTR) | (0 << CPOL) | (1 << CPHA) | ( 0 << SPR0);
 
   //Watchdog at .5 seconds
   WDTCSR = (1<<WDCE);
-- 
2.43.0